virgl: add virgl_shader_binding_state
[mesa.git] / src / gallium / drivers / virgl / virgl_context.h
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef VIRGL_CONTEXT_H
24 #define VIRGL_CONTEXT_H
25
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "util/slab.h"
29 #include "util/list.h"
30
31 #include "virgl_transfer_queue.h"
32
33 struct pipe_screen;
34 struct tgsi_token;
35 struct u_upload_mgr;
36 struct virgl_cmd_buf;
37 struct virgl_vertex_elements_state;
38
39 struct virgl_sampler_view {
40 struct pipe_sampler_view base;
41 uint32_t handle;
42 };
43
44 struct virgl_so_target {
45 struct pipe_stream_output_target base;
46 uint32_t handle;
47 };
48
49 struct virgl_rasterizer_state {
50 struct pipe_rasterizer_state rs;
51 uint32_t handle;
52 };
53
54 struct virgl_shader_binding_state {
55 struct pipe_sampler_view *views[16];
56 uint32_t view_enabled_mask;
57 };
58
59 struct virgl_context {
60 struct pipe_context base;
61 struct virgl_cmd_buf *cbuf;
62 unsigned cbuf_initial_cdw;
63
64 struct virgl_shader_binding_state shader_bindings[PIPE_SHADER_TYPES];
65
66 struct virgl_vertex_elements_state *vertex_elements;
67
68 struct pipe_framebuffer_state framebuffer;
69
70 struct slab_child_pool transfer_pool;
71 struct virgl_transfer_queue queue;
72 struct u_upload_mgr *uploader;
73 bool encoded_transfers;
74
75 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
76 unsigned num_vertex_buffers;
77 boolean vertex_array_dirty;
78
79 struct virgl_rasterizer_state rs_state;
80 struct virgl_so_target so_targets[PIPE_MAX_SO_BUFFERS];
81 unsigned num_so_targets;
82
83 struct pipe_resource *ubos[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];
84
85 struct pipe_resource *ssbos[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
86 struct pipe_resource *images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
87 uint32_t num_draws, num_compute;
88
89 struct pipe_resource *atomic_buffers[PIPE_MAX_HW_ATOMIC_BUFFERS];
90
91 struct primconvert_context *primconvert;
92 uint32_t hw_sub_ctx_id;
93 };
94
95 static inline struct virgl_sampler_view *
96 virgl_sampler_view(struct pipe_sampler_view *view)
97 {
98 return (struct virgl_sampler_view *)view;
99 };
100
101 static inline struct virgl_so_target *
102 virgl_so_target(struct pipe_stream_output_target *target)
103 {
104 return (struct virgl_so_target *)target;
105 }
106
107 static inline struct virgl_context *virgl_context(struct pipe_context *ctx)
108 {
109 return (struct virgl_context *)ctx;
110 }
111
112 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
113 void *priv, unsigned flags);
114
115 void virgl_init_blit_functions(struct virgl_context *vctx);
116 void virgl_init_query_functions(struct virgl_context *vctx);
117 void virgl_init_so_functions(struct virgl_context *vctx);
118
119 struct tgsi_token *virgl_tgsi_transform(struct virgl_context *vctx, const struct tgsi_token *tokens_in);
120
121 #endif