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virgl: unwrap the includes
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24
25 #include "util/u_memory.h"
26 #include "util/u_math.h"
27 #include "pipe/p_state.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30
31 #include "virgl_context.h"
32 #include "virgl_encode.h"
33 #include "virgl_protocol.h"
34 #include "virgl_resource.h"
35 #include "virgl_screen.h"
36
37 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
38 uint32_t dword)
39 {
40 int len = (dword >> 16);
41
42 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
43 ctx->base.flush(&ctx->base, NULL, 0);
44
45 virgl_encoder_write_dword(ctx->cbuf, dword);
46 return 0;
47 }
48
49 static void virgl_encoder_write_res(struct virgl_context *ctx,
50 struct virgl_resource *res)
51 {
52 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
53
54 if (res && res->hw_res)
55 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
56 else {
57 virgl_encoder_write_dword(ctx->cbuf, 0);
58 }
59 }
60
61 int virgl_encode_bind_object(struct virgl_context *ctx,
62 uint32_t handle, uint32_t object)
63 {
64 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
65 virgl_encoder_write_dword(ctx->cbuf, handle);
66 return 0;
67 }
68
69 int virgl_encode_delete_object(struct virgl_context *ctx,
70 uint32_t handle, uint32_t object)
71 {
72 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
73 virgl_encoder_write_dword(ctx->cbuf, handle);
74 return 0;
75 }
76
77 int virgl_encode_blend_state(struct virgl_context *ctx,
78 uint32_t handle,
79 const struct pipe_blend_state *blend_state)
80 {
81 uint32_t tmp;
82 int i;
83
84 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
85 virgl_encoder_write_dword(ctx->cbuf, handle);
86
87 tmp =
88 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
89 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
90 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
91 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
92 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
93
94 virgl_encoder_write_dword(ctx->cbuf, tmp);
95
96 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
97 virgl_encoder_write_dword(ctx->cbuf, tmp);
98
99 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
100 tmp =
101 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
102 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
103 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
104 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
105 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
106 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
107 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
108 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
109 virgl_encoder_write_dword(ctx->cbuf, tmp);
110 }
111 return 0;
112 }
113
114 int virgl_encode_dsa_state(struct virgl_context *ctx,
115 uint32_t handle,
116 const struct pipe_depth_stencil_alpha_state *dsa_state)
117 {
118 uint32_t tmp;
119 int i;
120 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
121 virgl_encoder_write_dword(ctx->cbuf, handle);
122
123 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
124 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
125 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
126 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
127 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
128 virgl_encoder_write_dword(ctx->cbuf, tmp);
129
130 for (i = 0; i < 2; i++) {
131 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
132 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
133 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
134 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
135 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
136 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
137 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
138 virgl_encoder_write_dword(ctx->cbuf, tmp);
139 }
140
141 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
142 return 0;
143 }
144 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
145 uint32_t handle,
146 const struct pipe_rasterizer_state *state)
147 {
148 uint32_t tmp;
149
150 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
151 virgl_encoder_write_dword(ctx->cbuf, handle);
152
153 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
154 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
155 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
156 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
157 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
158 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
159 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
160 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
161 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
162 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
163 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
164 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
165 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
166 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
167 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
168 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
169 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
170 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
171 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
172 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
173 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
174 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
175 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
176 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
177 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
178 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
179 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
180 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule);
181
182 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
183 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
184 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
185 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
186 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
187 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
188 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
189 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
190 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
191 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
192 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
193 return 0;
194 }
195
196 static void virgl_emit_shader_header(struct virgl_context *ctx,
197 uint32_t handle, uint32_t len,
198 uint32_t type, uint32_t offlen,
199 uint32_t num_tokens)
200 {
201 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
202 virgl_encoder_write_dword(ctx->cbuf, handle);
203 virgl_encoder_write_dword(ctx->cbuf, type);
204 virgl_encoder_write_dword(ctx->cbuf, offlen);
205 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
206 }
207
208 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
209 const struct pipe_stream_output_info *so_info)
210 {
211 int num_outputs = 0;
212 int i;
213 uint32_t tmp;
214
215 if (so_info)
216 num_outputs = so_info->num_outputs;
217
218 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
219 if (num_outputs) {
220 for (i = 0; i < 4; i++)
221 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
222
223 for (i = 0; i < so_info->num_outputs; i++) {
224 tmp =
225 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
226 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
227 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
228 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
229 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
230 virgl_encoder_write_dword(ctx->cbuf, tmp);
231 virgl_encoder_write_dword(ctx->cbuf, 0);
232 }
233 }
234 }
235
236 int virgl_encode_shader_state(struct virgl_context *ctx,
237 uint32_t handle,
238 uint32_t type,
239 const struct pipe_stream_output_info *so_info,
240 const struct tgsi_token *tokens)
241 {
242 char *str, *sptr;
243 uint32_t shader_len, len;
244 bool bret;
245 int num_tokens = tgsi_num_tokens(tokens);
246 int str_total_size = 65536;
247 int retry_size = 1;
248 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
249 bool first_pass;
250 str = CALLOC(1, str_total_size);
251 if (!str)
252 return -1;
253
254 do {
255 int old_size;
256
257 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
258 if (bret == false) {
259 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
260 old_size = str_total_size;
261 str_total_size = 65536 * ++retry_size;
262 str = REALLOC(str, old_size, str_total_size);
263 if (!str)
264 return -1;
265 }
266 } while (bret == false && retry_size < 10);
267
268 if (bret == false)
269 return -1;
270
271 shader_len = strlen(str) + 1;
272
273 left_bytes = shader_len;
274
275 base_hdr_size = 5;
276 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
277 first_pass = true;
278 sptr = str;
279 while (left_bytes) {
280 uint32_t length, offlen;
281 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
282 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
283 ctx->base.flush(&ctx->base, NULL, 0);
284
285 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
286
287 length = MIN2(thispass, left_bytes);
288 len = ((length + 3) / 4) + hdr_len;
289
290 if (first_pass)
291 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
292 else
293 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
294
295 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
296
297 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
298
299 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
300
301 sptr += length;
302 first_pass = false;
303 left_bytes -= length;
304 }
305
306 FREE(str);
307 return 0;
308 }
309
310
311 int virgl_encode_clear(struct virgl_context *ctx,
312 unsigned buffers,
313 const union pipe_color_union *color,
314 double depth, unsigned stencil)
315 {
316 int i;
317
318 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
319 virgl_encoder_write_dword(ctx->cbuf, buffers);
320 for (i = 0; i < 4; i++)
321 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
322 virgl_encoder_write_qword(ctx->cbuf, *(uint64_t *)&depth);
323 virgl_encoder_write_dword(ctx->cbuf, stencil);
324 return 0;
325 }
326
327 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
328 const struct pipe_framebuffer_state *state)
329 {
330 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
331 int i;
332
333 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
334 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
335 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
336 for (i = 0; i < state->nr_cbufs; i++) {
337 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
338 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
339 }
340
341 return 0;
342 }
343
344 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
345 int start_slot,
346 int num_viewports,
347 const struct pipe_viewport_state *states)
348 {
349 int i,v;
350 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
351 virgl_encoder_write_dword(ctx->cbuf, start_slot);
352 for (v = 0; v < num_viewports; v++) {
353 for (i = 0; i < 3; i++)
354 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
355 for (i = 0; i < 3; i++)
356 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
357 }
358 return 0;
359 }
360
361 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
362 uint32_t handle,
363 unsigned num_elements,
364 const struct pipe_vertex_element *element)
365 {
366 int i;
367 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
368 virgl_encoder_write_dword(ctx->cbuf, handle);
369 for (i = 0; i < num_elements; i++) {
370 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
371 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
372 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
373 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
374 }
375 return 0;
376 }
377
378 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
379 unsigned num_buffers,
380 const struct pipe_vertex_buffer *buffers)
381 {
382 int i;
383 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
384 for (i = 0; i < num_buffers; i++) {
385 struct virgl_resource *res = virgl_resource(buffers[i].buffer);
386 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
387 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
388 virgl_encoder_write_res(ctx, res);
389 }
390 return 0;
391 }
392
393 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
394 const struct pipe_index_buffer *ib)
395 {
396 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
397 struct virgl_resource *res = NULL;
398 if (ib)
399 res = virgl_resource(ib->buffer);
400
401 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
402 virgl_encoder_write_res(ctx, res);
403 if (ib) {
404 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
405 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
406 }
407 return 0;
408 }
409
410 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
411 const struct pipe_draw_info *info)
412 {
413 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, VIRGL_DRAW_VBO_SIZE));
414 virgl_encoder_write_dword(ctx->cbuf, info->start);
415 virgl_encoder_write_dword(ctx->cbuf, info->count);
416 virgl_encoder_write_dword(ctx->cbuf, info->mode);
417 virgl_encoder_write_dword(ctx->cbuf, info->indexed);
418 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
419 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
420 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
421 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
422 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
423 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
424 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
425 if (info->count_from_stream_output)
426 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
427 else
428 virgl_encoder_write_dword(ctx->cbuf, 0);
429 return 0;
430 }
431
432 int virgl_encoder_create_surface(struct virgl_context *ctx,
433 uint32_t handle,
434 struct virgl_resource *res,
435 const struct pipe_surface *templat)
436 {
437 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
438 virgl_encoder_write_dword(ctx->cbuf, handle);
439 virgl_encoder_write_res(ctx, res);
440 virgl_encoder_write_dword(ctx->cbuf, templat->format);
441 if (templat->texture->target == PIPE_BUFFER) {
442 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
443 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
444
445 } else {
446 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
447 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
448 }
449 return 0;
450 }
451
452 int virgl_encoder_create_so_target(struct virgl_context *ctx,
453 uint32_t handle,
454 struct virgl_resource *res,
455 unsigned buffer_offset,
456 unsigned buffer_size)
457 {
458 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
459 virgl_encoder_write_dword(ctx->cbuf, handle);
460 virgl_encoder_write_res(ctx, res);
461 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
462 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
463 return 0;
464 }
465
466 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
467 struct virgl_resource *res,
468 unsigned level, unsigned usage,
469 const struct pipe_box *box,
470 unsigned stride, unsigned layer_stride)
471 {
472 virgl_encoder_write_res(ctx, res);
473 virgl_encoder_write_dword(ctx->cbuf, level);
474 virgl_encoder_write_dword(ctx->cbuf, usage);
475 virgl_encoder_write_dword(ctx->cbuf, stride);
476 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
477 virgl_encoder_write_dword(ctx->cbuf, box->x);
478 virgl_encoder_write_dword(ctx->cbuf, box->y);
479 virgl_encoder_write_dword(ctx->cbuf, box->z);
480 virgl_encoder_write_dword(ctx->cbuf, box->width);
481 virgl_encoder_write_dword(ctx->cbuf, box->height);
482 virgl_encoder_write_dword(ctx->cbuf, box->depth);
483 }
484
485 int virgl_encoder_inline_write(struct virgl_context *ctx,
486 struct virgl_resource *res,
487 unsigned level, unsigned usage,
488 const struct pipe_box *box,
489 const void *data, unsigned stride,
490 unsigned layer_stride)
491 {
492 uint32_t size = (stride ? stride : box->width) * box->height;
493 uint32_t length, thispass, left_bytes;
494 struct pipe_box mybox = *box;
495
496 length = 11 + (size + 3) / 4;
497 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
498 if (box->height > 1 || box->depth > 1) {
499 debug_printf("inline transfer failed due to multi dimensions and too large\n");
500 assert(0);
501 }
502 }
503
504 left_bytes = size;
505 while (left_bytes) {
506 if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
507 ctx->base.flush(&ctx->base, NULL, 0);
508
509 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
510
511 length = MIN2(thispass, left_bytes);
512
513 mybox.width = length;
514 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
515 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
516 virgl_encoder_write_block(ctx->cbuf, data, length);
517 left_bytes -= length;
518 mybox.x += length;
519 data += length;
520 }
521 return 0;
522 }
523
524 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
525 struct virgl_resource *res)
526 {
527 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
528 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
529 return 0;
530 }
531
532 int virgl_encode_sampler_state(struct virgl_context *ctx,
533 uint32_t handle,
534 const struct pipe_sampler_state *state)
535 {
536 uint32_t tmp;
537 int i;
538 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
539 virgl_encoder_write_dword(ctx->cbuf, handle);
540
541 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
542 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
543 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
544 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
545 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
546 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
547 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
548 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func);
549
550 virgl_encoder_write_dword(ctx->cbuf, tmp);
551 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
552 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
553 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
554 for (i = 0; i < 4; i++)
555 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
556 return 0;
557 }
558
559
560 int virgl_encode_sampler_view(struct virgl_context *ctx,
561 uint32_t handle,
562 struct virgl_resource *res,
563 const struct pipe_sampler_view *state)
564 {
565 uint32_t tmp;
566 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
567 virgl_encoder_write_dword(ctx->cbuf, handle);
568 virgl_encoder_write_res(ctx, res);
569 virgl_encoder_write_dword(ctx->cbuf, state->format);
570 if (res->u.b.target == PIPE_BUFFER) {
571 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.first_element);
572 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.last_element);
573 } else {
574 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
575 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
576 }
577 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
578 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
579 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
580 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
581 virgl_encoder_write_dword(ctx->cbuf, tmp);
582 return 0;
583 }
584
585 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
586 uint32_t shader_type,
587 uint32_t start_slot,
588 uint32_t num_views,
589 struct virgl_sampler_view **views)
590 {
591 int i;
592 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
593 virgl_encoder_write_dword(ctx->cbuf, shader_type);
594 virgl_encoder_write_dword(ctx->cbuf, start_slot);
595 for (i = 0; i < num_views; i++) {
596 uint32_t handle = views[i] ? views[i]->handle : 0;
597 virgl_encoder_write_dword(ctx->cbuf, handle);
598 }
599 return 0;
600 }
601
602 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
603 uint32_t shader_type,
604 uint32_t start_slot,
605 uint32_t num_handles,
606 uint32_t *handles)
607 {
608 int i;
609 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
610 virgl_encoder_write_dword(ctx->cbuf, shader_type);
611 virgl_encoder_write_dword(ctx->cbuf, start_slot);
612 for (i = 0; i < num_handles; i++)
613 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
614 return 0;
615 }
616
617 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
618 uint32_t shader,
619 uint32_t index,
620 uint32_t size,
621 const void *data)
622 {
623 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
624 virgl_encoder_write_dword(ctx->cbuf, shader);
625 virgl_encoder_write_dword(ctx->cbuf, index);
626 if (data)
627 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
628 return 0;
629 }
630
631 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
632 uint32_t shader,
633 uint32_t index,
634 uint32_t offset,
635 uint32_t length,
636 struct virgl_resource *res)
637 {
638 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
639 virgl_encoder_write_dword(ctx->cbuf, shader);
640 virgl_encoder_write_dword(ctx->cbuf, index);
641 virgl_encoder_write_dword(ctx->cbuf, offset);
642 virgl_encoder_write_dword(ctx->cbuf, length);
643 virgl_encoder_write_res(ctx, res);
644 return 0;
645 }
646
647
648 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
649 const struct pipe_stencil_ref *ref)
650 {
651 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
652 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
653 return 0;
654 }
655
656 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
657 const struct pipe_blend_color *color)
658 {
659 int i;
660 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
661 for (i = 0; i < 4; i++)
662 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
663 return 0;
664 }
665
666 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
667 unsigned start_slot,
668 int num_scissors,
669 const struct pipe_scissor_state *ss)
670 {
671 int i;
672 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
673 virgl_encoder_write_dword(ctx->cbuf, start_slot);
674 for (i = 0; i < num_scissors; i++) {
675 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
676 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
677 }
678 return 0;
679 }
680
681 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
682 const struct pipe_poly_stipple *ps)
683 {
684 int i;
685 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
686 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
687 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
688 }
689 }
690
691 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
692 unsigned sample_mask)
693 {
694 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
695 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
696 }
697
698 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
699 const struct pipe_clip_state *clip)
700 {
701 int i, j;
702 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
703 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
704 for (j = 0; j < 4; j++) {
705 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
706 }
707 }
708 }
709
710 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
711 struct virgl_resource *dst_res,
712 unsigned dst_level,
713 unsigned dstx, unsigned dsty, unsigned dstz,
714 struct virgl_resource *src_res,
715 unsigned src_level,
716 const struct pipe_box *src_box)
717 {
718 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
719 virgl_encoder_write_res(ctx, dst_res);
720 virgl_encoder_write_dword(ctx->cbuf, dst_level);
721 virgl_encoder_write_dword(ctx->cbuf, dstx);
722 virgl_encoder_write_dword(ctx->cbuf, dsty);
723 virgl_encoder_write_dword(ctx->cbuf, dstz);
724 virgl_encoder_write_res(ctx, src_res);
725 virgl_encoder_write_dword(ctx->cbuf, src_level);
726 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
727 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
728 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
729 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
730 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
731 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
732 return 0;
733 }
734
735 int virgl_encode_blit(struct virgl_context *ctx,
736 struct virgl_resource *dst_res,
737 struct virgl_resource *src_res,
738 const struct pipe_blit_info *blit)
739 {
740 uint32_t tmp;
741 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
742 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
743 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
744 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable);
745 virgl_encoder_write_dword(ctx->cbuf, tmp);
746 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
747 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
748
749 virgl_encoder_write_res(ctx, dst_res);
750 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
751 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
752 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
753 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
754 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
755 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
756 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
757 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
758
759 virgl_encoder_write_res(ctx, src_res);
760 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
761 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
762 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
763 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
764 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
765 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
766 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
767 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
768 return 0;
769 }
770
771 int virgl_encoder_create_query(struct virgl_context *ctx,
772 uint32_t handle,
773 uint query_type,
774 uint query_index,
775 struct virgl_resource *res,
776 uint32_t offset)
777 {
778 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
779 virgl_encoder_write_dword(ctx->cbuf, handle);
780 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
781 virgl_encoder_write_dword(ctx->cbuf, offset);
782 virgl_encoder_write_res(ctx, res);
783 return 0;
784 }
785
786 int virgl_encoder_begin_query(struct virgl_context *ctx,
787 uint32_t handle)
788 {
789 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
790 virgl_encoder_write_dword(ctx->cbuf, handle);
791 return 0;
792 }
793
794 int virgl_encoder_end_query(struct virgl_context *ctx,
795 uint32_t handle)
796 {
797 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
798 virgl_encoder_write_dword(ctx->cbuf, handle);
799 return 0;
800 }
801
802 int virgl_encoder_get_query_result(struct virgl_context *ctx,
803 uint32_t handle, boolean wait)
804 {
805 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
806 virgl_encoder_write_dword(ctx->cbuf, handle);
807 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
808 return 0;
809 }
810
811 int virgl_encoder_render_condition(struct virgl_context *ctx,
812 uint32_t handle, boolean condition,
813 uint mode)
814 {
815 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
816 virgl_encoder_write_dword(ctx->cbuf, handle);
817 virgl_encoder_write_dword(ctx->cbuf, condition);
818 virgl_encoder_write_dword(ctx->cbuf, mode);
819 return 0;
820 }
821
822 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
823 unsigned num_targets,
824 struct pipe_stream_output_target **targets,
825 unsigned append_bitmask)
826 {
827 int i;
828
829 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
830 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
831 for (i = 0; i < num_targets; i++) {
832 struct virgl_so_target *tg = virgl_so_target(targets[i]);
833 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
834 }
835 return 0;
836 }
837
838
839 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
840 {
841 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
842 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
843 return 0;
844 }
845
846 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
847 {
848 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
849 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
850 return 0;
851 }
852
853 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
854 {
855 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
856 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
857 return 0;
858 }
859
860 int virgl_encode_bind_shader(struct virgl_context *ctx,
861 uint32_t handle, uint32_t type)
862 {
863 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
864 virgl_encoder_write_dword(ctx->cbuf, handle);
865 virgl_encoder_write_dword(ctx->cbuf, type);
866 return 0;
867 }