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4493c3f8ad2f75544803af4e57640b5717755285
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24
25 #include "util/u_memory.h"
26 #include "util/u_math.h"
27 #include "pipe/p_state.h"
28 #include "virgl_encode.h"
29 #include "virgl_resource.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "tgsi/tgsi_parse.h"
32
33 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
34 uint32_t dword)
35 {
36 int len = (dword >> 16);
37
38 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
39 ctx->base.flush(&ctx->base, NULL, 0);
40
41 virgl_encoder_write_dword(ctx->cbuf, dword);
42 return 0;
43 }
44
45 static void virgl_encoder_write_res(struct virgl_context *ctx,
46 struct virgl_resource *res)
47 {
48 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
49
50 if (res && res->hw_res)
51 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
52 else {
53 virgl_encoder_write_dword(ctx->cbuf, 0);
54 }
55 }
56
57 int virgl_encode_bind_object(struct virgl_context *ctx,
58 uint32_t handle, uint32_t object)
59 {
60 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
61 virgl_encoder_write_dword(ctx->cbuf, handle);
62 return 0;
63 }
64
65 int virgl_encode_delete_object(struct virgl_context *ctx,
66 uint32_t handle, uint32_t object)
67 {
68 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
69 virgl_encoder_write_dword(ctx->cbuf, handle);
70 return 0;
71 }
72
73 int virgl_encode_blend_state(struct virgl_context *ctx,
74 uint32_t handle,
75 const struct pipe_blend_state *blend_state)
76 {
77 uint32_t tmp;
78 int i;
79
80 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
81 virgl_encoder_write_dword(ctx->cbuf, handle);
82
83 tmp =
84 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
85 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
86 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
87 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
88 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
89
90 virgl_encoder_write_dword(ctx->cbuf, tmp);
91
92 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
93 virgl_encoder_write_dword(ctx->cbuf, tmp);
94
95 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
96 tmp =
97 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
98 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
99 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
100 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
101 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
102 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
103 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
104 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
105 virgl_encoder_write_dword(ctx->cbuf, tmp);
106 }
107 return 0;
108 }
109
110 int virgl_encode_dsa_state(struct virgl_context *ctx,
111 uint32_t handle,
112 const struct pipe_depth_stencil_alpha_state *dsa_state)
113 {
114 uint32_t tmp;
115 int i;
116 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
117 virgl_encoder_write_dword(ctx->cbuf, handle);
118
119 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
120 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
121 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
122 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
123 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
124 virgl_encoder_write_dword(ctx->cbuf, tmp);
125
126 for (i = 0; i < 2; i++) {
127 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
128 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
129 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
130 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
131 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
132 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
133 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
134 virgl_encoder_write_dword(ctx->cbuf, tmp);
135 }
136
137 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
138 return 0;
139 }
140 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
141 uint32_t handle,
142 const struct pipe_rasterizer_state *state)
143 {
144 uint32_t tmp;
145
146 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
147 virgl_encoder_write_dword(ctx->cbuf, handle);
148
149 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
150 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
151 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
152 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
153 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
154 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
155 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
156 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
157 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
158 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
159 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
160 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
161 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
162 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
163 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
164 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
165 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
166 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
167 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
168 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
169 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
170 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
171 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
172 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
173 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
174 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
175 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
176 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule);
177
178 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
179 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
180 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
181 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
182 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
183 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
184 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
185 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
186 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
187 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
188 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
189 return 0;
190 }
191
192 static void virgl_emit_shader_header(struct virgl_context *ctx,
193 uint32_t handle, uint32_t len,
194 uint32_t type, uint32_t offlen,
195 uint32_t num_tokens)
196 {
197 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
198 virgl_encoder_write_dword(ctx->cbuf, handle);
199 virgl_encoder_write_dword(ctx->cbuf, type);
200 virgl_encoder_write_dword(ctx->cbuf, offlen);
201 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
202 }
203
204 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
205 const struct pipe_stream_output_info *so_info)
206 {
207 int num_outputs = 0;
208 int i;
209 uint32_t tmp;
210
211 if (so_info)
212 num_outputs = so_info->num_outputs;
213
214 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
215 if (num_outputs) {
216 for (i = 0; i < 4; i++)
217 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
218
219 for (i = 0; i < so_info->num_outputs; i++) {
220 tmp =
221 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
222 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
223 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
224 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
225 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
226 virgl_encoder_write_dword(ctx->cbuf, tmp);
227 virgl_encoder_write_dword(ctx->cbuf, 0);
228 }
229 }
230 }
231
232 int virgl_encode_shader_state(struct virgl_context *ctx,
233 uint32_t handle,
234 uint32_t type,
235 const struct pipe_stream_output_info *so_info,
236 const struct tgsi_token *tokens)
237 {
238 char *str, *sptr;
239 uint32_t shader_len, len;
240 bool bret;
241 int num_tokens = tgsi_num_tokens(tokens);
242 int str_total_size = 65536;
243 int retry_size = 1;
244 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
245 bool first_pass;
246 str = CALLOC(1, str_total_size);
247 if (!str)
248 return -1;
249
250 do {
251 int old_size;
252
253 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
254 if (bret == false) {
255 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
256 old_size = str_total_size;
257 str_total_size = 65536 * ++retry_size;
258 str = REALLOC(str, old_size, str_total_size);
259 if (!str)
260 return -1;
261 }
262 } while (bret == false && retry_size < 10);
263
264 if (bret == false)
265 return -1;
266
267 shader_len = strlen(str) + 1;
268
269 left_bytes = shader_len;
270
271 base_hdr_size = 5;
272 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
273 first_pass = true;
274 sptr = str;
275 while (left_bytes) {
276 uint32_t length, offlen;
277 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
278 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
279 ctx->base.flush(&ctx->base, NULL, 0);
280
281 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
282
283 length = MIN2(thispass, left_bytes);
284 len = ((length + 3) / 4) + hdr_len;
285
286 if (first_pass)
287 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
288 else
289 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
290
291 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
292
293 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
294
295 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
296
297 sptr += length;
298 first_pass = false;
299 left_bytes -= length;
300 }
301
302 FREE(str);
303 return 0;
304 }
305
306
307 int virgl_encode_clear(struct virgl_context *ctx,
308 unsigned buffers,
309 const union pipe_color_union *color,
310 double depth, unsigned stencil)
311 {
312 int i;
313
314 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
315 virgl_encoder_write_dword(ctx->cbuf, buffers);
316 for (i = 0; i < 4; i++)
317 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
318 virgl_encoder_write_qword(ctx->cbuf, *(uint64_t *)&depth);
319 virgl_encoder_write_dword(ctx->cbuf, stencil);
320 return 0;
321 }
322
323 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
324 const struct pipe_framebuffer_state *state)
325 {
326 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
327 int i;
328
329 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
330 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
331 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
332 for (i = 0; i < state->nr_cbufs; i++) {
333 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
334 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
335 }
336
337 return 0;
338 }
339
340 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
341 int start_slot,
342 int num_viewports,
343 const struct pipe_viewport_state *states)
344 {
345 int i,v;
346 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
347 virgl_encoder_write_dword(ctx->cbuf, start_slot);
348 for (v = 0; v < num_viewports; v++) {
349 for (i = 0; i < 3; i++)
350 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
351 for (i = 0; i < 3; i++)
352 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
353 }
354 return 0;
355 }
356
357 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
358 uint32_t handle,
359 unsigned num_elements,
360 const struct pipe_vertex_element *element)
361 {
362 int i;
363 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
364 virgl_encoder_write_dword(ctx->cbuf, handle);
365 for (i = 0; i < num_elements; i++) {
366 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
367 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
368 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
369 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
370 }
371 return 0;
372 }
373
374 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
375 unsigned num_buffers,
376 const struct pipe_vertex_buffer *buffers)
377 {
378 int i;
379 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
380 for (i = 0; i < num_buffers; i++) {
381 struct virgl_resource *res = virgl_resource(buffers[i].buffer);
382 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
383 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
384 virgl_encoder_write_res(ctx, res);
385 }
386 return 0;
387 }
388
389 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
390 const struct pipe_index_buffer *ib)
391 {
392 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
393 struct virgl_resource *res = NULL;
394 if (ib)
395 res = virgl_resource(ib->buffer);
396
397 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
398 virgl_encoder_write_res(ctx, res);
399 if (ib) {
400 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
401 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
402 }
403 return 0;
404 }
405
406 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
407 const struct pipe_draw_info *info)
408 {
409 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, VIRGL_DRAW_VBO_SIZE));
410 virgl_encoder_write_dword(ctx->cbuf, info->start);
411 virgl_encoder_write_dword(ctx->cbuf, info->count);
412 virgl_encoder_write_dword(ctx->cbuf, info->mode);
413 virgl_encoder_write_dword(ctx->cbuf, info->indexed);
414 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
415 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
416 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
417 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
418 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
419 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
420 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
421 if (info->count_from_stream_output)
422 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
423 else
424 virgl_encoder_write_dword(ctx->cbuf, 0);
425 return 0;
426 }
427
428 int virgl_encoder_create_surface(struct virgl_context *ctx,
429 uint32_t handle,
430 struct virgl_resource *res,
431 const struct pipe_surface *templat)
432 {
433 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
434 virgl_encoder_write_dword(ctx->cbuf, handle);
435 virgl_encoder_write_res(ctx, res);
436 virgl_encoder_write_dword(ctx->cbuf, templat->format);
437 if (templat->texture->target == PIPE_BUFFER) {
438 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
439 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
440
441 } else {
442 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
443 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
444 }
445 return 0;
446 }
447
448 int virgl_encoder_create_so_target(struct virgl_context *ctx,
449 uint32_t handle,
450 struct virgl_resource *res,
451 unsigned buffer_offset,
452 unsigned buffer_size)
453 {
454 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
455 virgl_encoder_write_dword(ctx->cbuf, handle);
456 virgl_encoder_write_res(ctx, res);
457 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
458 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
459 return 0;
460 }
461
462 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
463 struct virgl_resource *res,
464 unsigned level, unsigned usage,
465 const struct pipe_box *box,
466 unsigned stride, unsigned layer_stride)
467 {
468 virgl_encoder_write_res(ctx, res);
469 virgl_encoder_write_dword(ctx->cbuf, level);
470 virgl_encoder_write_dword(ctx->cbuf, usage);
471 virgl_encoder_write_dword(ctx->cbuf, stride);
472 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
473 virgl_encoder_write_dword(ctx->cbuf, box->x);
474 virgl_encoder_write_dword(ctx->cbuf, box->y);
475 virgl_encoder_write_dword(ctx->cbuf, box->z);
476 virgl_encoder_write_dword(ctx->cbuf, box->width);
477 virgl_encoder_write_dword(ctx->cbuf, box->height);
478 virgl_encoder_write_dword(ctx->cbuf, box->depth);
479 }
480
481 int virgl_encoder_inline_write(struct virgl_context *ctx,
482 struct virgl_resource *res,
483 unsigned level, unsigned usage,
484 const struct pipe_box *box,
485 const void *data, unsigned stride,
486 unsigned layer_stride)
487 {
488 uint32_t size = (stride ? stride : box->width) * box->height;
489 uint32_t length, thispass, left_bytes;
490 struct pipe_box mybox = *box;
491
492 length = 11 + (size + 3) / 4;
493 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
494 if (box->height > 1 || box->depth > 1) {
495 debug_printf("inline transfer failed due to multi dimensions and too large\n");
496 assert(0);
497 }
498 }
499
500 left_bytes = size;
501 while (left_bytes) {
502 if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
503 ctx->base.flush(&ctx->base, NULL, 0);
504
505 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
506
507 length = MIN2(thispass, left_bytes);
508
509 mybox.width = length;
510 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
511 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
512 virgl_encoder_write_block(ctx->cbuf, data, length);
513 left_bytes -= length;
514 mybox.x += length;
515 data += length;
516 }
517 return 0;
518 }
519
520 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
521 struct virgl_resource *res)
522 {
523 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
524 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
525 return 0;
526 }
527
528 int virgl_encode_sampler_state(struct virgl_context *ctx,
529 uint32_t handle,
530 const struct pipe_sampler_state *state)
531 {
532 uint32_t tmp;
533 int i;
534 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
535 virgl_encoder_write_dword(ctx->cbuf, handle);
536
537 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
538 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
539 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
540 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
541 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
542 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
543 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
544 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func);
545
546 virgl_encoder_write_dword(ctx->cbuf, tmp);
547 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
548 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
549 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
550 for (i = 0; i < 4; i++)
551 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
552 return 0;
553 }
554
555
556 int virgl_encode_sampler_view(struct virgl_context *ctx,
557 uint32_t handle,
558 struct virgl_resource *res,
559 const struct pipe_sampler_view *state)
560 {
561 uint32_t tmp;
562 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
563 virgl_encoder_write_dword(ctx->cbuf, handle);
564 virgl_encoder_write_res(ctx, res);
565 virgl_encoder_write_dword(ctx->cbuf, state->format);
566 if (res->u.b.target == PIPE_BUFFER) {
567 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.first_element);
568 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.last_element);
569 } else {
570 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
571 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
572 }
573 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
574 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
575 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
576 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
577 virgl_encoder_write_dword(ctx->cbuf, tmp);
578 return 0;
579 }
580
581 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
582 uint32_t shader_type,
583 uint32_t start_slot,
584 uint32_t num_views,
585 struct virgl_sampler_view **views)
586 {
587 int i;
588 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
589 virgl_encoder_write_dword(ctx->cbuf, shader_type);
590 virgl_encoder_write_dword(ctx->cbuf, start_slot);
591 for (i = 0; i < num_views; i++) {
592 uint32_t handle = views[i] ? views[i]->handle : 0;
593 virgl_encoder_write_dword(ctx->cbuf, handle);
594 }
595 return 0;
596 }
597
598 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
599 uint32_t shader_type,
600 uint32_t start_slot,
601 uint32_t num_handles,
602 uint32_t *handles)
603 {
604 int i;
605 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
606 virgl_encoder_write_dword(ctx->cbuf, shader_type);
607 virgl_encoder_write_dword(ctx->cbuf, start_slot);
608 for (i = 0; i < num_handles; i++)
609 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
610 return 0;
611 }
612
613 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
614 uint32_t shader,
615 uint32_t index,
616 uint32_t size,
617 const void *data)
618 {
619 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
620 virgl_encoder_write_dword(ctx->cbuf, shader);
621 virgl_encoder_write_dword(ctx->cbuf, index);
622 if (data)
623 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
624 return 0;
625 }
626
627 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
628 uint32_t shader,
629 uint32_t index,
630 uint32_t offset,
631 uint32_t length,
632 struct virgl_resource *res)
633 {
634 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
635 virgl_encoder_write_dword(ctx->cbuf, shader);
636 virgl_encoder_write_dword(ctx->cbuf, index);
637 virgl_encoder_write_dword(ctx->cbuf, offset);
638 virgl_encoder_write_dword(ctx->cbuf, length);
639 virgl_encoder_write_res(ctx, res);
640 return 0;
641 }
642
643
644 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
645 const struct pipe_stencil_ref *ref)
646 {
647 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
648 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
649 return 0;
650 }
651
652 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
653 const struct pipe_blend_color *color)
654 {
655 int i;
656 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
657 for (i = 0; i < 4; i++)
658 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
659 return 0;
660 }
661
662 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
663 unsigned start_slot,
664 int num_scissors,
665 const struct pipe_scissor_state *ss)
666 {
667 int i;
668 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
669 virgl_encoder_write_dword(ctx->cbuf, start_slot);
670 for (i = 0; i < num_scissors; i++) {
671 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
672 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
673 }
674 return 0;
675 }
676
677 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
678 const struct pipe_poly_stipple *ps)
679 {
680 int i;
681 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
682 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
683 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
684 }
685 }
686
687 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
688 unsigned sample_mask)
689 {
690 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
691 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
692 }
693
694 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
695 const struct pipe_clip_state *clip)
696 {
697 int i, j;
698 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
699 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
700 for (j = 0; j < 4; j++) {
701 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
702 }
703 }
704 }
705
706 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
707 struct virgl_resource *dst_res,
708 unsigned dst_level,
709 unsigned dstx, unsigned dsty, unsigned dstz,
710 struct virgl_resource *src_res,
711 unsigned src_level,
712 const struct pipe_box *src_box)
713 {
714 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
715 virgl_encoder_write_res(ctx, dst_res);
716 virgl_encoder_write_dword(ctx->cbuf, dst_level);
717 virgl_encoder_write_dword(ctx->cbuf, dstx);
718 virgl_encoder_write_dword(ctx->cbuf, dsty);
719 virgl_encoder_write_dword(ctx->cbuf, dstz);
720 virgl_encoder_write_res(ctx, src_res);
721 virgl_encoder_write_dword(ctx->cbuf, src_level);
722 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
723 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
724 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
725 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
726 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
727 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
728 return 0;
729 }
730
731 int virgl_encode_blit(struct virgl_context *ctx,
732 struct virgl_resource *dst_res,
733 struct virgl_resource *src_res,
734 const struct pipe_blit_info *blit)
735 {
736 uint32_t tmp;
737 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
738 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
739 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
740 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable);
741 virgl_encoder_write_dword(ctx->cbuf, tmp);
742 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
743 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
744
745 virgl_encoder_write_res(ctx, dst_res);
746 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
747 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
748 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
749 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
750 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
751 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
752 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
753 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
754
755 virgl_encoder_write_res(ctx, src_res);
756 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
757 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
758 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
759 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
760 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
761 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
762 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
763 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
764 return 0;
765 }
766
767 int virgl_encoder_create_query(struct virgl_context *ctx,
768 uint32_t handle,
769 uint query_type,
770 uint query_index,
771 struct virgl_resource *res,
772 uint32_t offset)
773 {
774 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
775 virgl_encoder_write_dword(ctx->cbuf, handle);
776 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
777 virgl_encoder_write_dword(ctx->cbuf, offset);
778 virgl_encoder_write_res(ctx, res);
779 return 0;
780 }
781
782 int virgl_encoder_begin_query(struct virgl_context *ctx,
783 uint32_t handle)
784 {
785 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
786 virgl_encoder_write_dword(ctx->cbuf, handle);
787 return 0;
788 }
789
790 int virgl_encoder_end_query(struct virgl_context *ctx,
791 uint32_t handle)
792 {
793 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
794 virgl_encoder_write_dword(ctx->cbuf, handle);
795 return 0;
796 }
797
798 int virgl_encoder_get_query_result(struct virgl_context *ctx,
799 uint32_t handle, boolean wait)
800 {
801 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
802 virgl_encoder_write_dword(ctx->cbuf, handle);
803 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
804 return 0;
805 }
806
807 int virgl_encoder_render_condition(struct virgl_context *ctx,
808 uint32_t handle, boolean condition,
809 uint mode)
810 {
811 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
812 virgl_encoder_write_dword(ctx->cbuf, handle);
813 virgl_encoder_write_dword(ctx->cbuf, condition);
814 virgl_encoder_write_dword(ctx->cbuf, mode);
815 return 0;
816 }
817
818 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
819 unsigned num_targets,
820 struct pipe_stream_output_target **targets,
821 unsigned append_bitmask)
822 {
823 int i;
824
825 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
826 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
827 for (i = 0; i < num_targets; i++) {
828 struct virgl_so_target *tg = virgl_so_target(targets[i]);
829 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
830 }
831 return 0;
832 }
833
834
835 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
836 {
837 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
838 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
839 return 0;
840 }
841
842 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
843 {
844 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
845 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
846 return 0;
847 }
848
849 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
850 {
851 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
852 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
853 return 0;
854 }
855
856 int virgl_encode_bind_shader(struct virgl_context *ctx,
857 uint32_t handle, uint32_t type)
858 {
859 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
860 virgl_encoder_write_dword(ctx->cbuf, handle);
861 virgl_encoder_write_dword(ctx->cbuf, type);
862 return 0;
863 }