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virgl: Support ARB_framebuffer_no_attachments
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24 #include <assert.h>
25 #include <string.h>
26
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_math.h"
30 #include "pipe/p_state.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_parse.h"
33
34 #include "virgl_context.h"
35 #include "virgl_encode.h"
36 #include "virgl_protocol.h"
37 #include "virgl_resource.h"
38 #include "virgl_screen.h"
39
40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
41 uint32_t dword)
42 {
43 int len = (dword >> 16);
44
45 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
46 ctx->base.flush(&ctx->base, NULL, 0);
47
48 virgl_encoder_write_dword(ctx->cbuf, dword);
49 return 0;
50 }
51
52 static void virgl_encoder_write_res(struct virgl_context *ctx,
53 struct virgl_resource *res)
54 {
55 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
56
57 if (res && res->hw_res)
58 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
59 else {
60 virgl_encoder_write_dword(ctx->cbuf, 0);
61 }
62 }
63
64 int virgl_encode_bind_object(struct virgl_context *ctx,
65 uint32_t handle, uint32_t object)
66 {
67 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
68 virgl_encoder_write_dword(ctx->cbuf, handle);
69 return 0;
70 }
71
72 int virgl_encode_delete_object(struct virgl_context *ctx,
73 uint32_t handle, uint32_t object)
74 {
75 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
76 virgl_encoder_write_dword(ctx->cbuf, handle);
77 return 0;
78 }
79
80 int virgl_encode_blend_state(struct virgl_context *ctx,
81 uint32_t handle,
82 const struct pipe_blend_state *blend_state)
83 {
84 uint32_t tmp;
85 int i;
86
87 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
88 virgl_encoder_write_dword(ctx->cbuf, handle);
89
90 tmp =
91 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
92 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
93 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
94 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
95 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
96
97 virgl_encoder_write_dword(ctx->cbuf, tmp);
98
99 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
100 virgl_encoder_write_dword(ctx->cbuf, tmp);
101
102 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
103 tmp =
104 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
105 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
106 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
107 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
108 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
109 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
110 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
111 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
112 virgl_encoder_write_dword(ctx->cbuf, tmp);
113 }
114 return 0;
115 }
116
117 int virgl_encode_dsa_state(struct virgl_context *ctx,
118 uint32_t handle,
119 const struct pipe_depth_stencil_alpha_state *dsa_state)
120 {
121 uint32_t tmp;
122 int i;
123 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
124 virgl_encoder_write_dword(ctx->cbuf, handle);
125
126 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
128 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
129 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
130 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
131 virgl_encoder_write_dword(ctx->cbuf, tmp);
132
133 for (i = 0; i < 2; i++) {
134 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
135 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
136 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
137 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
138 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
139 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
141 virgl_encoder_write_dword(ctx->cbuf, tmp);
142 }
143
144 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
145 return 0;
146 }
147 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
148 uint32_t handle,
149 const struct pipe_rasterizer_state *state)
150 {
151 uint32_t tmp;
152
153 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
154 virgl_encoder_write_dword(ctx->cbuf, handle);
155
156 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
157 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
158 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
159 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
160 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
161 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
162 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
163 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
164 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
165 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
166 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
167 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
168 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
169 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
170 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
171 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
172 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
173 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
174 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
175 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
176 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
177 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
178 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
179 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
180 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
181 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
182 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
183 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
184 VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
185
186 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
187 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
188 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
189 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
190 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
191 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
192 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
193 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
194 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
195 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
196 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
197 return 0;
198 }
199
200 static void virgl_emit_shader_header(struct virgl_context *ctx,
201 uint32_t handle, uint32_t len,
202 uint32_t type, uint32_t offlen,
203 uint32_t num_tokens)
204 {
205 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
206 virgl_encoder_write_dword(ctx->cbuf, handle);
207 virgl_encoder_write_dword(ctx->cbuf, type);
208 virgl_encoder_write_dword(ctx->cbuf, offlen);
209 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
210 }
211
212 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
213 const struct pipe_stream_output_info *so_info)
214 {
215 int num_outputs = 0;
216 int i;
217 uint32_t tmp;
218
219 if (so_info)
220 num_outputs = so_info->num_outputs;
221
222 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
223 if (num_outputs) {
224 for (i = 0; i < 4; i++)
225 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
226
227 for (i = 0; i < so_info->num_outputs; i++) {
228 tmp =
229 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
230 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
231 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
232 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
233 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
234 virgl_encoder_write_dword(ctx->cbuf, tmp);
235 virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream);
236 }
237 }
238 }
239
240 int virgl_encode_shader_state(struct virgl_context *ctx,
241 uint32_t handle,
242 uint32_t type,
243 const struct pipe_stream_output_info *so_info,
244 uint32_t cs_req_local_mem,
245 const struct tgsi_token *tokens)
246 {
247 char *str, *sptr;
248 uint32_t shader_len, len;
249 bool bret;
250 int num_tokens = tgsi_num_tokens(tokens);
251 int str_total_size = 65536;
252 int retry_size = 1;
253 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
254 bool first_pass;
255 str = CALLOC(1, str_total_size);
256 if (!str)
257 return -1;
258
259 do {
260 int old_size;
261
262 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
263 if (bret == false) {
264 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
265 old_size = str_total_size;
266 str_total_size = 65536 * ++retry_size;
267 str = REALLOC(str, old_size, str_total_size);
268 if (!str)
269 return -1;
270 }
271 } while (bret == false && retry_size < 10);
272
273 if (bret == false)
274 return -1;
275
276 shader_len = strlen(str) + 1;
277
278 left_bytes = shader_len;
279
280 base_hdr_size = 5;
281 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
282 first_pass = true;
283 sptr = str;
284 while (left_bytes) {
285 uint32_t length, offlen;
286 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
287 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
288 ctx->base.flush(&ctx->base, NULL, 0);
289
290 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
291
292 length = MIN2(thispass, left_bytes);
293 len = ((length + 3) / 4) + hdr_len;
294
295 if (first_pass)
296 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
297 else
298 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
299
300 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
301
302 if (type == PIPE_SHADER_COMPUTE)
303 virgl_encoder_write_dword(ctx->cbuf, cs_req_local_mem);
304 else
305 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
306
307 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
308
309 sptr += length;
310 first_pass = false;
311 left_bytes -= length;
312 }
313
314 FREE(str);
315 return 0;
316 }
317
318
319 int virgl_encode_clear(struct virgl_context *ctx,
320 unsigned buffers,
321 const union pipe_color_union *color,
322 double depth, unsigned stencil)
323 {
324 int i;
325 uint64_t qword;
326
327 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
328 memcpy(&qword, &depth, sizeof(qword));
329
330 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
331 virgl_encoder_write_dword(ctx->cbuf, buffers);
332 for (i = 0; i < 4; i++)
333 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
334 virgl_encoder_write_qword(ctx->cbuf, qword);
335 virgl_encoder_write_dword(ctx->cbuf, stencil);
336 return 0;
337 }
338
339 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
340 const struct pipe_framebuffer_state *state)
341 {
342 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
343 int i;
344
345 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
346 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
347 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
348 for (i = 0; i < state->nr_cbufs; i++) {
349 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
350 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
351 }
352
353 struct virgl_screen *rs = virgl_screen(ctx->base.screen);
354 if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH) {
355 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACH, 0, VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE));
356 virgl_encoder_write_dword(ctx->cbuf, state->width | (state->height << 16));
357 virgl_encoder_write_dword(ctx->cbuf, state->layers | (state->samples << 16));
358 }
359 return 0;
360 }
361
362 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
363 int start_slot,
364 int num_viewports,
365 const struct pipe_viewport_state *states)
366 {
367 int i,v;
368 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
369 virgl_encoder_write_dword(ctx->cbuf, start_slot);
370 for (v = 0; v < num_viewports; v++) {
371 for (i = 0; i < 3; i++)
372 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
373 for (i = 0; i < 3; i++)
374 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
375 }
376 return 0;
377 }
378
379 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
380 uint32_t handle,
381 unsigned num_elements,
382 const struct pipe_vertex_element *element)
383 {
384 int i;
385 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
386 virgl_encoder_write_dword(ctx->cbuf, handle);
387 for (i = 0; i < num_elements; i++) {
388 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
389 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
390 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
391 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
392 }
393 return 0;
394 }
395
396 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
397 unsigned num_buffers,
398 const struct pipe_vertex_buffer *buffers)
399 {
400 int i;
401 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
402 for (i = 0; i < num_buffers; i++) {
403 struct virgl_resource *res = virgl_resource(buffers[i].buffer.resource);
404 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
405 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
406 virgl_encoder_write_res(ctx, res);
407 }
408 return 0;
409 }
410
411 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
412 const struct virgl_indexbuf *ib)
413 {
414 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
415 struct virgl_resource *res = NULL;
416 if (ib)
417 res = virgl_resource(ib->buffer);
418
419 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
420 virgl_encoder_write_res(ctx, res);
421 if (ib) {
422 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
423 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
424 }
425 return 0;
426 }
427
428 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
429 const struct pipe_draw_info *info)
430 {
431 uint32_t length = VIRGL_DRAW_VBO_SIZE;
432 if (info->mode == PIPE_PRIM_PATCHES)
433 length = VIRGL_DRAW_VBO_SIZE_TESS;
434 if (info->indirect)
435 length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
436 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, length));
437 virgl_encoder_write_dword(ctx->cbuf, info->start);
438 virgl_encoder_write_dword(ctx->cbuf, info->count);
439 virgl_encoder_write_dword(ctx->cbuf, info->mode);
440 virgl_encoder_write_dword(ctx->cbuf, !!info->index_size);
441 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
442 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
443 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
444 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
445 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
446 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
447 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
448 if (info->count_from_stream_output)
449 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
450 else
451 virgl_encoder_write_dword(ctx->cbuf, 0);
452 if (length >= VIRGL_DRAW_VBO_SIZE_TESS) {
453 virgl_encoder_write_dword(ctx->cbuf, info->vertices_per_patch); /* vertices per patch */
454 virgl_encoder_write_dword(ctx->cbuf, info->drawid); /* drawid */
455 }
456 if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
457 virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
458 virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
459 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
460 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
461 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
462 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
463 }
464 return 0;
465 }
466
467 int virgl_encoder_create_surface(struct virgl_context *ctx,
468 uint32_t handle,
469 struct virgl_resource *res,
470 const struct pipe_surface *templat)
471 {
472 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
473 virgl_encoder_write_dword(ctx->cbuf, handle);
474 virgl_encoder_write_res(ctx, res);
475 virgl_encoder_write_dword(ctx->cbuf, templat->format);
476 if (templat->texture->target == PIPE_BUFFER) {
477 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
478 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
479
480 } else {
481 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
482 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
483 }
484 return 0;
485 }
486
487 int virgl_encoder_create_so_target(struct virgl_context *ctx,
488 uint32_t handle,
489 struct virgl_resource *res,
490 unsigned buffer_offset,
491 unsigned buffer_size)
492 {
493 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
494 virgl_encoder_write_dword(ctx->cbuf, handle);
495 virgl_encoder_write_res(ctx, res);
496 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
497 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
498 return 0;
499 }
500
501 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
502 struct virgl_resource *res,
503 unsigned level, unsigned usage,
504 const struct pipe_box *box,
505 unsigned stride, unsigned layer_stride)
506 {
507 virgl_encoder_write_res(ctx, res);
508 virgl_encoder_write_dword(ctx->cbuf, level);
509 virgl_encoder_write_dword(ctx->cbuf, usage);
510 virgl_encoder_write_dword(ctx->cbuf, stride);
511 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
512 virgl_encoder_write_dword(ctx->cbuf, box->x);
513 virgl_encoder_write_dword(ctx->cbuf, box->y);
514 virgl_encoder_write_dword(ctx->cbuf, box->z);
515 virgl_encoder_write_dword(ctx->cbuf, box->width);
516 virgl_encoder_write_dword(ctx->cbuf, box->height);
517 virgl_encoder_write_dword(ctx->cbuf, box->depth);
518 }
519
520 int virgl_encoder_inline_write(struct virgl_context *ctx,
521 struct virgl_resource *res,
522 unsigned level, unsigned usage,
523 const struct pipe_box *box,
524 const void *data, unsigned stride,
525 unsigned layer_stride)
526 {
527 uint32_t size = (stride ? stride : box->width) * box->height;
528 uint32_t length, thispass, left_bytes;
529 struct pipe_box mybox = *box;
530
531 length = 11 + (size + 3) / 4;
532 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
533 if (box->height > 1 || box->depth > 1) {
534 debug_printf("inline transfer failed due to multi dimensions and too large\n");
535 assert(0);
536 }
537 }
538
539 left_bytes = size;
540 while (left_bytes) {
541 if (ctx->cbuf->cdw + 12 >= VIRGL_MAX_CMDBUF_DWORDS)
542 ctx->base.flush(&ctx->base, NULL, 0);
543
544 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
545
546 length = MIN2(thispass, left_bytes);
547
548 mybox.width = length;
549 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
550 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
551 virgl_encoder_write_block(ctx->cbuf, data, length);
552 left_bytes -= length;
553 mybox.x += length;
554 data += length;
555 }
556 return 0;
557 }
558
559 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
560 struct virgl_resource *res)
561 {
562 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
563 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
564 return 0;
565 }
566
567 int virgl_encode_sampler_state(struct virgl_context *ctx,
568 uint32_t handle,
569 const struct pipe_sampler_state *state)
570 {
571 uint32_t tmp;
572 int i;
573 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
574 virgl_encoder_write_dword(ctx->cbuf, handle);
575
576 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
577 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
578 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
579 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
580 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
581 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
582 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
583 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
584 VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map);
585
586 virgl_encoder_write_dword(ctx->cbuf, tmp);
587 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
588 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
589 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
590 for (i = 0; i < 4; i++)
591 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
592 return 0;
593 }
594
595
596 int virgl_encode_sampler_view(struct virgl_context *ctx,
597 uint32_t handle,
598 struct virgl_resource *res,
599 const struct pipe_sampler_view *state)
600 {
601 unsigned elem_size = util_format_get_blocksize(state->format);
602 struct virgl_screen *rs = virgl_screen(ctx->base.screen);
603 uint32_t tmp;
604 uint32_t dword_fmt_target = state->format;
605 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
606 virgl_encoder_write_dword(ctx->cbuf, handle);
607 virgl_encoder_write_res(ctx, res);
608 if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
609 dword_fmt_target |= (state->target << 24);
610 virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
611 if (res->u.b.target == PIPE_BUFFER) {
612 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
613 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
614 } else {
615 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
616 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
617 }
618 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
619 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
620 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
621 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
622 virgl_encoder_write_dword(ctx->cbuf, tmp);
623 return 0;
624 }
625
626 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
627 uint32_t shader_type,
628 uint32_t start_slot,
629 uint32_t num_views,
630 struct virgl_sampler_view **views)
631 {
632 int i;
633 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
634 virgl_encoder_write_dword(ctx->cbuf, shader_type);
635 virgl_encoder_write_dword(ctx->cbuf, start_slot);
636 for (i = 0; i < num_views; i++) {
637 uint32_t handle = views[i] ? views[i]->handle : 0;
638 virgl_encoder_write_dword(ctx->cbuf, handle);
639 }
640 return 0;
641 }
642
643 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
644 uint32_t shader_type,
645 uint32_t start_slot,
646 uint32_t num_handles,
647 uint32_t *handles)
648 {
649 int i;
650 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
651 virgl_encoder_write_dword(ctx->cbuf, shader_type);
652 virgl_encoder_write_dword(ctx->cbuf, start_slot);
653 for (i = 0; i < num_handles; i++)
654 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
655 return 0;
656 }
657
658 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
659 uint32_t shader,
660 uint32_t index,
661 uint32_t size,
662 const void *data)
663 {
664 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
665 virgl_encoder_write_dword(ctx->cbuf, shader);
666 virgl_encoder_write_dword(ctx->cbuf, index);
667 if (data)
668 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
669 return 0;
670 }
671
672 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
673 uint32_t shader,
674 uint32_t index,
675 uint32_t offset,
676 uint32_t length,
677 struct virgl_resource *res)
678 {
679 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
680 virgl_encoder_write_dword(ctx->cbuf, shader);
681 virgl_encoder_write_dword(ctx->cbuf, index);
682 virgl_encoder_write_dword(ctx->cbuf, offset);
683 virgl_encoder_write_dword(ctx->cbuf, length);
684 virgl_encoder_write_res(ctx, res);
685 return 0;
686 }
687
688
689 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
690 const struct pipe_stencil_ref *ref)
691 {
692 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
693 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
694 return 0;
695 }
696
697 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
698 const struct pipe_blend_color *color)
699 {
700 int i;
701 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
702 for (i = 0; i < 4; i++)
703 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
704 return 0;
705 }
706
707 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
708 unsigned start_slot,
709 int num_scissors,
710 const struct pipe_scissor_state *ss)
711 {
712 int i;
713 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
714 virgl_encoder_write_dword(ctx->cbuf, start_slot);
715 for (i = 0; i < num_scissors; i++) {
716 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
717 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
718 }
719 return 0;
720 }
721
722 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
723 const struct pipe_poly_stipple *ps)
724 {
725 int i;
726 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
727 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
728 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
729 }
730 }
731
732 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
733 unsigned sample_mask)
734 {
735 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
736 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
737 }
738
739 void virgl_encoder_set_min_samples(struct virgl_context *ctx,
740 unsigned min_samples)
741 {
742 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_MIN_SAMPLES, 0, VIRGL_SET_MIN_SAMPLES_SIZE));
743 virgl_encoder_write_dword(ctx->cbuf, min_samples);
744 }
745
746 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
747 const struct pipe_clip_state *clip)
748 {
749 int i, j;
750 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
751 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
752 for (j = 0; j < 4; j++) {
753 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
754 }
755 }
756 }
757
758 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
759 struct virgl_resource *dst_res,
760 unsigned dst_level,
761 unsigned dstx, unsigned dsty, unsigned dstz,
762 struct virgl_resource *src_res,
763 unsigned src_level,
764 const struct pipe_box *src_box)
765 {
766 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
767 virgl_encoder_write_res(ctx, dst_res);
768 virgl_encoder_write_dword(ctx->cbuf, dst_level);
769 virgl_encoder_write_dword(ctx->cbuf, dstx);
770 virgl_encoder_write_dword(ctx->cbuf, dsty);
771 virgl_encoder_write_dword(ctx->cbuf, dstz);
772 virgl_encoder_write_res(ctx, src_res);
773 virgl_encoder_write_dword(ctx->cbuf, src_level);
774 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
775 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
776 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
777 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
778 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
779 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
780 return 0;
781 }
782
783 int virgl_encode_blit(struct virgl_context *ctx,
784 struct virgl_resource *dst_res,
785 struct virgl_resource *src_res,
786 const struct pipe_blit_info *blit)
787 {
788 uint32_t tmp;
789 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
790 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
791 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
792 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) |
793 VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) |
794 VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend);
795 virgl_encoder_write_dword(ctx->cbuf, tmp);
796 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
797 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
798
799 virgl_encoder_write_res(ctx, dst_res);
800 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
801 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
802 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
803 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
804 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
805 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
806 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
807 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
808
809 virgl_encoder_write_res(ctx, src_res);
810 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
811 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
812 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
813 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
814 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
815 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
816 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
817 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
818 return 0;
819 }
820
821 int virgl_encoder_create_query(struct virgl_context *ctx,
822 uint32_t handle,
823 uint query_type,
824 uint query_index,
825 struct virgl_resource *res,
826 uint32_t offset)
827 {
828 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
829 virgl_encoder_write_dword(ctx->cbuf, handle);
830 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
831 virgl_encoder_write_dword(ctx->cbuf, offset);
832 virgl_encoder_write_res(ctx, res);
833 return 0;
834 }
835
836 int virgl_encoder_begin_query(struct virgl_context *ctx,
837 uint32_t handle)
838 {
839 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
840 virgl_encoder_write_dword(ctx->cbuf, handle);
841 return 0;
842 }
843
844 int virgl_encoder_end_query(struct virgl_context *ctx,
845 uint32_t handle)
846 {
847 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
848 virgl_encoder_write_dword(ctx->cbuf, handle);
849 return 0;
850 }
851
852 int virgl_encoder_get_query_result(struct virgl_context *ctx,
853 uint32_t handle, boolean wait)
854 {
855 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
856 virgl_encoder_write_dword(ctx->cbuf, handle);
857 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
858 return 0;
859 }
860
861 int virgl_encoder_render_condition(struct virgl_context *ctx,
862 uint32_t handle, boolean condition,
863 enum pipe_render_cond_flag mode)
864 {
865 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
866 virgl_encoder_write_dword(ctx->cbuf, handle);
867 virgl_encoder_write_dword(ctx->cbuf, condition);
868 virgl_encoder_write_dword(ctx->cbuf, mode);
869 return 0;
870 }
871
872 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
873 unsigned num_targets,
874 struct pipe_stream_output_target **targets,
875 unsigned append_bitmask)
876 {
877 int i;
878
879 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
880 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
881 for (i = 0; i < num_targets; i++) {
882 struct virgl_so_target *tg = virgl_so_target(targets[i]);
883 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
884 }
885 return 0;
886 }
887
888
889 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
890 {
891 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
892 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
893 return 0;
894 }
895
896 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
897 {
898 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
899 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
900 return 0;
901 }
902
903 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
904 {
905 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
906 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
907 return 0;
908 }
909
910 int virgl_encode_bind_shader(struct virgl_context *ctx,
911 uint32_t handle, uint32_t type)
912 {
913 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
914 virgl_encoder_write_dword(ctx->cbuf, handle);
915 virgl_encoder_write_dword(ctx->cbuf, type);
916 return 0;
917 }
918
919 int virgl_encode_set_tess_state(struct virgl_context *ctx,
920 const float outer[4],
921 const float inner[2])
922 {
923 int i;
924 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_TESS_STATE, 0, 6));
925 for (i = 0; i < 4; i++)
926 virgl_encoder_write_dword(ctx->cbuf, fui(outer[i]));
927 for (i = 0; i < 2; i++)
928 virgl_encoder_write_dword(ctx->cbuf, fui(inner[i]));
929 return 0;
930 }
931
932 int virgl_encode_set_shader_buffers(struct virgl_context *ctx,
933 enum pipe_shader_type shader,
934 unsigned start_slot, unsigned count,
935 const struct pipe_shader_buffer *buffers)
936 {
937 int i;
938 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SHADER_BUFFERS, 0, VIRGL_SET_SHADER_BUFFER_SIZE(count)));
939
940 virgl_encoder_write_dword(ctx->cbuf, shader);
941 virgl_encoder_write_dword(ctx->cbuf, start_slot);
942 for (i = 0; i < count; i++) {
943 if (buffers) {
944 struct virgl_resource *res = virgl_resource(buffers[i].buffer);
945 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
946 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_size);
947 virgl_encoder_write_res(ctx, res);
948 } else {
949 virgl_encoder_write_dword(ctx->cbuf, 0);
950 virgl_encoder_write_dword(ctx->cbuf, 0);
951 virgl_encoder_write_dword(ctx->cbuf, 0);
952 }
953 }
954 return 0;
955 }
956
957 int virgl_encode_set_shader_images(struct virgl_context *ctx,
958 enum pipe_shader_type shader,
959 unsigned start_slot, unsigned count,
960 const struct pipe_image_view *images)
961 {
962 int i;
963 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SHADER_IMAGES, 0, VIRGL_SET_SHADER_IMAGE_SIZE(count)));
964
965 virgl_encoder_write_dword(ctx->cbuf, shader);
966 virgl_encoder_write_dword(ctx->cbuf, start_slot);
967 for (i = 0; i < count; i++) {
968 if (images) {
969 struct virgl_resource *res = virgl_resource(images[i].resource);
970 virgl_encoder_write_dword(ctx->cbuf, images[i].format);
971 virgl_encoder_write_dword(ctx->cbuf, images[i].access);
972 virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.offset);
973 virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.size);
974 virgl_encoder_write_res(ctx, res);
975 } else {
976 virgl_encoder_write_dword(ctx->cbuf, 0);
977 virgl_encoder_write_dword(ctx->cbuf, 0);
978 virgl_encoder_write_dword(ctx->cbuf, 0);
979 virgl_encoder_write_dword(ctx->cbuf, 0);
980 virgl_encoder_write_dword(ctx->cbuf, 0);
981 }
982 }
983 return 0;
984 }
985
986 int virgl_encode_memory_barrier(struct virgl_context *ctx,
987 unsigned flags)
988 {
989 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_MEMORY_BARRIER, 0, 1));
990 virgl_encoder_write_dword(ctx->cbuf, flags);
991 return 0;
992 }
993
994 int virgl_encode_launch_grid(struct virgl_context *ctx,
995 const struct pipe_grid_info *grid_info)
996 {
997 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_LAUNCH_GRID, 0, VIRGL_LAUNCH_GRID_SIZE));
998 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[0]);
999 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[1]);
1000 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[2]);
1001 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[0]);
1002 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[1]);
1003 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[2]);
1004 if (grid_info->indirect) {
1005 struct virgl_resource *res = virgl_resource(grid_info->indirect);
1006 virgl_encoder_write_res(ctx, res);
1007 } else
1008 virgl_encoder_write_dword(ctx->cbuf, 0);
1009 virgl_encoder_write_dword(ctx->cbuf, grid_info->indirect_offset);
1010 return 0;
1011 }