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6b800d3d0778abdc8706172876a218c10abbcd78
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24 #include <assert.h>
25 #include <string.h>
26
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_math.h"
30 #include "pipe/p_state.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_parse.h"
33
34 #include "virgl_context.h"
35 #include "virgl_encode.h"
36 #include "virgl_protocol.h"
37 #include "virgl_resource.h"
38 #include "virgl_screen.h"
39
40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
41 uint32_t dword)
42 {
43 int len = (dword >> 16);
44
45 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
46 ctx->base.flush(&ctx->base, NULL, 0);
47
48 virgl_encoder_write_dword(ctx->cbuf, dword);
49 return 0;
50 }
51
52 static void virgl_encoder_write_res(struct virgl_context *ctx,
53 struct virgl_resource *res)
54 {
55 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
56
57 if (res && res->hw_res)
58 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
59 else {
60 virgl_encoder_write_dword(ctx->cbuf, 0);
61 }
62 }
63
64 int virgl_encode_bind_object(struct virgl_context *ctx,
65 uint32_t handle, uint32_t object)
66 {
67 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
68 virgl_encoder_write_dword(ctx->cbuf, handle);
69 return 0;
70 }
71
72 int virgl_encode_delete_object(struct virgl_context *ctx,
73 uint32_t handle, uint32_t object)
74 {
75 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
76 virgl_encoder_write_dword(ctx->cbuf, handle);
77 return 0;
78 }
79
80 int virgl_encode_blend_state(struct virgl_context *ctx,
81 uint32_t handle,
82 const struct pipe_blend_state *blend_state)
83 {
84 uint32_t tmp;
85 int i;
86
87 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
88 virgl_encoder_write_dword(ctx->cbuf, handle);
89
90 tmp =
91 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
92 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
93 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
94 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
95 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
96
97 virgl_encoder_write_dword(ctx->cbuf, tmp);
98
99 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
100 virgl_encoder_write_dword(ctx->cbuf, tmp);
101
102 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
103 tmp =
104 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
105 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
106 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
107 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
108 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
109 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
110 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
111 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
112 virgl_encoder_write_dword(ctx->cbuf, tmp);
113 }
114 return 0;
115 }
116
117 int virgl_encode_dsa_state(struct virgl_context *ctx,
118 uint32_t handle,
119 const struct pipe_depth_stencil_alpha_state *dsa_state)
120 {
121 uint32_t tmp;
122 int i;
123 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
124 virgl_encoder_write_dword(ctx->cbuf, handle);
125
126 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
128 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
129 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
130 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
131 virgl_encoder_write_dword(ctx->cbuf, tmp);
132
133 for (i = 0; i < 2; i++) {
134 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
135 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
136 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
137 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
138 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
139 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
141 virgl_encoder_write_dword(ctx->cbuf, tmp);
142 }
143
144 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
145 return 0;
146 }
147 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
148 uint32_t handle,
149 const struct pipe_rasterizer_state *state)
150 {
151 uint32_t tmp;
152
153 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
154 virgl_encoder_write_dword(ctx->cbuf, handle);
155
156 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
157 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
158 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
159 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
160 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
161 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
162 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
163 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
164 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
165 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
166 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
167 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
168 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
169 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
170 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
171 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
172 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
173 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
174 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
175 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
176 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
177 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
178 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
179 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
180 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
181 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
182 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
183 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
184 VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
185
186 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
187 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
188 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
189 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
190 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
191 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
192 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
193 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
194 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
195 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
196 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
197 return 0;
198 }
199
200 static void virgl_emit_shader_header(struct virgl_context *ctx,
201 uint32_t handle, uint32_t len,
202 uint32_t type, uint32_t offlen,
203 uint32_t num_tokens)
204 {
205 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
206 virgl_encoder_write_dword(ctx->cbuf, handle);
207 virgl_encoder_write_dword(ctx->cbuf, type);
208 virgl_encoder_write_dword(ctx->cbuf, offlen);
209 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
210 }
211
212 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
213 const struct pipe_stream_output_info *so_info)
214 {
215 int num_outputs = 0;
216 int i;
217 uint32_t tmp;
218
219 if (so_info)
220 num_outputs = so_info->num_outputs;
221
222 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
223 if (num_outputs) {
224 for (i = 0; i < 4; i++)
225 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
226
227 for (i = 0; i < so_info->num_outputs; i++) {
228 tmp =
229 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
230 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
231 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
232 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
233 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
234 virgl_encoder_write_dword(ctx->cbuf, tmp);
235 virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream);
236 }
237 }
238 }
239
240 int virgl_encode_shader_state(struct virgl_context *ctx,
241 uint32_t handle,
242 uint32_t type,
243 const struct pipe_stream_output_info *so_info,
244 const struct tgsi_token *tokens)
245 {
246 char *str, *sptr;
247 uint32_t shader_len, len;
248 bool bret;
249 int num_tokens = tgsi_num_tokens(tokens);
250 int str_total_size = 65536;
251 int retry_size = 1;
252 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
253 bool first_pass;
254 str = CALLOC(1, str_total_size);
255 if (!str)
256 return -1;
257
258 do {
259 int old_size;
260
261 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
262 if (bret == false) {
263 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
264 old_size = str_total_size;
265 str_total_size = 65536 * ++retry_size;
266 str = REALLOC(str, old_size, str_total_size);
267 if (!str)
268 return -1;
269 }
270 } while (bret == false && retry_size < 10);
271
272 if (bret == false)
273 return -1;
274
275 shader_len = strlen(str) + 1;
276
277 left_bytes = shader_len;
278
279 base_hdr_size = 5;
280 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
281 first_pass = true;
282 sptr = str;
283 while (left_bytes) {
284 uint32_t length, offlen;
285 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
286 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
287 ctx->base.flush(&ctx->base, NULL, 0);
288
289 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
290
291 length = MIN2(thispass, left_bytes);
292 len = ((length + 3) / 4) + hdr_len;
293
294 if (first_pass)
295 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
296 else
297 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
298
299 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
300
301 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
302
303 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
304
305 sptr += length;
306 first_pass = false;
307 left_bytes -= length;
308 }
309
310 FREE(str);
311 return 0;
312 }
313
314
315 int virgl_encode_clear(struct virgl_context *ctx,
316 unsigned buffers,
317 const union pipe_color_union *color,
318 double depth, unsigned stencil)
319 {
320 int i;
321 uint64_t qword;
322
323 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
324 memcpy(&qword, &depth, sizeof(qword));
325
326 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
327 virgl_encoder_write_dword(ctx->cbuf, buffers);
328 for (i = 0; i < 4; i++)
329 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
330 virgl_encoder_write_qword(ctx->cbuf, qword);
331 virgl_encoder_write_dword(ctx->cbuf, stencil);
332 return 0;
333 }
334
335 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
336 const struct pipe_framebuffer_state *state)
337 {
338 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
339 int i;
340
341 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
342 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
343 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
344 for (i = 0; i < state->nr_cbufs; i++) {
345 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
346 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
347 }
348
349 return 0;
350 }
351
352 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
353 int start_slot,
354 int num_viewports,
355 const struct pipe_viewport_state *states)
356 {
357 int i,v;
358 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
359 virgl_encoder_write_dword(ctx->cbuf, start_slot);
360 for (v = 0; v < num_viewports; v++) {
361 for (i = 0; i < 3; i++)
362 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
363 for (i = 0; i < 3; i++)
364 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
365 }
366 return 0;
367 }
368
369 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
370 uint32_t handle,
371 unsigned num_elements,
372 const struct pipe_vertex_element *element)
373 {
374 int i;
375 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
376 virgl_encoder_write_dword(ctx->cbuf, handle);
377 for (i = 0; i < num_elements; i++) {
378 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
379 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
380 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
381 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
382 }
383 return 0;
384 }
385
386 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
387 unsigned num_buffers,
388 const struct pipe_vertex_buffer *buffers)
389 {
390 int i;
391 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
392 for (i = 0; i < num_buffers; i++) {
393 struct virgl_resource *res = virgl_resource(buffers[i].buffer.resource);
394 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
395 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
396 virgl_encoder_write_res(ctx, res);
397 }
398 return 0;
399 }
400
401 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
402 const struct virgl_indexbuf *ib)
403 {
404 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
405 struct virgl_resource *res = NULL;
406 if (ib)
407 res = virgl_resource(ib->buffer);
408
409 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
410 virgl_encoder_write_res(ctx, res);
411 if (ib) {
412 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
413 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
414 }
415 return 0;
416 }
417
418 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
419 const struct pipe_draw_info *info)
420 {
421 uint32_t length = VIRGL_DRAW_VBO_SIZE;
422 if (info->mode == PIPE_PRIM_PATCHES)
423 length = VIRGL_DRAW_VBO_SIZE_TESS;
424 if (info->indirect)
425 length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
426 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, length));
427 virgl_encoder_write_dword(ctx->cbuf, info->start);
428 virgl_encoder_write_dword(ctx->cbuf, info->count);
429 virgl_encoder_write_dword(ctx->cbuf, info->mode);
430 virgl_encoder_write_dword(ctx->cbuf, !!info->index_size);
431 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
432 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
433 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
434 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
435 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
436 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
437 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
438 if (info->count_from_stream_output)
439 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
440 else
441 virgl_encoder_write_dword(ctx->cbuf, 0);
442 if (length >= VIRGL_DRAW_VBO_SIZE_TESS) {
443 virgl_encoder_write_dword(ctx->cbuf, info->vertices_per_patch); /* vertices per patch */
444 virgl_encoder_write_dword(ctx->cbuf, info->drawid); /* drawid */
445 }
446 if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
447 virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
448 virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
449 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
450 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
451 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
452 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
453 }
454 return 0;
455 }
456
457 int virgl_encoder_create_surface(struct virgl_context *ctx,
458 uint32_t handle,
459 struct virgl_resource *res,
460 const struct pipe_surface *templat)
461 {
462 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
463 virgl_encoder_write_dword(ctx->cbuf, handle);
464 virgl_encoder_write_res(ctx, res);
465 virgl_encoder_write_dword(ctx->cbuf, templat->format);
466 if (templat->texture->target == PIPE_BUFFER) {
467 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
468 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
469
470 } else {
471 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
472 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
473 }
474 return 0;
475 }
476
477 int virgl_encoder_create_so_target(struct virgl_context *ctx,
478 uint32_t handle,
479 struct virgl_resource *res,
480 unsigned buffer_offset,
481 unsigned buffer_size)
482 {
483 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
484 virgl_encoder_write_dword(ctx->cbuf, handle);
485 virgl_encoder_write_res(ctx, res);
486 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
487 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
488 return 0;
489 }
490
491 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
492 struct virgl_resource *res,
493 unsigned level, unsigned usage,
494 const struct pipe_box *box,
495 unsigned stride, unsigned layer_stride)
496 {
497 virgl_encoder_write_res(ctx, res);
498 virgl_encoder_write_dword(ctx->cbuf, level);
499 virgl_encoder_write_dword(ctx->cbuf, usage);
500 virgl_encoder_write_dword(ctx->cbuf, stride);
501 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
502 virgl_encoder_write_dword(ctx->cbuf, box->x);
503 virgl_encoder_write_dword(ctx->cbuf, box->y);
504 virgl_encoder_write_dword(ctx->cbuf, box->z);
505 virgl_encoder_write_dword(ctx->cbuf, box->width);
506 virgl_encoder_write_dword(ctx->cbuf, box->height);
507 virgl_encoder_write_dword(ctx->cbuf, box->depth);
508 }
509
510 int virgl_encoder_inline_write(struct virgl_context *ctx,
511 struct virgl_resource *res,
512 unsigned level, unsigned usage,
513 const struct pipe_box *box,
514 const void *data, unsigned stride,
515 unsigned layer_stride)
516 {
517 uint32_t size = (stride ? stride : box->width) * box->height;
518 uint32_t length, thispass, left_bytes;
519 struct pipe_box mybox = *box;
520
521 length = 11 + (size + 3) / 4;
522 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
523 if (box->height > 1 || box->depth > 1) {
524 debug_printf("inline transfer failed due to multi dimensions and too large\n");
525 assert(0);
526 }
527 }
528
529 left_bytes = size;
530 while (left_bytes) {
531 if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
532 ctx->base.flush(&ctx->base, NULL, 0);
533
534 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
535
536 length = MIN2(thispass, left_bytes);
537
538 mybox.width = length;
539 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
540 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
541 virgl_encoder_write_block(ctx->cbuf, data, length);
542 left_bytes -= length;
543 mybox.x += length;
544 data += length;
545 }
546 return 0;
547 }
548
549 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
550 struct virgl_resource *res)
551 {
552 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
553 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
554 return 0;
555 }
556
557 int virgl_encode_sampler_state(struct virgl_context *ctx,
558 uint32_t handle,
559 const struct pipe_sampler_state *state)
560 {
561 uint32_t tmp;
562 int i;
563 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
564 virgl_encoder_write_dword(ctx->cbuf, handle);
565
566 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
567 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
568 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
569 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
570 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
571 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
572 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
573 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
574 VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map);
575
576 virgl_encoder_write_dword(ctx->cbuf, tmp);
577 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
578 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
579 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
580 for (i = 0; i < 4; i++)
581 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
582 return 0;
583 }
584
585
586 int virgl_encode_sampler_view(struct virgl_context *ctx,
587 uint32_t handle,
588 struct virgl_resource *res,
589 const struct pipe_sampler_view *state)
590 {
591 unsigned elem_size = util_format_get_blocksize(state->format);
592 struct virgl_screen *rs = virgl_screen(ctx->base.screen);
593 uint32_t tmp;
594 uint32_t dword_fmt_target = state->format;
595 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
596 virgl_encoder_write_dword(ctx->cbuf, handle);
597 virgl_encoder_write_res(ctx, res);
598 if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
599 dword_fmt_target |= (state->target << 24);
600 virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
601 if (res->u.b.target == PIPE_BUFFER) {
602 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
603 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
604 } else {
605 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
606 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
607 }
608 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
609 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
610 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
611 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
612 virgl_encoder_write_dword(ctx->cbuf, tmp);
613 return 0;
614 }
615
616 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
617 uint32_t shader_type,
618 uint32_t start_slot,
619 uint32_t num_views,
620 struct virgl_sampler_view **views)
621 {
622 int i;
623 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
624 virgl_encoder_write_dword(ctx->cbuf, shader_type);
625 virgl_encoder_write_dword(ctx->cbuf, start_slot);
626 for (i = 0; i < num_views; i++) {
627 uint32_t handle = views[i] ? views[i]->handle : 0;
628 virgl_encoder_write_dword(ctx->cbuf, handle);
629 }
630 return 0;
631 }
632
633 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
634 uint32_t shader_type,
635 uint32_t start_slot,
636 uint32_t num_handles,
637 uint32_t *handles)
638 {
639 int i;
640 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
641 virgl_encoder_write_dword(ctx->cbuf, shader_type);
642 virgl_encoder_write_dword(ctx->cbuf, start_slot);
643 for (i = 0; i < num_handles; i++)
644 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
645 return 0;
646 }
647
648 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
649 uint32_t shader,
650 uint32_t index,
651 uint32_t size,
652 const void *data)
653 {
654 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
655 virgl_encoder_write_dword(ctx->cbuf, shader);
656 virgl_encoder_write_dword(ctx->cbuf, index);
657 if (data)
658 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
659 return 0;
660 }
661
662 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
663 uint32_t shader,
664 uint32_t index,
665 uint32_t offset,
666 uint32_t length,
667 struct virgl_resource *res)
668 {
669 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
670 virgl_encoder_write_dword(ctx->cbuf, shader);
671 virgl_encoder_write_dword(ctx->cbuf, index);
672 virgl_encoder_write_dword(ctx->cbuf, offset);
673 virgl_encoder_write_dword(ctx->cbuf, length);
674 virgl_encoder_write_res(ctx, res);
675 return 0;
676 }
677
678
679 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
680 const struct pipe_stencil_ref *ref)
681 {
682 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
683 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
684 return 0;
685 }
686
687 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
688 const struct pipe_blend_color *color)
689 {
690 int i;
691 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
692 for (i = 0; i < 4; i++)
693 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
694 return 0;
695 }
696
697 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
698 unsigned start_slot,
699 int num_scissors,
700 const struct pipe_scissor_state *ss)
701 {
702 int i;
703 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
704 virgl_encoder_write_dword(ctx->cbuf, start_slot);
705 for (i = 0; i < num_scissors; i++) {
706 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
707 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
708 }
709 return 0;
710 }
711
712 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
713 const struct pipe_poly_stipple *ps)
714 {
715 int i;
716 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
717 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
718 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
719 }
720 }
721
722 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
723 unsigned sample_mask)
724 {
725 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
726 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
727 }
728
729 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
730 const struct pipe_clip_state *clip)
731 {
732 int i, j;
733 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
734 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
735 for (j = 0; j < 4; j++) {
736 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
737 }
738 }
739 }
740
741 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
742 struct virgl_resource *dst_res,
743 unsigned dst_level,
744 unsigned dstx, unsigned dsty, unsigned dstz,
745 struct virgl_resource *src_res,
746 unsigned src_level,
747 const struct pipe_box *src_box)
748 {
749 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
750 virgl_encoder_write_res(ctx, dst_res);
751 virgl_encoder_write_dword(ctx->cbuf, dst_level);
752 virgl_encoder_write_dword(ctx->cbuf, dstx);
753 virgl_encoder_write_dword(ctx->cbuf, dsty);
754 virgl_encoder_write_dword(ctx->cbuf, dstz);
755 virgl_encoder_write_res(ctx, src_res);
756 virgl_encoder_write_dword(ctx->cbuf, src_level);
757 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
758 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
759 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
760 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
761 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
762 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
763 return 0;
764 }
765
766 int virgl_encode_blit(struct virgl_context *ctx,
767 struct virgl_resource *dst_res,
768 struct virgl_resource *src_res,
769 const struct pipe_blit_info *blit)
770 {
771 uint32_t tmp;
772 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
773 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
774 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
775 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) |
776 VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) |
777 VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend);
778 virgl_encoder_write_dword(ctx->cbuf, tmp);
779 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
780 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
781
782 virgl_encoder_write_res(ctx, dst_res);
783 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
784 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
785 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
786 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
787 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
788 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
789 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
790 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
791
792 virgl_encoder_write_res(ctx, src_res);
793 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
794 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
795 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
796 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
797 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
798 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
799 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
800 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
801 return 0;
802 }
803
804 int virgl_encoder_create_query(struct virgl_context *ctx,
805 uint32_t handle,
806 uint query_type,
807 uint query_index,
808 struct virgl_resource *res,
809 uint32_t offset)
810 {
811 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
812 virgl_encoder_write_dword(ctx->cbuf, handle);
813 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
814 virgl_encoder_write_dword(ctx->cbuf, offset);
815 virgl_encoder_write_res(ctx, res);
816 return 0;
817 }
818
819 int virgl_encoder_begin_query(struct virgl_context *ctx,
820 uint32_t handle)
821 {
822 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
823 virgl_encoder_write_dword(ctx->cbuf, handle);
824 return 0;
825 }
826
827 int virgl_encoder_end_query(struct virgl_context *ctx,
828 uint32_t handle)
829 {
830 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
831 virgl_encoder_write_dword(ctx->cbuf, handle);
832 return 0;
833 }
834
835 int virgl_encoder_get_query_result(struct virgl_context *ctx,
836 uint32_t handle, boolean wait)
837 {
838 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
839 virgl_encoder_write_dword(ctx->cbuf, handle);
840 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
841 return 0;
842 }
843
844 int virgl_encoder_render_condition(struct virgl_context *ctx,
845 uint32_t handle, boolean condition,
846 enum pipe_render_cond_flag mode)
847 {
848 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
849 virgl_encoder_write_dword(ctx->cbuf, handle);
850 virgl_encoder_write_dword(ctx->cbuf, condition);
851 virgl_encoder_write_dword(ctx->cbuf, mode);
852 return 0;
853 }
854
855 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
856 unsigned num_targets,
857 struct pipe_stream_output_target **targets,
858 unsigned append_bitmask)
859 {
860 int i;
861
862 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
863 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
864 for (i = 0; i < num_targets; i++) {
865 struct virgl_so_target *tg = virgl_so_target(targets[i]);
866 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
867 }
868 return 0;
869 }
870
871
872 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
873 {
874 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
875 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
876 return 0;
877 }
878
879 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
880 {
881 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
882 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
883 return 0;
884 }
885
886 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
887 {
888 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
889 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
890 return 0;
891 }
892
893 int virgl_encode_bind_shader(struct virgl_context *ctx,
894 uint32_t handle, uint32_t type)
895 {
896 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
897 virgl_encoder_write_dword(ctx->cbuf, handle);
898 virgl_encoder_write_dword(ctx->cbuf, type);
899 return 0;
900 }
901
902 int virgl_encode_set_tess_state(struct virgl_context *ctx,
903 const float outer[4],
904 const float inner[2])
905 {
906 int i;
907 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_TESS_STATE, 0, 6));
908 for (i = 0; i < 4; i++)
909 virgl_encoder_write_dword(ctx->cbuf, fui(outer[i]));
910 for (i = 0; i < 2; i++)
911 virgl_encoder_write_dword(ctx->cbuf, fui(inner[i]));
912 return 0;
913 }