src/gallium/drivers/virgl/virgl_encode.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdint.h>
  24 #include <assert.h>
  25 #include <string.h>
  26
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_math.h"
  30 #include "pipe/p_state.h"
  31 #include "tgsi/tgsi_dump.h"
  32 #include "tgsi/tgsi_parse.h"
  33
  34 #include "virgl_context.h"
  35 #include "virgl_encode.h"
  36 #include "virgl_protocol.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_screen.h"
  39
  40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
  41                                         uint32_t dword)
  42 {
  43    int len = (dword >> 16);
  44
  45    if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
  46       ctx->base.flush(&ctx->base, NULL, 0);
  47
  48    virgl_encoder_write_dword(ctx->cbuf, dword);
  49    return 0;
  50 }
  51
  52 static void virgl_encoder_write_res(struct virgl_context *ctx,
  53                                     struct virgl_resource *res)
  54 {
  55    struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
  56
  57    if (res && res->hw_res)
  58       vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
  59    else {
  60       virgl_encoder_write_dword(ctx->cbuf, 0);
  61    }
  62 }
  63
  64 int virgl_encode_bind_object(struct virgl_context *ctx,
  65                             uint32_t handle, uint32_t object)
  66 {
  67    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
  68    virgl_encoder_write_dword(ctx->cbuf, handle);
  69    return 0;
  70 }
  71
  72 int virgl_encode_delete_object(struct virgl_context *ctx,
  73                               uint32_t handle, uint32_t object)
  74 {
  75    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
  76    virgl_encoder_write_dword(ctx->cbuf, handle);
  77    return 0;
  78 }
  79
  80 int virgl_encode_blend_state(struct virgl_context *ctx,
  81                             uint32_t handle,
  82                             const struct pipe_blend_state *blend_state)
  83 {
  84    uint32_t tmp;
  85    int i;
  86
  87    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
  88    virgl_encoder_write_dword(ctx->cbuf, handle);
  89
  90    tmp =
  91       VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
  92       VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
  93       VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
  94       VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
  95       VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
  96
  97    virgl_encoder_write_dword(ctx->cbuf, tmp);
  98
  99    tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
 100    virgl_encoder_write_dword(ctx->cbuf, tmp);
 101
 102    for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
 103       tmp =
 104          VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
 105          VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
 106          VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
 107          VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
 108          VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
 109          VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
 110          VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
 111          VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
 112       virgl_encoder_write_dword(ctx->cbuf, tmp);
 113    }
 114    return 0;
 115 }
 116
 117 int virgl_encode_dsa_state(struct virgl_context *ctx,
 118                           uint32_t handle,
 119                           const struct pipe_depth_stencil_alpha_state *dsa_state)
 120 {
 121    uint32_t tmp;
 122    int i;
 123    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
 124    virgl_encoder_write_dword(ctx->cbuf, handle);
 125
 126    tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
 127       VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
 128       VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
 129       VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
 130       VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
 131    virgl_encoder_write_dword(ctx->cbuf, tmp);
 132
 133    for (i = 0; i < 2; i++) {
 134       tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
 135          VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
 136          VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
 137          VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
 138          VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
 139          VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
 140          VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
 141       virgl_encoder_write_dword(ctx->cbuf, tmp);
 142    }
 143
 144    virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
 145    return 0;
 146 }
 147 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
 148                                   uint32_t handle,
 149                                   const struct pipe_rasterizer_state *state)
 150 {
 151    uint32_t tmp;
 152
 153    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
 154    virgl_encoder_write_dword(ctx->cbuf, handle);
 155
 156    tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
 157       VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
 158       VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
 159       VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
 160       VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
 161       VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
 162       VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
 163       VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
 164       VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
 165       VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
 166       VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
 167       VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
 168       VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
 169       VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
 170       VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
 171       VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
 172       VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
 173       VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
 174       VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
 175       VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
 176       VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
 177       VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
 178       VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
 179       VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
 180       VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
 181       VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
 182       VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
 183       VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
 184       VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
 185
 186    virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
 187    virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
 188    virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
 189    tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
 190       VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
 191       VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
 192    virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
 193    virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
 194    virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
 195    virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
 196    virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
 197    return 0;
 198 }
 199
 200 static void virgl_emit_shader_header(struct virgl_context *ctx,
 201                                      uint32_t handle, uint32_t len,
 202                                      uint32_t type, uint32_t offlen,
 203                                      uint32_t num_tokens)
 204 {
 205    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
 206    virgl_encoder_write_dword(ctx->cbuf, handle);
 207    virgl_encoder_write_dword(ctx->cbuf, type);
 208    virgl_encoder_write_dword(ctx->cbuf, offlen);
 209    virgl_encoder_write_dword(ctx->cbuf, num_tokens);
 210 }
 211
 212 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
 213                                         const struct pipe_stream_output_info *so_info)
 214 {
 215    int num_outputs = 0;
 216    int i;
 217    uint32_t tmp;
 218
 219    if (so_info)
 220       num_outputs = so_info->num_outputs;
 221
 222    virgl_encoder_write_dword(ctx->cbuf, num_outputs);
 223    if (num_outputs) {
 224       for (i = 0; i < 4; i++)
 225          virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
 226
 227       for (i = 0; i < so_info->num_outputs; i++) {
 228          tmp =
 229            VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
 230            VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
 231            VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
 232            VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
 233            VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
 234          virgl_encoder_write_dword(ctx->cbuf, tmp);
 235          virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream);
 236       }
 237    }
 238 }
 239
 240 int virgl_encode_shader_state(struct virgl_context *ctx,
 241                               uint32_t handle,
 242                               uint32_t type,
 243                               const struct pipe_stream_output_info *so_info,
 244                               const struct tgsi_token *tokens)
 245 {
 246    char *str, *sptr;
 247    uint32_t shader_len, len;
 248    bool bret;
 249    int num_tokens = tgsi_num_tokens(tokens);
 250    int str_total_size = 65536;
 251    int retry_size = 1;
 252    uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
 253    bool first_pass;
 254    str = CALLOC(1, str_total_size);
 255    if (!str)
 256       return -1;
 257
 258    do {
 259       int old_size;
 260
 261       bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
 262       if (bret == false) {
 263          fprintf(stderr, "Failed to translate shader in available space - trying again\n");
 264          old_size = str_total_size;
 265          str_total_size = 65536 * ++retry_size;
 266          str = REALLOC(str, old_size, str_total_size);
 267          if (!str)
 268             return -1;
 269       }
 270    } while (bret == false && retry_size < 10);
 271
 272    if (bret == false)
 273       return -1;
 274
 275    shader_len = strlen(str) + 1;
 276
 277    left_bytes = shader_len;
 278
 279    base_hdr_size = 5;
 280    strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
 281    first_pass = true;
 282    sptr = str;
 283    while (left_bytes) {
 284       uint32_t length, offlen;
 285       int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
 286       if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
 287          ctx->base.flush(&ctx->base, NULL, 0);
 288
 289       thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
 290
 291       length = MIN2(thispass, left_bytes);
 292       len = ((length + 3) / 4) + hdr_len;
 293
 294       if (first_pass)
 295          offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
 296       else
 297          offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
 298
 299       virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
 300
 301       virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
 302
 303       virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
 304
 305       sptr += length;
 306       first_pass = false;
 307       left_bytes -= length;
 308    }
 309
 310    FREE(str);
 311    return 0;
 312 }
 313
 314
 315 int virgl_encode_clear(struct virgl_context *ctx,
 316                       unsigned buffers,
 317                       const union pipe_color_union *color,
 318                       double depth, unsigned stencil)
 319 {
 320    int i;
 321    uint64_t qword;
 322
 323    STATIC_ASSERT(sizeof(qword) == sizeof(depth));
 324    memcpy(&qword, &depth, sizeof(qword));
 325
 326    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
 327    virgl_encoder_write_dword(ctx->cbuf, buffers);
 328    for (i = 0; i < 4; i++)
 329       virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
 330    virgl_encoder_write_qword(ctx->cbuf, qword);
 331    virgl_encoder_write_dword(ctx->cbuf, stencil);
 332    return 0;
 333 }
 334
 335 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
 336                                        const struct pipe_framebuffer_state *state)
 337 {
 338    struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
 339    int i;
 340
 341    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
 342    virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
 343    virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
 344    for (i = 0; i < state->nr_cbufs; i++) {
 345       struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
 346       virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
 347    }
 348
 349    return 0;
 350 }
 351
 352 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
 353                                       int start_slot,
 354                                       int num_viewports,
 355                                       const struct pipe_viewport_state *states)
 356 {
 357    int i,v;
 358    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
 359    virgl_encoder_write_dword(ctx->cbuf, start_slot);
 360    for (v = 0; v < num_viewports; v++) {
 361       for (i = 0; i < 3; i++)
 362          virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
 363       for (i = 0; i < 3; i++)
 364          virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
 365    }
 366    return 0;
 367 }
 368
 369 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
 370                                         uint32_t handle,
 371                                         unsigned num_elements,
 372                                         const struct pipe_vertex_element *element)
 373 {
 374    int i;
 375    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
 376    virgl_encoder_write_dword(ctx->cbuf, handle);
 377    for (i = 0; i < num_elements; i++) {
 378       virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
 379       virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
 380       virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
 381       virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
 382    }
 383    return 0;
 384 }
 385
 386 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
 387                                     unsigned num_buffers,
 388                                     const struct pipe_vertex_buffer *buffers)
 389 {
 390    int i;
 391    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
 392    for (i = 0; i < num_buffers; i++) {
 393       struct virgl_resource *res = virgl_resource(buffers[i].buffer.resource);
 394       virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
 395       virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
 396       virgl_encoder_write_res(ctx, res);
 397    }
 398    return 0;
 399 }
 400
 401 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
 402                                   const struct virgl_indexbuf *ib)
 403 {
 404    int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
 405    struct virgl_resource *res = NULL;
 406    if (ib)
 407       res = virgl_resource(ib->buffer);
 408
 409    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
 410    virgl_encoder_write_res(ctx, res);
 411    if (ib) {
 412       virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
 413       virgl_encoder_write_dword(ctx->cbuf, ib->offset);
 414    }
 415    return 0;
 416 }
 417
 418 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
 419                           const struct pipe_draw_info *info)
 420 {
 421    uint32_t length = VIRGL_DRAW_VBO_SIZE;
 422    if (info->indirect)
 423       length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
 424    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, length));
 425    virgl_encoder_write_dword(ctx->cbuf, info->start);
 426    virgl_encoder_write_dword(ctx->cbuf, info->count);
 427    virgl_encoder_write_dword(ctx->cbuf, info->mode);
 428    virgl_encoder_write_dword(ctx->cbuf, !!info->index_size);
 429    virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
 430    virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
 431    virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
 432    virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
 433    virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
 434    virgl_encoder_write_dword(ctx->cbuf, info->min_index);
 435    virgl_encoder_write_dword(ctx->cbuf, info->max_index);
 436    if (info->count_from_stream_output)
 437       virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
 438    else
 439       virgl_encoder_write_dword(ctx->cbuf, 0);
 440    if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
 441       virgl_encoder_write_dword(ctx->cbuf, 0); /* vertices per patch */
 442       virgl_encoder_write_dword(ctx->cbuf, 0); /* drawid */
 443       virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
 444       virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
 445       virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
 446       virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
 447       virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
 448       virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
 449    }
 450    return 0;
 451 }
 452
 453 int virgl_encoder_create_surface(struct virgl_context *ctx,
 454                                 uint32_t handle,
 455                                 struct virgl_resource *res,
 456                                 const struct pipe_surface *templat)
 457 {
 458    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
 459    virgl_encoder_write_dword(ctx->cbuf, handle);
 460    virgl_encoder_write_res(ctx, res);
 461    virgl_encoder_write_dword(ctx->cbuf, templat->format);
 462    if (templat->texture->target == PIPE_BUFFER) {
 463       virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
 464       virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
 465
 466    } else {
 467       virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
 468       virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
 469    }
 470    return 0;
 471 }
 472
 473 int virgl_encoder_create_so_target(struct virgl_context *ctx,
 474                                   uint32_t handle,
 475                                   struct virgl_resource *res,
 476                                   unsigned buffer_offset,
 477                                   unsigned buffer_size)
 478 {
 479    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
 480    virgl_encoder_write_dword(ctx->cbuf, handle);
 481    virgl_encoder_write_res(ctx, res);
 482    virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
 483    virgl_encoder_write_dword(ctx->cbuf, buffer_size);
 484    return 0;
 485 }
 486
 487 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
 488                                            struct virgl_resource *res,
 489                                            unsigned level, unsigned usage,
 490                                            const struct pipe_box *box,
 491                                            unsigned stride, unsigned layer_stride)
 492 {
 493    virgl_encoder_write_res(ctx, res);
 494    virgl_encoder_write_dword(ctx->cbuf, level);
 495    virgl_encoder_write_dword(ctx->cbuf, usage);
 496    virgl_encoder_write_dword(ctx->cbuf, stride);
 497    virgl_encoder_write_dword(ctx->cbuf, layer_stride);
 498    virgl_encoder_write_dword(ctx->cbuf, box->x);
 499    virgl_encoder_write_dword(ctx->cbuf, box->y);
 500    virgl_encoder_write_dword(ctx->cbuf, box->z);
 501    virgl_encoder_write_dword(ctx->cbuf, box->width);
 502    virgl_encoder_write_dword(ctx->cbuf, box->height);
 503    virgl_encoder_write_dword(ctx->cbuf, box->depth);
 504 }
 505
 506 int virgl_encoder_inline_write(struct virgl_context *ctx,
 507                               struct virgl_resource *res,
 508                               unsigned level, unsigned usage,
 509                               const struct pipe_box *box,
 510                               const void *data, unsigned stride,
 511                               unsigned layer_stride)
 512 {
 513    uint32_t size = (stride ? stride : box->width) * box->height;
 514    uint32_t length, thispass, left_bytes;
 515    struct pipe_box mybox = *box;
 516
 517    length = 11 + (size + 3) / 4;
 518    if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
 519       if (box->height > 1 || box->depth > 1) {
 520          debug_printf("inline transfer failed due to multi dimensions and too large\n");
 521          assert(0);
 522       }
 523    }
 524
 525    left_bytes = size;
 526    while (left_bytes) {
 527       if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
 528          ctx->base.flush(&ctx->base, NULL, 0);
 529
 530       thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
 531
 532       length = MIN2(thispass, left_bytes);
 533
 534       mybox.width = length;
 535       virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
 536       virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
 537       virgl_encoder_write_block(ctx->cbuf, data, length);
 538       left_bytes -= length;
 539       mybox.x += length;
 540       data += length;
 541    }
 542    return 0;
 543 }
 544
 545 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
 546                                    struct virgl_resource *res)
 547 {
 548 //   virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
 549 //   virgl_encoder_write_dword(ctx->cbuf, res_handle);
 550    return 0;
 551 }
 552
 553 int virgl_encode_sampler_state(struct virgl_context *ctx,
 554                               uint32_t handle,
 555                               const struct pipe_sampler_state *state)
 556 {
 557    uint32_t tmp;
 558    int i;
 559    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
 560    virgl_encoder_write_dword(ctx->cbuf, handle);
 561
 562    tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
 563       VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
 564       VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
 565       VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
 566       VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
 567       VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
 568       VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
 569       VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
 570       VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map);
 571
 572    virgl_encoder_write_dword(ctx->cbuf, tmp);
 573    virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
 574    virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
 575    virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
 576    for (i = 0; i <  4; i++)
 577       virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
 578    return 0;
 579 }
 580
 581
 582 int virgl_encode_sampler_view(struct virgl_context *ctx,
 583                              uint32_t handle,
 584                              struct virgl_resource *res,
 585                              const struct pipe_sampler_view *state)
 586 {
 587    unsigned elem_size = util_format_get_blocksize(state->format);
 588
 589    uint32_t tmp;
 590    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
 591    virgl_encoder_write_dword(ctx->cbuf, handle);
 592    virgl_encoder_write_res(ctx, res);
 593    virgl_encoder_write_dword(ctx->cbuf, state->format);
 594    if (res->u.b.target == PIPE_BUFFER) {
 595       virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
 596       virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
 597    } else {
 598       virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
 599       virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
 600    }
 601    tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
 602       VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
 603       VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
 604       VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
 605    virgl_encoder_write_dword(ctx->cbuf, tmp);
 606    return 0;
 607 }
 608
 609 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
 610                                   uint32_t shader_type,
 611                                   uint32_t start_slot,
 612                                   uint32_t num_views,
 613                                   struct virgl_sampler_view **views)
 614 {
 615    int i;
 616    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
 617    virgl_encoder_write_dword(ctx->cbuf, shader_type);
 618    virgl_encoder_write_dword(ctx->cbuf, start_slot);
 619    for (i = 0; i < num_views; i++) {
 620       uint32_t handle = views[i] ? views[i]->handle : 0;
 621       virgl_encoder_write_dword(ctx->cbuf, handle);
 622    }
 623    return 0;
 624 }
 625
 626 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
 627                                     uint32_t shader_type,
 628                                     uint32_t start_slot,
 629                                     uint32_t num_handles,
 630                                     uint32_t *handles)
 631 {
 632    int i;
 633    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
 634    virgl_encoder_write_dword(ctx->cbuf, shader_type);
 635    virgl_encoder_write_dword(ctx->cbuf, start_slot);
 636    for (i = 0; i < num_handles; i++)
 637       virgl_encoder_write_dword(ctx->cbuf, handles[i]);
 638    return 0;
 639 }
 640
 641 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
 642                                        uint32_t shader,
 643                                        uint32_t index,
 644                                        uint32_t size,
 645                                        const void *data)
 646 {
 647    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
 648    virgl_encoder_write_dword(ctx->cbuf, shader);
 649    virgl_encoder_write_dword(ctx->cbuf, index);
 650    if (data)
 651       virgl_encoder_write_block(ctx->cbuf, data, size * 4);
 652    return 0;
 653 }
 654
 655 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
 656                                      uint32_t shader,
 657                                      uint32_t index,
 658                                      uint32_t offset,
 659                                      uint32_t length,
 660                                      struct virgl_resource *res)
 661 {
 662    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
 663    virgl_encoder_write_dword(ctx->cbuf, shader);
 664    virgl_encoder_write_dword(ctx->cbuf, index);
 665    virgl_encoder_write_dword(ctx->cbuf, offset);
 666    virgl_encoder_write_dword(ctx->cbuf, length);
 667    virgl_encoder_write_res(ctx, res);
 668    return 0;
 669 }
 670
 671
 672 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
 673                                  const struct pipe_stencil_ref *ref)
 674 {
 675    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
 676    virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
 677    return 0;
 678 }
 679
 680 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
 681                                  const struct pipe_blend_color *color)
 682 {
 683    int i;
 684    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
 685    for (i = 0; i < 4; i++)
 686       virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
 687    return 0;
 688 }
 689
 690 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
 691                                     unsigned start_slot,
 692                                     int num_scissors,
 693                                     const struct pipe_scissor_state *ss)
 694 {
 695    int i;
 696    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
 697    virgl_encoder_write_dword(ctx->cbuf, start_slot);
 698    for (i = 0; i < num_scissors; i++) {
 699       virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
 700       virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
 701    }
 702    return 0;
 703 }
 704
 705 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
 706                                       const struct pipe_poly_stipple *ps)
 707 {
 708    int i;
 709    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
 710    for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
 711       virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
 712    }
 713 }
 714
 715 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
 716                                   unsigned sample_mask)
 717 {
 718    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
 719    virgl_encoder_write_dword(ctx->cbuf, sample_mask);
 720 }
 721
 722 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
 723                                  const struct pipe_clip_state *clip)
 724 {
 725    int i, j;
 726    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
 727    for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
 728       for (j = 0; j < 4; j++) {
 729          virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
 730       }
 731    }
 732 }
 733
 734 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
 735                                      struct virgl_resource *dst_res,
 736                                      unsigned dst_level,
 737                                      unsigned dstx, unsigned dsty, unsigned dstz,
 738                                      struct virgl_resource *src_res,
 739                                      unsigned src_level,
 740                                      const struct pipe_box *src_box)
 741 {
 742    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
 743    virgl_encoder_write_res(ctx, dst_res);
 744    virgl_encoder_write_dword(ctx->cbuf, dst_level);
 745    virgl_encoder_write_dword(ctx->cbuf, dstx);
 746    virgl_encoder_write_dword(ctx->cbuf, dsty);
 747    virgl_encoder_write_dword(ctx->cbuf, dstz);
 748    virgl_encoder_write_res(ctx, src_res);
 749    virgl_encoder_write_dword(ctx->cbuf, src_level);
 750    virgl_encoder_write_dword(ctx->cbuf, src_box->x);
 751    virgl_encoder_write_dword(ctx->cbuf, src_box->y);
 752    virgl_encoder_write_dword(ctx->cbuf, src_box->z);
 753    virgl_encoder_write_dword(ctx->cbuf, src_box->width);
 754    virgl_encoder_write_dword(ctx->cbuf, src_box->height);
 755    virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
 756    return 0;
 757 }
 758
 759 int virgl_encode_blit(struct virgl_context *ctx,
 760                      struct virgl_resource *dst_res,
 761                      struct virgl_resource *src_res,
 762                      const struct pipe_blit_info *blit)
 763 {
 764    uint32_t tmp;
 765    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
 766    tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
 767       VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
 768       VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) |
 769       VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) |
 770       VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend);
 771    virgl_encoder_write_dword(ctx->cbuf, tmp);
 772    virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
 773    virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
 774
 775    virgl_encoder_write_res(ctx, dst_res);
 776    virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
 777    virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
 778    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
 779    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
 780    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
 781    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
 782    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
 783    virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
 784
 785    virgl_encoder_write_res(ctx, src_res);
 786    virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
 787    virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
 788    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
 789    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
 790    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
 791    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
 792    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
 793    virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
 794    return 0;
 795 }
 796
 797 int virgl_encoder_create_query(struct virgl_context *ctx,
 798                               uint32_t handle,
 799                               uint query_type,
 800                               uint query_index,
 801                               struct virgl_resource *res,
 802                               uint32_t offset)
 803 {
 804    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
 805    virgl_encoder_write_dword(ctx->cbuf, handle);
 806    virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
 807    virgl_encoder_write_dword(ctx->cbuf, offset);
 808    virgl_encoder_write_res(ctx, res);
 809    return 0;
 810 }
 811
 812 int virgl_encoder_begin_query(struct virgl_context *ctx,
 813                              uint32_t handle)
 814 {
 815    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
 816    virgl_encoder_write_dword(ctx->cbuf, handle);
 817    return 0;
 818 }
 819
 820 int virgl_encoder_end_query(struct virgl_context *ctx,
 821                            uint32_t handle)
 822 {
 823    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
 824    virgl_encoder_write_dword(ctx->cbuf, handle);
 825    return 0;
 826 }
 827
 828 int virgl_encoder_get_query_result(struct virgl_context *ctx,
 829                                   uint32_t handle, boolean wait)
 830 {
 831    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
 832    virgl_encoder_write_dword(ctx->cbuf, handle);
 833    virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
 834    return 0;
 835 }
 836
 837 int virgl_encoder_render_condition(struct virgl_context *ctx,
 838                                   uint32_t handle, boolean condition,
 839                                   enum pipe_render_cond_flag mode)
 840 {
 841    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
 842    virgl_encoder_write_dword(ctx->cbuf, handle);
 843    virgl_encoder_write_dword(ctx->cbuf, condition);
 844    virgl_encoder_write_dword(ctx->cbuf, mode);
 845    return 0;
 846 }
 847
 848 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
 849                                 unsigned num_targets,
 850                                 struct pipe_stream_output_target **targets,
 851                                 unsigned append_bitmask)
 852 {
 853    int i;
 854
 855    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
 856    virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
 857    for (i = 0; i < num_targets; i++) {
 858       struct virgl_so_target *tg = virgl_so_target(targets[i]);
 859       virgl_encoder_write_dword(ctx->cbuf, tg->handle);
 860    }
 861    return 0;
 862 }
 863
 864
 865 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
 866 {
 867    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
 868    virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
 869    return 0;
 870 }
 871
 872 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
 873 {
 874    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
 875    virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
 876    return 0;
 877 }
 878
 879 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
 880 {
 881    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
 882    virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
 883    return 0;
 884 }
 885
 886 int virgl_encode_bind_shader(struct virgl_context *ctx,
 887                              uint32_t handle, uint32_t type)
 888 {
 889    virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
 890    virgl_encoder_write_dword(ctx->cbuf, handle);
 891    virgl_encoder_write_dword(ctx->cbuf, type);
 892    return 0;
 893 }