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virgl: add ARB_draw_indirect support.
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24 #include <assert.h>
25 #include <string.h>
26
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_math.h"
30 #include "pipe/p_state.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_parse.h"
33
34 #include "virgl_context.h"
35 #include "virgl_encode.h"
36 #include "virgl_protocol.h"
37 #include "virgl_resource.h"
38 #include "virgl_screen.h"
39
40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
41 uint32_t dword)
42 {
43 int len = (dword >> 16);
44
45 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
46 ctx->base.flush(&ctx->base, NULL, 0);
47
48 virgl_encoder_write_dword(ctx->cbuf, dword);
49 return 0;
50 }
51
52 static void virgl_encoder_write_res(struct virgl_context *ctx,
53 struct virgl_resource *res)
54 {
55 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
56
57 if (res && res->hw_res)
58 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
59 else {
60 virgl_encoder_write_dword(ctx->cbuf, 0);
61 }
62 }
63
64 int virgl_encode_bind_object(struct virgl_context *ctx,
65 uint32_t handle, uint32_t object)
66 {
67 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
68 virgl_encoder_write_dword(ctx->cbuf, handle);
69 return 0;
70 }
71
72 int virgl_encode_delete_object(struct virgl_context *ctx,
73 uint32_t handle, uint32_t object)
74 {
75 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
76 virgl_encoder_write_dword(ctx->cbuf, handle);
77 return 0;
78 }
79
80 int virgl_encode_blend_state(struct virgl_context *ctx,
81 uint32_t handle,
82 const struct pipe_blend_state *blend_state)
83 {
84 uint32_t tmp;
85 int i;
86
87 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
88 virgl_encoder_write_dword(ctx->cbuf, handle);
89
90 tmp =
91 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
92 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
93 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
94 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
95 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
96
97 virgl_encoder_write_dword(ctx->cbuf, tmp);
98
99 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
100 virgl_encoder_write_dword(ctx->cbuf, tmp);
101
102 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
103 tmp =
104 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
105 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
106 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
107 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
108 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
109 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
110 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
111 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
112 virgl_encoder_write_dword(ctx->cbuf, tmp);
113 }
114 return 0;
115 }
116
117 int virgl_encode_dsa_state(struct virgl_context *ctx,
118 uint32_t handle,
119 const struct pipe_depth_stencil_alpha_state *dsa_state)
120 {
121 uint32_t tmp;
122 int i;
123 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
124 virgl_encoder_write_dword(ctx->cbuf, handle);
125
126 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
128 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
129 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
130 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
131 virgl_encoder_write_dword(ctx->cbuf, tmp);
132
133 for (i = 0; i < 2; i++) {
134 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
135 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
136 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
137 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
138 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
139 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
141 virgl_encoder_write_dword(ctx->cbuf, tmp);
142 }
143
144 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
145 return 0;
146 }
147 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
148 uint32_t handle,
149 const struct pipe_rasterizer_state *state)
150 {
151 uint32_t tmp;
152
153 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
154 virgl_encoder_write_dword(ctx->cbuf, handle);
155
156 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
157 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
158 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
159 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
160 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
161 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
162 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
163 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
164 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
165 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
166 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
167 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
168 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
169 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
170 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
171 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
172 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
173 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
174 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
175 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
176 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
177 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
178 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
179 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
180 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
181 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
182 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
183 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule);
184
185 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
186 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
187 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
188 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
189 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
190 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
191 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
192 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
193 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
194 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
195 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
196 return 0;
197 }
198
199 static void virgl_emit_shader_header(struct virgl_context *ctx,
200 uint32_t handle, uint32_t len,
201 uint32_t type, uint32_t offlen,
202 uint32_t num_tokens)
203 {
204 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
205 virgl_encoder_write_dword(ctx->cbuf, handle);
206 virgl_encoder_write_dword(ctx->cbuf, type);
207 virgl_encoder_write_dword(ctx->cbuf, offlen);
208 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
209 }
210
211 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
212 const struct pipe_stream_output_info *so_info)
213 {
214 int num_outputs = 0;
215 int i;
216 uint32_t tmp;
217
218 if (so_info)
219 num_outputs = so_info->num_outputs;
220
221 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
222 if (num_outputs) {
223 for (i = 0; i < 4; i++)
224 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
225
226 for (i = 0; i < so_info->num_outputs; i++) {
227 tmp =
228 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
229 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
230 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
231 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
232 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
233 virgl_encoder_write_dword(ctx->cbuf, tmp);
234 virgl_encoder_write_dword(ctx->cbuf, 0);
235 }
236 }
237 }
238
239 int virgl_encode_shader_state(struct virgl_context *ctx,
240 uint32_t handle,
241 uint32_t type,
242 const struct pipe_stream_output_info *so_info,
243 const struct tgsi_token *tokens)
244 {
245 char *str, *sptr;
246 uint32_t shader_len, len;
247 bool bret;
248 int num_tokens = tgsi_num_tokens(tokens);
249 int str_total_size = 65536;
250 int retry_size = 1;
251 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
252 bool first_pass;
253 str = CALLOC(1, str_total_size);
254 if (!str)
255 return -1;
256
257 do {
258 int old_size;
259
260 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
261 if (bret == false) {
262 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
263 old_size = str_total_size;
264 str_total_size = 65536 * ++retry_size;
265 str = REALLOC(str, old_size, str_total_size);
266 if (!str)
267 return -1;
268 }
269 } while (bret == false && retry_size < 10);
270
271 if (bret == false)
272 return -1;
273
274 shader_len = strlen(str) + 1;
275
276 left_bytes = shader_len;
277
278 base_hdr_size = 5;
279 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
280 first_pass = true;
281 sptr = str;
282 while (left_bytes) {
283 uint32_t length, offlen;
284 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
285 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
286 ctx->base.flush(&ctx->base, NULL, 0);
287
288 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
289
290 length = MIN2(thispass, left_bytes);
291 len = ((length + 3) / 4) + hdr_len;
292
293 if (first_pass)
294 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
295 else
296 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
297
298 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
299
300 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
301
302 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
303
304 sptr += length;
305 first_pass = false;
306 left_bytes -= length;
307 }
308
309 FREE(str);
310 return 0;
311 }
312
313
314 int virgl_encode_clear(struct virgl_context *ctx,
315 unsigned buffers,
316 const union pipe_color_union *color,
317 double depth, unsigned stencil)
318 {
319 int i;
320 uint64_t qword;
321
322 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
323 memcpy(&qword, &depth, sizeof(qword));
324
325 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
326 virgl_encoder_write_dword(ctx->cbuf, buffers);
327 for (i = 0; i < 4; i++)
328 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
329 virgl_encoder_write_qword(ctx->cbuf, qword);
330 virgl_encoder_write_dword(ctx->cbuf, stencil);
331 return 0;
332 }
333
334 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
335 const struct pipe_framebuffer_state *state)
336 {
337 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
338 int i;
339
340 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
341 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
342 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
343 for (i = 0; i < state->nr_cbufs; i++) {
344 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
345 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
346 }
347
348 return 0;
349 }
350
351 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
352 int start_slot,
353 int num_viewports,
354 const struct pipe_viewport_state *states)
355 {
356 int i,v;
357 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
358 virgl_encoder_write_dword(ctx->cbuf, start_slot);
359 for (v = 0; v < num_viewports; v++) {
360 for (i = 0; i < 3; i++)
361 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
362 for (i = 0; i < 3; i++)
363 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
364 }
365 return 0;
366 }
367
368 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
369 uint32_t handle,
370 unsigned num_elements,
371 const struct pipe_vertex_element *element)
372 {
373 int i;
374 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
375 virgl_encoder_write_dword(ctx->cbuf, handle);
376 for (i = 0; i < num_elements; i++) {
377 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
378 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
379 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
380 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
381 }
382 return 0;
383 }
384
385 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
386 unsigned num_buffers,
387 const struct pipe_vertex_buffer *buffers)
388 {
389 int i;
390 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
391 for (i = 0; i < num_buffers; i++) {
392 struct virgl_resource *res = virgl_resource(buffers[i].buffer.resource);
393 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
394 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
395 virgl_encoder_write_res(ctx, res);
396 }
397 return 0;
398 }
399
400 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
401 const struct virgl_indexbuf *ib)
402 {
403 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
404 struct virgl_resource *res = NULL;
405 if (ib)
406 res = virgl_resource(ib->buffer);
407
408 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
409 virgl_encoder_write_res(ctx, res);
410 if (ib) {
411 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
412 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
413 }
414 return 0;
415 }
416
417 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
418 const struct pipe_draw_info *info)
419 {
420 uint32_t length = VIRGL_DRAW_VBO_SIZE;
421 if (info->indirect)
422 length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
423 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, length));
424 virgl_encoder_write_dword(ctx->cbuf, info->start);
425 virgl_encoder_write_dword(ctx->cbuf, info->count);
426 virgl_encoder_write_dword(ctx->cbuf, info->mode);
427 virgl_encoder_write_dword(ctx->cbuf, !!info->index_size);
428 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
429 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
430 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
431 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
432 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
433 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
434 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
435 if (info->count_from_stream_output)
436 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
437 else
438 virgl_encoder_write_dword(ctx->cbuf, 0);
439 if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
440 virgl_encoder_write_dword(ctx->cbuf, 0); /* vertices per patch */
441 virgl_encoder_write_dword(ctx->cbuf, 0); /* drawid */
442 virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
443 virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
444 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
445 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
446 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
447 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
448 }
449 return 0;
450 }
451
452 int virgl_encoder_create_surface(struct virgl_context *ctx,
453 uint32_t handle,
454 struct virgl_resource *res,
455 const struct pipe_surface *templat)
456 {
457 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
458 virgl_encoder_write_dword(ctx->cbuf, handle);
459 virgl_encoder_write_res(ctx, res);
460 virgl_encoder_write_dword(ctx->cbuf, templat->format);
461 if (templat->texture->target == PIPE_BUFFER) {
462 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
463 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
464
465 } else {
466 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
467 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
468 }
469 return 0;
470 }
471
472 int virgl_encoder_create_so_target(struct virgl_context *ctx,
473 uint32_t handle,
474 struct virgl_resource *res,
475 unsigned buffer_offset,
476 unsigned buffer_size)
477 {
478 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
479 virgl_encoder_write_dword(ctx->cbuf, handle);
480 virgl_encoder_write_res(ctx, res);
481 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
482 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
483 return 0;
484 }
485
486 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
487 struct virgl_resource *res,
488 unsigned level, unsigned usage,
489 const struct pipe_box *box,
490 unsigned stride, unsigned layer_stride)
491 {
492 virgl_encoder_write_res(ctx, res);
493 virgl_encoder_write_dword(ctx->cbuf, level);
494 virgl_encoder_write_dword(ctx->cbuf, usage);
495 virgl_encoder_write_dword(ctx->cbuf, stride);
496 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
497 virgl_encoder_write_dword(ctx->cbuf, box->x);
498 virgl_encoder_write_dword(ctx->cbuf, box->y);
499 virgl_encoder_write_dword(ctx->cbuf, box->z);
500 virgl_encoder_write_dword(ctx->cbuf, box->width);
501 virgl_encoder_write_dword(ctx->cbuf, box->height);
502 virgl_encoder_write_dword(ctx->cbuf, box->depth);
503 }
504
505 int virgl_encoder_inline_write(struct virgl_context *ctx,
506 struct virgl_resource *res,
507 unsigned level, unsigned usage,
508 const struct pipe_box *box,
509 const void *data, unsigned stride,
510 unsigned layer_stride)
511 {
512 uint32_t size = (stride ? stride : box->width) * box->height;
513 uint32_t length, thispass, left_bytes;
514 struct pipe_box mybox = *box;
515
516 length = 11 + (size + 3) / 4;
517 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
518 if (box->height > 1 || box->depth > 1) {
519 debug_printf("inline transfer failed due to multi dimensions and too large\n");
520 assert(0);
521 }
522 }
523
524 left_bytes = size;
525 while (left_bytes) {
526 if (ctx->cbuf->cdw + 12 > VIRGL_MAX_CMDBUF_DWORDS)
527 ctx->base.flush(&ctx->base, NULL, 0);
528
529 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
530
531 length = MIN2(thispass, left_bytes);
532
533 mybox.width = length;
534 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
535 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
536 virgl_encoder_write_block(ctx->cbuf, data, length);
537 left_bytes -= length;
538 mybox.x += length;
539 data += length;
540 }
541 return 0;
542 }
543
544 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
545 struct virgl_resource *res)
546 {
547 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
548 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
549 return 0;
550 }
551
552 int virgl_encode_sampler_state(struct virgl_context *ctx,
553 uint32_t handle,
554 const struct pipe_sampler_state *state)
555 {
556 uint32_t tmp;
557 int i;
558 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
559 virgl_encoder_write_dword(ctx->cbuf, handle);
560
561 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
562 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
563 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
564 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
565 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
566 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
567 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
568 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func);
569
570 virgl_encoder_write_dword(ctx->cbuf, tmp);
571 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
572 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
573 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
574 for (i = 0; i < 4; i++)
575 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
576 return 0;
577 }
578
579
580 int virgl_encode_sampler_view(struct virgl_context *ctx,
581 uint32_t handle,
582 struct virgl_resource *res,
583 const struct pipe_sampler_view *state)
584 {
585 unsigned elem_size = util_format_get_blocksize(state->format);
586
587 uint32_t tmp;
588 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
589 virgl_encoder_write_dword(ctx->cbuf, handle);
590 virgl_encoder_write_res(ctx, res);
591 virgl_encoder_write_dword(ctx->cbuf, state->format);
592 if (res->u.b.target == PIPE_BUFFER) {
593 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
594 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
595 } else {
596 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
597 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
598 }
599 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
600 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
601 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
602 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
603 virgl_encoder_write_dword(ctx->cbuf, tmp);
604 return 0;
605 }
606
607 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
608 uint32_t shader_type,
609 uint32_t start_slot,
610 uint32_t num_views,
611 struct virgl_sampler_view **views)
612 {
613 int i;
614 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
615 virgl_encoder_write_dword(ctx->cbuf, shader_type);
616 virgl_encoder_write_dword(ctx->cbuf, start_slot);
617 for (i = 0; i < num_views; i++) {
618 uint32_t handle = views[i] ? views[i]->handle : 0;
619 virgl_encoder_write_dword(ctx->cbuf, handle);
620 }
621 return 0;
622 }
623
624 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
625 uint32_t shader_type,
626 uint32_t start_slot,
627 uint32_t num_handles,
628 uint32_t *handles)
629 {
630 int i;
631 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
632 virgl_encoder_write_dword(ctx->cbuf, shader_type);
633 virgl_encoder_write_dword(ctx->cbuf, start_slot);
634 for (i = 0; i < num_handles; i++)
635 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
636 return 0;
637 }
638
639 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
640 uint32_t shader,
641 uint32_t index,
642 uint32_t size,
643 const void *data)
644 {
645 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
646 virgl_encoder_write_dword(ctx->cbuf, shader);
647 virgl_encoder_write_dword(ctx->cbuf, index);
648 if (data)
649 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
650 return 0;
651 }
652
653 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
654 uint32_t shader,
655 uint32_t index,
656 uint32_t offset,
657 uint32_t length,
658 struct virgl_resource *res)
659 {
660 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
661 virgl_encoder_write_dword(ctx->cbuf, shader);
662 virgl_encoder_write_dword(ctx->cbuf, index);
663 virgl_encoder_write_dword(ctx->cbuf, offset);
664 virgl_encoder_write_dword(ctx->cbuf, length);
665 virgl_encoder_write_res(ctx, res);
666 return 0;
667 }
668
669
670 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
671 const struct pipe_stencil_ref *ref)
672 {
673 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
674 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
675 return 0;
676 }
677
678 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
679 const struct pipe_blend_color *color)
680 {
681 int i;
682 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
683 for (i = 0; i < 4; i++)
684 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
685 return 0;
686 }
687
688 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
689 unsigned start_slot,
690 int num_scissors,
691 const struct pipe_scissor_state *ss)
692 {
693 int i;
694 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
695 virgl_encoder_write_dword(ctx->cbuf, start_slot);
696 for (i = 0; i < num_scissors; i++) {
697 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
698 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
699 }
700 return 0;
701 }
702
703 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
704 const struct pipe_poly_stipple *ps)
705 {
706 int i;
707 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
708 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
709 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
710 }
711 }
712
713 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
714 unsigned sample_mask)
715 {
716 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
717 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
718 }
719
720 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
721 const struct pipe_clip_state *clip)
722 {
723 int i, j;
724 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
725 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
726 for (j = 0; j < 4; j++) {
727 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
728 }
729 }
730 }
731
732 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
733 struct virgl_resource *dst_res,
734 unsigned dst_level,
735 unsigned dstx, unsigned dsty, unsigned dstz,
736 struct virgl_resource *src_res,
737 unsigned src_level,
738 const struct pipe_box *src_box)
739 {
740 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
741 virgl_encoder_write_res(ctx, dst_res);
742 virgl_encoder_write_dword(ctx->cbuf, dst_level);
743 virgl_encoder_write_dword(ctx->cbuf, dstx);
744 virgl_encoder_write_dword(ctx->cbuf, dsty);
745 virgl_encoder_write_dword(ctx->cbuf, dstz);
746 virgl_encoder_write_res(ctx, src_res);
747 virgl_encoder_write_dword(ctx->cbuf, src_level);
748 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
749 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
750 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
751 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
752 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
753 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
754 return 0;
755 }
756
757 int virgl_encode_blit(struct virgl_context *ctx,
758 struct virgl_resource *dst_res,
759 struct virgl_resource *src_res,
760 const struct pipe_blit_info *blit)
761 {
762 uint32_t tmp;
763 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
764 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
765 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
766 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) |
767 VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) |
768 VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend);
769 virgl_encoder_write_dword(ctx->cbuf, tmp);
770 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
771 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
772
773 virgl_encoder_write_res(ctx, dst_res);
774 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
775 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
776 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
777 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
778 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
779 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
780 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
781 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
782
783 virgl_encoder_write_res(ctx, src_res);
784 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
785 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
786 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
787 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
788 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
789 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
790 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
791 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
792 return 0;
793 }
794
795 int virgl_encoder_create_query(struct virgl_context *ctx,
796 uint32_t handle,
797 uint query_type,
798 uint query_index,
799 struct virgl_resource *res,
800 uint32_t offset)
801 {
802 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
803 virgl_encoder_write_dword(ctx->cbuf, handle);
804 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
805 virgl_encoder_write_dword(ctx->cbuf, offset);
806 virgl_encoder_write_res(ctx, res);
807 return 0;
808 }
809
810 int virgl_encoder_begin_query(struct virgl_context *ctx,
811 uint32_t handle)
812 {
813 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
814 virgl_encoder_write_dword(ctx->cbuf, handle);
815 return 0;
816 }
817
818 int virgl_encoder_end_query(struct virgl_context *ctx,
819 uint32_t handle)
820 {
821 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
822 virgl_encoder_write_dword(ctx->cbuf, handle);
823 return 0;
824 }
825
826 int virgl_encoder_get_query_result(struct virgl_context *ctx,
827 uint32_t handle, boolean wait)
828 {
829 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
830 virgl_encoder_write_dword(ctx->cbuf, handle);
831 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
832 return 0;
833 }
834
835 int virgl_encoder_render_condition(struct virgl_context *ctx,
836 uint32_t handle, boolean condition,
837 enum pipe_render_cond_flag mode)
838 {
839 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
840 virgl_encoder_write_dword(ctx->cbuf, handle);
841 virgl_encoder_write_dword(ctx->cbuf, condition);
842 virgl_encoder_write_dword(ctx->cbuf, mode);
843 return 0;
844 }
845
846 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
847 unsigned num_targets,
848 struct pipe_stream_output_target **targets,
849 unsigned append_bitmask)
850 {
851 int i;
852
853 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
854 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
855 for (i = 0; i < num_targets; i++) {
856 struct virgl_so_target *tg = virgl_so_target(targets[i]);
857 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
858 }
859 return 0;
860 }
861
862
863 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
864 {
865 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
866 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
867 return 0;
868 }
869
870 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
871 {
872 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
873 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
874 return 0;
875 }
876
877 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
878 {
879 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
880 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
881 return 0;
882 }
883
884 int virgl_encode_bind_shader(struct virgl_context *ctx,
885 uint32_t handle, uint32_t type)
886 {
887 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
888 virgl_encoder_write_dword(ctx->cbuf, handle);
889 virgl_encoder_write_dword(ctx->cbuf, type);
890 return 0;
891 }