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virgl: add initial ARB_compute_shader support
[mesa.git] / src / gallium / drivers / virgl / virgl_encode.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdint.h>
24 #include <assert.h>
25 #include <string.h>
26
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_math.h"
30 #include "pipe/p_state.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_parse.h"
33
34 #include "virgl_context.h"
35 #include "virgl_encode.h"
36 #include "virgl_protocol.h"
37 #include "virgl_resource.h"
38 #include "virgl_screen.h"
39
40 static int virgl_encoder_write_cmd_dword(struct virgl_context *ctx,
41 uint32_t dword)
42 {
43 int len = (dword >> 16);
44
45 if ((ctx->cbuf->cdw + len + 1) > VIRGL_MAX_CMDBUF_DWORDS)
46 ctx->base.flush(&ctx->base, NULL, 0);
47
48 virgl_encoder_write_dword(ctx->cbuf, dword);
49 return 0;
50 }
51
52 static void virgl_encoder_write_res(struct virgl_context *ctx,
53 struct virgl_resource *res)
54 {
55 struct virgl_winsys *vws = virgl_screen(ctx->base.screen)->vws;
56
57 if (res && res->hw_res)
58 vws->emit_res(vws, ctx->cbuf, res->hw_res, TRUE);
59 else {
60 virgl_encoder_write_dword(ctx->cbuf, 0);
61 }
62 }
63
64 int virgl_encode_bind_object(struct virgl_context *ctx,
65 uint32_t handle, uint32_t object)
66 {
67 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_OBJECT, object, 1));
68 virgl_encoder_write_dword(ctx->cbuf, handle);
69 return 0;
70 }
71
72 int virgl_encode_delete_object(struct virgl_context *ctx,
73 uint32_t handle, uint32_t object)
74 {
75 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_OBJECT, object, 1));
76 virgl_encoder_write_dword(ctx->cbuf, handle);
77 return 0;
78 }
79
80 int virgl_encode_blend_state(struct virgl_context *ctx,
81 uint32_t handle,
82 const struct pipe_blend_state *blend_state)
83 {
84 uint32_t tmp;
85 int i;
86
87 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_BLEND, VIRGL_OBJ_BLEND_SIZE));
88 virgl_encoder_write_dword(ctx->cbuf, handle);
89
90 tmp =
91 VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(blend_state->independent_blend_enable) |
92 VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(blend_state->logicop_enable) |
93 VIRGL_OBJ_BLEND_S0_DITHER(blend_state->dither) |
94 VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(blend_state->alpha_to_coverage) |
95 VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(blend_state->alpha_to_one);
96
97 virgl_encoder_write_dword(ctx->cbuf, tmp);
98
99 tmp = VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(blend_state->logicop_func);
100 virgl_encoder_write_dword(ctx->cbuf, tmp);
101
102 for (i = 0; i < VIRGL_MAX_COLOR_BUFS; i++) {
103 tmp =
104 VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(blend_state->rt[i].blend_enable) |
105 VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(blend_state->rt[i].rgb_func) |
106 VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(blend_state->rt[i].rgb_src_factor) |
107 VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(blend_state->rt[i].rgb_dst_factor)|
108 VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(blend_state->rt[i].alpha_func) |
109 VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(blend_state->rt[i].alpha_src_factor) |
110 VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(blend_state->rt[i].alpha_dst_factor) |
111 VIRGL_OBJ_BLEND_S2_RT_COLORMASK(blend_state->rt[i].colormask);
112 virgl_encoder_write_dword(ctx->cbuf, tmp);
113 }
114 return 0;
115 }
116
117 int virgl_encode_dsa_state(struct virgl_context *ctx,
118 uint32_t handle,
119 const struct pipe_depth_stencil_alpha_state *dsa_state)
120 {
121 uint32_t tmp;
122 int i;
123 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
124 virgl_encoder_write_dword(ctx->cbuf, handle);
125
126 tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
128 VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
129 VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha.enabled) |
130 VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha.func);
131 virgl_encoder_write_dword(ctx->cbuf, tmp);
132
133 for (i = 0; i < 2; i++) {
134 tmp = VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(dsa_state->stencil[i].enabled) |
135 VIRGL_OBJ_DSA_S1_STENCIL_FUNC(dsa_state->stencil[i].func) |
136 VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(dsa_state->stencil[i].fail_op) |
137 VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(dsa_state->stencil[i].zpass_op) |
138 VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(dsa_state->stencil[i].zfail_op) |
139 VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(dsa_state->stencil[i].valuemask) |
140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
141 virgl_encoder_write_dword(ctx->cbuf, tmp);
142 }
143
144 virgl_encoder_write_dword(ctx->cbuf, fui(dsa_state->alpha.ref_value));
145 return 0;
146 }
147 int virgl_encode_rasterizer_state(struct virgl_context *ctx,
148 uint32_t handle,
149 const struct pipe_rasterizer_state *state)
150 {
151 uint32_t tmp;
152
153 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_RASTERIZER, VIRGL_OBJ_RS_SIZE));
154 virgl_encoder_write_dword(ctx->cbuf, handle);
155
156 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
157 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip) |
158 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
159 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
160 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
161 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
162 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
163 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
164 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
165 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
166 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
167 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
168 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
169 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
170 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
171 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
172 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
173 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
174 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
175 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
176 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
177 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
178 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
179 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
180 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
181 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
182 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
183 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
184 VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
185
186 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
187 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
188 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
189 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
190 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
191 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
192 virgl_encoder_write_dword(ctx->cbuf, tmp); /* S3 */
193 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
194 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
195 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
196 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
197 return 0;
198 }
199
200 static void virgl_emit_shader_header(struct virgl_context *ctx,
201 uint32_t handle, uint32_t len,
202 uint32_t type, uint32_t offlen,
203 uint32_t num_tokens)
204 {
205 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SHADER, len));
206 virgl_encoder_write_dword(ctx->cbuf, handle);
207 virgl_encoder_write_dword(ctx->cbuf, type);
208 virgl_encoder_write_dword(ctx->cbuf, offlen);
209 virgl_encoder_write_dword(ctx->cbuf, num_tokens);
210 }
211
212 static void virgl_emit_shader_streamout(struct virgl_context *ctx,
213 const struct pipe_stream_output_info *so_info)
214 {
215 int num_outputs = 0;
216 int i;
217 uint32_t tmp;
218
219 if (so_info)
220 num_outputs = so_info->num_outputs;
221
222 virgl_encoder_write_dword(ctx->cbuf, num_outputs);
223 if (num_outputs) {
224 for (i = 0; i < 4; i++)
225 virgl_encoder_write_dword(ctx->cbuf, so_info->stride[i]);
226
227 for (i = 0; i < so_info->num_outputs; i++) {
228 tmp =
229 VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(so_info->output[i].register_index) |
230 VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(so_info->output[i].start_component) |
231 VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(so_info->output[i].num_components) |
232 VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) |
233 VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
234 virgl_encoder_write_dword(ctx->cbuf, tmp);
235 virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream);
236 }
237 }
238 }
239
240 int virgl_encode_shader_state(struct virgl_context *ctx,
241 uint32_t handle,
242 uint32_t type,
243 const struct pipe_stream_output_info *so_info,
244 uint32_t cs_req_local_mem,
245 const struct tgsi_token *tokens)
246 {
247 char *str, *sptr;
248 uint32_t shader_len, len;
249 bool bret;
250 int num_tokens = tgsi_num_tokens(tokens);
251 int str_total_size = 65536;
252 int retry_size = 1;
253 uint32_t left_bytes, base_hdr_size, strm_hdr_size, thispass;
254 bool first_pass;
255 str = CALLOC(1, str_total_size);
256 if (!str)
257 return -1;
258
259 do {
260 int old_size;
261
262 bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, str_total_size);
263 if (bret == false) {
264 fprintf(stderr, "Failed to translate shader in available space - trying again\n");
265 old_size = str_total_size;
266 str_total_size = 65536 * ++retry_size;
267 str = REALLOC(str, old_size, str_total_size);
268 if (!str)
269 return -1;
270 }
271 } while (bret == false && retry_size < 10);
272
273 if (bret == false)
274 return -1;
275
276 shader_len = strlen(str) + 1;
277
278 left_bytes = shader_len;
279
280 base_hdr_size = 5;
281 strm_hdr_size = so_info->num_outputs ? so_info->num_outputs * 2 + 4 : 0;
282 first_pass = true;
283 sptr = str;
284 while (left_bytes) {
285 uint32_t length, offlen;
286 int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
287 if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
288 ctx->base.flush(&ctx->base, NULL, 0);
289
290 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
291
292 length = MIN2(thispass, left_bytes);
293 len = ((length + 3) / 4) + hdr_len;
294
295 if (first_pass)
296 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL(shader_len);
297 else
298 offlen = VIRGL_OBJ_SHADER_OFFSET_VAL((uintptr_t)sptr - (uintptr_t)str) | VIRGL_OBJ_SHADER_OFFSET_CONT;
299
300 virgl_emit_shader_header(ctx, handle, len, type, offlen, num_tokens);
301
302 if (type == PIPE_SHADER_COMPUTE)
303 virgl_encoder_write_dword(ctx->cbuf, cs_req_local_mem);
304 else
305 virgl_emit_shader_streamout(ctx, first_pass ? so_info : NULL);
306
307 virgl_encoder_write_block(ctx->cbuf, (uint8_t *)sptr, length);
308
309 sptr += length;
310 first_pass = false;
311 left_bytes -= length;
312 }
313
314 FREE(str);
315 return 0;
316 }
317
318
319 int virgl_encode_clear(struct virgl_context *ctx,
320 unsigned buffers,
321 const union pipe_color_union *color,
322 double depth, unsigned stencil)
323 {
324 int i;
325 uint64_t qword;
326
327 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
328 memcpy(&qword, &depth, sizeof(qword));
329
330 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE));
331 virgl_encoder_write_dword(ctx->cbuf, buffers);
332 for (i = 0; i < 4; i++)
333 virgl_encoder_write_dword(ctx->cbuf, color->ui[i]);
334 virgl_encoder_write_qword(ctx->cbuf, qword);
335 virgl_encoder_write_dword(ctx->cbuf, stencil);
336 return 0;
337 }
338
339 int virgl_encoder_set_framebuffer_state(struct virgl_context *ctx,
340 const struct pipe_framebuffer_state *state)
341 {
342 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
343 int i;
344
345 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
346 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
347 virgl_encoder_write_dword(ctx->cbuf, zsurf ? zsurf->handle : 0);
348 for (i = 0; i < state->nr_cbufs; i++) {
349 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
350 virgl_encoder_write_dword(ctx->cbuf, surf ? surf->handle : 0);
351 }
352
353 return 0;
354 }
355
356 int virgl_encoder_set_viewport_states(struct virgl_context *ctx,
357 int start_slot,
358 int num_viewports,
359 const struct pipe_viewport_state *states)
360 {
361 int i,v;
362 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VIEWPORT_STATE, 0, VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports)));
363 virgl_encoder_write_dword(ctx->cbuf, start_slot);
364 for (v = 0; v < num_viewports; v++) {
365 for (i = 0; i < 3; i++)
366 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].scale[i]));
367 for (i = 0; i < 3; i++)
368 virgl_encoder_write_dword(ctx->cbuf, fui(states[v].translate[i]));
369 }
370 return 0;
371 }
372
373 int virgl_encoder_create_vertex_elements(struct virgl_context *ctx,
374 uint32_t handle,
375 unsigned num_elements,
376 const struct pipe_vertex_element *element)
377 {
378 int i;
379 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_VERTEX_ELEMENTS, VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements)));
380 virgl_encoder_write_dword(ctx->cbuf, handle);
381 for (i = 0; i < num_elements; i++) {
382 virgl_encoder_write_dword(ctx->cbuf, element[i].src_offset);
383 virgl_encoder_write_dword(ctx->cbuf, element[i].instance_divisor);
384 virgl_encoder_write_dword(ctx->cbuf, element[i].vertex_buffer_index);
385 virgl_encoder_write_dword(ctx->cbuf, element[i].src_format);
386 }
387 return 0;
388 }
389
390 int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx,
391 unsigned num_buffers,
392 const struct pipe_vertex_buffer *buffers)
393 {
394 int i;
395 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers)));
396 for (i = 0; i < num_buffers; i++) {
397 struct virgl_resource *res = virgl_resource(buffers[i].buffer.resource);
398 virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride);
399 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
400 virgl_encoder_write_res(ctx, res);
401 }
402 return 0;
403 }
404
405 int virgl_encoder_set_index_buffer(struct virgl_context *ctx,
406 const struct virgl_indexbuf *ib)
407 {
408 int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib);
409 struct virgl_resource *res = NULL;
410 if (ib)
411 res = virgl_resource(ib->buffer);
412
413 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length));
414 virgl_encoder_write_res(ctx, res);
415 if (ib) {
416 virgl_encoder_write_dword(ctx->cbuf, ib->index_size);
417 virgl_encoder_write_dword(ctx->cbuf, ib->offset);
418 }
419 return 0;
420 }
421
422 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
423 const struct pipe_draw_info *info)
424 {
425 uint32_t length = VIRGL_DRAW_VBO_SIZE;
426 if (info->mode == PIPE_PRIM_PATCHES)
427 length = VIRGL_DRAW_VBO_SIZE_TESS;
428 if (info->indirect)
429 length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
430 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, length));
431 virgl_encoder_write_dword(ctx->cbuf, info->start);
432 virgl_encoder_write_dword(ctx->cbuf, info->count);
433 virgl_encoder_write_dword(ctx->cbuf, info->mode);
434 virgl_encoder_write_dword(ctx->cbuf, !!info->index_size);
435 virgl_encoder_write_dword(ctx->cbuf, info->instance_count);
436 virgl_encoder_write_dword(ctx->cbuf, info->index_bias);
437 virgl_encoder_write_dword(ctx->cbuf, info->start_instance);
438 virgl_encoder_write_dword(ctx->cbuf, info->primitive_restart);
439 virgl_encoder_write_dword(ctx->cbuf, info->restart_index);
440 virgl_encoder_write_dword(ctx->cbuf, info->min_index);
441 virgl_encoder_write_dword(ctx->cbuf, info->max_index);
442 if (info->count_from_stream_output)
443 virgl_encoder_write_dword(ctx->cbuf, info->count_from_stream_output->buffer_size);
444 else
445 virgl_encoder_write_dword(ctx->cbuf, 0);
446 if (length >= VIRGL_DRAW_VBO_SIZE_TESS) {
447 virgl_encoder_write_dword(ctx->cbuf, info->vertices_per_patch); /* vertices per patch */
448 virgl_encoder_write_dword(ctx->cbuf, info->drawid); /* drawid */
449 }
450 if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
451 virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
452 virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
453 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
454 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
455 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
456 virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
457 }
458 return 0;
459 }
460
461 int virgl_encoder_create_surface(struct virgl_context *ctx,
462 uint32_t handle,
463 struct virgl_resource *res,
464 const struct pipe_surface *templat)
465 {
466 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SURFACE, VIRGL_OBJ_SURFACE_SIZE));
467 virgl_encoder_write_dword(ctx->cbuf, handle);
468 virgl_encoder_write_res(ctx, res);
469 virgl_encoder_write_dword(ctx->cbuf, templat->format);
470 if (templat->texture->target == PIPE_BUFFER) {
471 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.first_element);
472 virgl_encoder_write_dword(ctx->cbuf, templat->u.buf.last_element);
473
474 } else {
475 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.level);
476 virgl_encoder_write_dword(ctx->cbuf, templat->u.tex.first_layer | (templat->u.tex.last_layer << 16));
477 }
478 return 0;
479 }
480
481 int virgl_encoder_create_so_target(struct virgl_context *ctx,
482 uint32_t handle,
483 struct virgl_resource *res,
484 unsigned buffer_offset,
485 unsigned buffer_size)
486 {
487 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_STREAMOUT_TARGET, VIRGL_OBJ_STREAMOUT_SIZE));
488 virgl_encoder_write_dword(ctx->cbuf, handle);
489 virgl_encoder_write_res(ctx, res);
490 virgl_encoder_write_dword(ctx->cbuf, buffer_offset);
491 virgl_encoder_write_dword(ctx->cbuf, buffer_size);
492 return 0;
493 }
494
495 static void virgl_encoder_iw_emit_header_1d(struct virgl_context *ctx,
496 struct virgl_resource *res,
497 unsigned level, unsigned usage,
498 const struct pipe_box *box,
499 unsigned stride, unsigned layer_stride)
500 {
501 virgl_encoder_write_res(ctx, res);
502 virgl_encoder_write_dword(ctx->cbuf, level);
503 virgl_encoder_write_dword(ctx->cbuf, usage);
504 virgl_encoder_write_dword(ctx->cbuf, stride);
505 virgl_encoder_write_dword(ctx->cbuf, layer_stride);
506 virgl_encoder_write_dword(ctx->cbuf, box->x);
507 virgl_encoder_write_dword(ctx->cbuf, box->y);
508 virgl_encoder_write_dword(ctx->cbuf, box->z);
509 virgl_encoder_write_dword(ctx->cbuf, box->width);
510 virgl_encoder_write_dword(ctx->cbuf, box->height);
511 virgl_encoder_write_dword(ctx->cbuf, box->depth);
512 }
513
514 int virgl_encoder_inline_write(struct virgl_context *ctx,
515 struct virgl_resource *res,
516 unsigned level, unsigned usage,
517 const struct pipe_box *box,
518 const void *data, unsigned stride,
519 unsigned layer_stride)
520 {
521 uint32_t size = (stride ? stride : box->width) * box->height;
522 uint32_t length, thispass, left_bytes;
523 struct pipe_box mybox = *box;
524
525 length = 11 + (size + 3) / 4;
526 if ((ctx->cbuf->cdw + length + 1) > VIRGL_MAX_CMDBUF_DWORDS) {
527 if (box->height > 1 || box->depth > 1) {
528 debug_printf("inline transfer failed due to multi dimensions and too large\n");
529 assert(0);
530 }
531 }
532
533 left_bytes = size;
534 while (left_bytes) {
535 if (ctx->cbuf->cdw + 12 >= VIRGL_MAX_CMDBUF_DWORDS)
536 ctx->base.flush(&ctx->base, NULL, 0);
537
538 thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - 12) * 4;
539
540 length = MIN2(thispass, left_bytes);
541
542 mybox.width = length;
543 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_INLINE_WRITE, 0, ((length + 3) / 4) + 11));
544 virgl_encoder_iw_emit_header_1d(ctx, res, level, usage, &mybox, stride, layer_stride);
545 virgl_encoder_write_block(ctx->cbuf, data, length);
546 left_bytes -= length;
547 mybox.x += length;
548 data += length;
549 }
550 return 0;
551 }
552
553 int virgl_encoder_flush_frontbuffer(struct virgl_context *ctx,
554 struct virgl_resource *res)
555 {
556 // virgl_encoder_write_dword(ctx->cbuf, VIRGL_CMD0(VIRGL_CCMD_FLUSH_FRONTUBFFER, 0, 1));
557 // virgl_encoder_write_dword(ctx->cbuf, res_handle);
558 return 0;
559 }
560
561 int virgl_encode_sampler_state(struct virgl_context *ctx,
562 uint32_t handle,
563 const struct pipe_sampler_state *state)
564 {
565 uint32_t tmp;
566 int i;
567 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_STATE, VIRGL_OBJ_SAMPLER_STATE_SIZE));
568 virgl_encoder_write_dword(ctx->cbuf, handle);
569
570 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
571 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
572 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
573 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
574 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
575 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
576 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
577 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
578 VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map);
579
580 virgl_encoder_write_dword(ctx->cbuf, tmp);
581 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
582 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
583 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
584 for (i = 0; i < 4; i++)
585 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
586 return 0;
587 }
588
589
590 int virgl_encode_sampler_view(struct virgl_context *ctx,
591 uint32_t handle,
592 struct virgl_resource *res,
593 const struct pipe_sampler_view *state)
594 {
595 unsigned elem_size = util_format_get_blocksize(state->format);
596 struct virgl_screen *rs = virgl_screen(ctx->base.screen);
597 uint32_t tmp;
598 uint32_t dword_fmt_target = state->format;
599 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
600 virgl_encoder_write_dword(ctx->cbuf, handle);
601 virgl_encoder_write_res(ctx, res);
602 if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
603 dword_fmt_target |= (state->target << 24);
604 virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
605 if (res->u.b.target == PIPE_BUFFER) {
606 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
607 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
608 } else {
609 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
610 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
611 }
612 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
613 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
614 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
615 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);
616 virgl_encoder_write_dword(ctx->cbuf, tmp);
617 return 0;
618 }
619
620 int virgl_encode_set_sampler_views(struct virgl_context *ctx,
621 uint32_t shader_type,
622 uint32_t start_slot,
623 uint32_t num_views,
624 struct virgl_sampler_view **views)
625 {
626 int i;
627 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLER_VIEWS, 0, VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views)));
628 virgl_encoder_write_dword(ctx->cbuf, shader_type);
629 virgl_encoder_write_dword(ctx->cbuf, start_slot);
630 for (i = 0; i < num_views; i++) {
631 uint32_t handle = views[i] ? views[i]->handle : 0;
632 virgl_encoder_write_dword(ctx->cbuf, handle);
633 }
634 return 0;
635 }
636
637 int virgl_encode_bind_sampler_states(struct virgl_context *ctx,
638 uint32_t shader_type,
639 uint32_t start_slot,
640 uint32_t num_handles,
641 uint32_t *handles)
642 {
643 int i;
644 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SAMPLER_STATES, 0, VIRGL_BIND_SAMPLER_STATES(num_handles)));
645 virgl_encoder_write_dword(ctx->cbuf, shader_type);
646 virgl_encoder_write_dword(ctx->cbuf, start_slot);
647 for (i = 0; i < num_handles; i++)
648 virgl_encoder_write_dword(ctx->cbuf, handles[i]);
649 return 0;
650 }
651
652 int virgl_encoder_write_constant_buffer(struct virgl_context *ctx,
653 uint32_t shader,
654 uint32_t index,
655 uint32_t size,
656 const void *data)
657 {
658 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CONSTANT_BUFFER, 0, size + 2));
659 virgl_encoder_write_dword(ctx->cbuf, shader);
660 virgl_encoder_write_dword(ctx->cbuf, index);
661 if (data)
662 virgl_encoder_write_block(ctx->cbuf, data, size * 4);
663 return 0;
664 }
665
666 int virgl_encoder_set_uniform_buffer(struct virgl_context *ctx,
667 uint32_t shader,
668 uint32_t index,
669 uint32_t offset,
670 uint32_t length,
671 struct virgl_resource *res)
672 {
673 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_UNIFORM_BUFFER, 0, VIRGL_SET_UNIFORM_BUFFER_SIZE));
674 virgl_encoder_write_dword(ctx->cbuf, shader);
675 virgl_encoder_write_dword(ctx->cbuf, index);
676 virgl_encoder_write_dword(ctx->cbuf, offset);
677 virgl_encoder_write_dword(ctx->cbuf, length);
678 virgl_encoder_write_res(ctx, res);
679 return 0;
680 }
681
682
683 int virgl_encoder_set_stencil_ref(struct virgl_context *ctx,
684 const struct pipe_stencil_ref *ref)
685 {
686 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STENCIL_REF, 0, VIRGL_SET_STENCIL_REF_SIZE));
687 virgl_encoder_write_dword(ctx->cbuf, VIRGL_STENCIL_REF_VAL(ref->ref_value[0] , (ref->ref_value[1])));
688 return 0;
689 }
690
691 int virgl_encoder_set_blend_color(struct virgl_context *ctx,
692 const struct pipe_blend_color *color)
693 {
694 int i;
695 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_BLEND_COLOR, 0, VIRGL_SET_BLEND_COLOR_SIZE));
696 for (i = 0; i < 4; i++)
697 virgl_encoder_write_dword(ctx->cbuf, fui(color->color[i]));
698 return 0;
699 }
700
701 int virgl_encoder_set_scissor_state(struct virgl_context *ctx,
702 unsigned start_slot,
703 int num_scissors,
704 const struct pipe_scissor_state *ss)
705 {
706 int i;
707 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SCISSOR_STATE, 0, VIRGL_SET_SCISSOR_STATE_SIZE(num_scissors)));
708 virgl_encoder_write_dword(ctx->cbuf, start_slot);
709 for (i = 0; i < num_scissors; i++) {
710 virgl_encoder_write_dword(ctx->cbuf, (ss[i].minx | ss[i].miny << 16));
711 virgl_encoder_write_dword(ctx->cbuf, (ss[i].maxx | ss[i].maxy << 16));
712 }
713 return 0;
714 }
715
716 void virgl_encoder_set_polygon_stipple(struct virgl_context *ctx,
717 const struct pipe_poly_stipple *ps)
718 {
719 int i;
720 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_POLYGON_STIPPLE, 0, VIRGL_POLYGON_STIPPLE_SIZE));
721 for (i = 0; i < VIRGL_POLYGON_STIPPLE_SIZE; i++) {
722 virgl_encoder_write_dword(ctx->cbuf, ps->stipple[i]);
723 }
724 }
725
726 void virgl_encoder_set_sample_mask(struct virgl_context *ctx,
727 unsigned sample_mask)
728 {
729 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SAMPLE_MASK, 0, VIRGL_SET_SAMPLE_MASK_SIZE));
730 virgl_encoder_write_dword(ctx->cbuf, sample_mask);
731 }
732
733 void virgl_encoder_set_min_samples(struct virgl_context *ctx,
734 unsigned min_samples)
735 {
736 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_MIN_SAMPLES, 0, VIRGL_SET_MIN_SAMPLES_SIZE));
737 virgl_encoder_write_dword(ctx->cbuf, min_samples);
738 }
739
740 void virgl_encoder_set_clip_state(struct virgl_context *ctx,
741 const struct pipe_clip_state *clip)
742 {
743 int i, j;
744 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_CLIP_STATE, 0, VIRGL_SET_CLIP_STATE_SIZE));
745 for (i = 0; i < VIRGL_MAX_CLIP_PLANES; i++) {
746 for (j = 0; j < 4; j++) {
747 virgl_encoder_write_dword(ctx->cbuf, fui(clip->ucp[i][j]));
748 }
749 }
750 }
751
752 int virgl_encode_resource_copy_region(struct virgl_context *ctx,
753 struct virgl_resource *dst_res,
754 unsigned dst_level,
755 unsigned dstx, unsigned dsty, unsigned dstz,
756 struct virgl_resource *src_res,
757 unsigned src_level,
758 const struct pipe_box *src_box)
759 {
760 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_RESOURCE_COPY_REGION, 0, VIRGL_CMD_RESOURCE_COPY_REGION_SIZE));
761 virgl_encoder_write_res(ctx, dst_res);
762 virgl_encoder_write_dword(ctx->cbuf, dst_level);
763 virgl_encoder_write_dword(ctx->cbuf, dstx);
764 virgl_encoder_write_dword(ctx->cbuf, dsty);
765 virgl_encoder_write_dword(ctx->cbuf, dstz);
766 virgl_encoder_write_res(ctx, src_res);
767 virgl_encoder_write_dword(ctx->cbuf, src_level);
768 virgl_encoder_write_dword(ctx->cbuf, src_box->x);
769 virgl_encoder_write_dword(ctx->cbuf, src_box->y);
770 virgl_encoder_write_dword(ctx->cbuf, src_box->z);
771 virgl_encoder_write_dword(ctx->cbuf, src_box->width);
772 virgl_encoder_write_dword(ctx->cbuf, src_box->height);
773 virgl_encoder_write_dword(ctx->cbuf, src_box->depth);
774 return 0;
775 }
776
777 int virgl_encode_blit(struct virgl_context *ctx,
778 struct virgl_resource *dst_res,
779 struct virgl_resource *src_res,
780 const struct pipe_blit_info *blit)
781 {
782 uint32_t tmp;
783 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE));
784 tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) |
785 VIRGL_CMD_BLIT_S0_FILTER(blit->filter) |
786 VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) |
787 VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) |
788 VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend);
789 virgl_encoder_write_dword(ctx->cbuf, tmp);
790 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16));
791 virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16));
792
793 virgl_encoder_write_res(ctx, dst_res);
794 virgl_encoder_write_dword(ctx->cbuf, blit->dst.level);
795 virgl_encoder_write_dword(ctx->cbuf, blit->dst.format);
796 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.x);
797 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.y);
798 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.z);
799 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.width);
800 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.height);
801 virgl_encoder_write_dword(ctx->cbuf, blit->dst.box.depth);
802
803 virgl_encoder_write_res(ctx, src_res);
804 virgl_encoder_write_dword(ctx->cbuf, blit->src.level);
805 virgl_encoder_write_dword(ctx->cbuf, blit->src.format);
806 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.x);
807 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.y);
808 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.z);
809 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.width);
810 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.height);
811 virgl_encoder_write_dword(ctx->cbuf, blit->src.box.depth);
812 return 0;
813 }
814
815 int virgl_encoder_create_query(struct virgl_context *ctx,
816 uint32_t handle,
817 uint query_type,
818 uint query_index,
819 struct virgl_resource *res,
820 uint32_t offset)
821 {
822 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_QUERY, VIRGL_OBJ_QUERY_SIZE));
823 virgl_encoder_write_dword(ctx->cbuf, handle);
824 virgl_encoder_write_dword(ctx->cbuf, ((query_type & 0xffff) | (query_index << 16)));
825 virgl_encoder_write_dword(ctx->cbuf, offset);
826 virgl_encoder_write_res(ctx, res);
827 return 0;
828 }
829
830 int virgl_encoder_begin_query(struct virgl_context *ctx,
831 uint32_t handle)
832 {
833 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BEGIN_QUERY, 0, 1));
834 virgl_encoder_write_dword(ctx->cbuf, handle);
835 return 0;
836 }
837
838 int virgl_encoder_end_query(struct virgl_context *ctx,
839 uint32_t handle)
840 {
841 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_END_QUERY, 0, 1));
842 virgl_encoder_write_dword(ctx->cbuf, handle);
843 return 0;
844 }
845
846 int virgl_encoder_get_query_result(struct virgl_context *ctx,
847 uint32_t handle, boolean wait)
848 {
849 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_GET_QUERY_RESULT, 0, 2));
850 virgl_encoder_write_dword(ctx->cbuf, handle);
851 virgl_encoder_write_dword(ctx->cbuf, wait ? 1 : 0);
852 return 0;
853 }
854
855 int virgl_encoder_render_condition(struct virgl_context *ctx,
856 uint32_t handle, boolean condition,
857 enum pipe_render_cond_flag mode)
858 {
859 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_RENDER_CONDITION, 0, VIRGL_RENDER_CONDITION_SIZE));
860 virgl_encoder_write_dword(ctx->cbuf, handle);
861 virgl_encoder_write_dword(ctx->cbuf, condition);
862 virgl_encoder_write_dword(ctx->cbuf, mode);
863 return 0;
864 }
865
866 int virgl_encoder_set_so_targets(struct virgl_context *ctx,
867 unsigned num_targets,
868 struct pipe_stream_output_target **targets,
869 unsigned append_bitmask)
870 {
871 int i;
872
873 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_STREAMOUT_TARGETS, 0, num_targets + 1));
874 virgl_encoder_write_dword(ctx->cbuf, append_bitmask);
875 for (i = 0; i < num_targets; i++) {
876 struct virgl_so_target *tg = virgl_so_target(targets[i]);
877 virgl_encoder_write_dword(ctx->cbuf, tg->handle);
878 }
879 return 0;
880 }
881
882
883 int virgl_encoder_set_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
884 {
885 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SUB_CTX, 0, 1));
886 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
887 return 0;
888 }
889
890 int virgl_encoder_create_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
891 {
892 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_SUB_CTX, 0, 1));
893 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
894 return 0;
895 }
896
897 int virgl_encoder_destroy_sub_ctx(struct virgl_context *ctx, uint32_t sub_ctx_id)
898 {
899 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DESTROY_SUB_CTX, 0, 1));
900 virgl_encoder_write_dword(ctx->cbuf, sub_ctx_id);
901 return 0;
902 }
903
904 int virgl_encode_bind_shader(struct virgl_context *ctx,
905 uint32_t handle, uint32_t type)
906 {
907 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BIND_SHADER, 0, 2));
908 virgl_encoder_write_dword(ctx->cbuf, handle);
909 virgl_encoder_write_dword(ctx->cbuf, type);
910 return 0;
911 }
912
913 int virgl_encode_set_tess_state(struct virgl_context *ctx,
914 const float outer[4],
915 const float inner[2])
916 {
917 int i;
918 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_TESS_STATE, 0, 6));
919 for (i = 0; i < 4; i++)
920 virgl_encoder_write_dword(ctx->cbuf, fui(outer[i]));
921 for (i = 0; i < 2; i++)
922 virgl_encoder_write_dword(ctx->cbuf, fui(inner[i]));
923 return 0;
924 }
925
926 int virgl_encode_set_shader_buffers(struct virgl_context *ctx,
927 enum pipe_shader_type shader,
928 unsigned start_slot, unsigned count,
929 const struct pipe_shader_buffer *buffers)
930 {
931 int i;
932 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SHADER_BUFFERS, 0, VIRGL_SET_SHADER_BUFFER_SIZE(count)));
933
934 virgl_encoder_write_dword(ctx->cbuf, shader);
935 virgl_encoder_write_dword(ctx->cbuf, start_slot);
936 for (i = 0; i < count; i++) {
937 if (buffers) {
938 struct virgl_resource *res = virgl_resource(buffers[i].buffer);
939 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset);
940 virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_size);
941 virgl_encoder_write_res(ctx, res);
942 } else {
943 virgl_encoder_write_dword(ctx->cbuf, 0);
944 virgl_encoder_write_dword(ctx->cbuf, 0);
945 virgl_encoder_write_dword(ctx->cbuf, 0);
946 }
947 }
948 return 0;
949 }
950
951 int virgl_encode_set_shader_images(struct virgl_context *ctx,
952 enum pipe_shader_type shader,
953 unsigned start_slot, unsigned count,
954 const struct pipe_image_view *images)
955 {
956 int i;
957 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_SHADER_IMAGES, 0, VIRGL_SET_SHADER_IMAGE_SIZE(count)));
958
959 virgl_encoder_write_dword(ctx->cbuf, shader);
960 virgl_encoder_write_dword(ctx->cbuf, start_slot);
961 for (i = 0; i < count; i++) {
962 if (images) {
963 struct virgl_resource *res = virgl_resource(images[i].resource);
964 virgl_encoder_write_dword(ctx->cbuf, images[i].format);
965 virgl_encoder_write_dword(ctx->cbuf, images[i].access);
966 virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.offset);
967 virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.size);
968 virgl_encoder_write_res(ctx, res);
969 } else {
970 virgl_encoder_write_dword(ctx->cbuf, 0);
971 virgl_encoder_write_dword(ctx->cbuf, 0);
972 virgl_encoder_write_dword(ctx->cbuf, 0);
973 virgl_encoder_write_dword(ctx->cbuf, 0);
974 virgl_encoder_write_dword(ctx->cbuf, 0);
975 }
976 }
977 return 0;
978 }
979
980 int virgl_encode_memory_barrier(struct virgl_context *ctx,
981 unsigned flags)
982 {
983 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_MEMORY_BARRIER, 0, 1));
984 virgl_encoder_write_dword(ctx->cbuf, flags);
985 return 0;
986 }
987
988 int virgl_encode_launch_grid(struct virgl_context *ctx,
989 const struct pipe_grid_info *grid_info)
990 {
991 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_LAUNCH_GRID, 0, VIRGL_LAUNCH_GRID_SIZE));
992 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[0]);
993 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[1]);
994 virgl_encoder_write_dword(ctx->cbuf, grid_info->block[2]);
995 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[0]);
996 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[1]);
997 virgl_encoder_write_dword(ctx->cbuf, grid_info->grid[2]);
998 if (grid_info->indirect) {
999 struct virgl_resource *res = virgl_resource(grid_info->indirect);
1000 virgl_encoder_write_res(ctx, res);
1001 } else
1002 virgl_encoder_write_dword(ctx->cbuf, 0);
1003 virgl_encoder_write_dword(ctx->cbuf, grid_info->indirect_offset);
1004 return 0;
1005 }