2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "util/u_memory.h"
24 #include "util/format/u_format.h"
25 #include "util/format/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/os_time.h"
30 #include "util/xmlconfig.h"
31 #include "pipe/p_defines.h"
32 #include "pipe/p_screen.h"
34 #include "tgsi/tgsi_exec.h"
36 #include "virgl_screen.h"
37 #include "virgl_resource.h"
38 #include "virgl_public.h"
39 #include "virgl_context.h"
40 #include "virgl_protocol.h"
43 static const struct debug_named_value debug_options
[] = {
44 { "verbose", VIRGL_DEBUG_VERBOSE
, NULL
},
45 { "tgsi", VIRGL_DEBUG_TGSI
, NULL
},
46 { "emubgra", VIRGL_DEBUG_EMULATE_BGRA
, "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
47 { "bgraswz", VIRGL_DEBUG_BGRA_DEST_SWIZZLE
, "Enable tweak to swizzle emulated BGRA on GLES hosts" },
48 { "sync", VIRGL_DEBUG_SYNC
, "Sync after every flush" },
49 { "xfer", VIRGL_DEBUG_XFER
, "Do not optimize for transfers" },
52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug
, "VIRGL_DEBUG", debug_options
, 0)
55 virgl_get_vendor(struct pipe_screen
*screen
)
62 virgl_get_name(struct pipe_screen
*screen
)
68 virgl_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
70 struct virgl_screen
*vscreen
= virgl_screen(screen
);
72 case PIPE_CAP_NPOT_TEXTURES
:
74 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
75 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
76 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
78 case PIPE_CAP_ANISOTROPIC_FILTER
:
80 case PIPE_CAP_POINT_SPRITE
:
82 case PIPE_CAP_MAX_RENDER_TARGETS
:
83 return vscreen
->caps
.caps
.v1
.max_render_targets
;
84 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
85 return vscreen
->caps
.caps
.v1
.max_dual_source_render_targets
;
86 case PIPE_CAP_OCCLUSION_QUERY
:
87 return vscreen
->caps
.caps
.v1
.bset
.occlusion_query
;
88 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
90 return vscreen
->caps
.caps
.v1
.bset
.mirror_clamp
;
91 case PIPE_CAP_TEXTURE_SWIZZLE
:
93 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
94 if (vscreen
->caps
.caps
.v2
.max_texture_2d_size
)
95 return vscreen
->caps
.caps
.v2
.max_texture_2d_size
;
97 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
98 if (vscreen
->caps
.caps
.v2
.max_texture_3d_size
)
99 return 1 + util_logbase2(vscreen
->caps
.caps
.v2
.max_texture_3d_size
);
100 return 9; /* 256 x 256 x 256 */
101 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
102 if (vscreen
->caps
.caps
.v2
.max_texture_cube_size
)
103 return 1 + util_logbase2(vscreen
->caps
.caps
.v2
.max_texture_cube_size
);
104 return 13; /* 4K x 4K */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
107 case PIPE_CAP_INDEP_BLEND_ENABLE
:
108 return vscreen
->caps
.caps
.v1
.bset
.indep_blend_enable
;
109 case PIPE_CAP_INDEP_BLEND_FUNC
:
110 return vscreen
->caps
.caps
.v1
.bset
.indep_blend_func
;
111 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
112 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
113 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
115 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
116 return vscreen
->caps
.caps
.v1
.bset
.fragment_coord_conventions
;
117 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
118 if (vscreen
->caps
.caps
.v1
.bset
.depth_clip_disable
)
120 if (vscreen
->caps
.caps
.v2
.host_feature_check_version
>= 3)
123 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
124 return vscreen
->caps
.caps
.v1
.max_streamout_buffers
;
125 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
128 case PIPE_CAP_PRIMITIVE_RESTART
:
129 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
130 return vscreen
->caps
.caps
.v1
.bset
.primitive_restart
;
131 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
132 return vscreen
->caps
.caps
.v1
.bset
.shader_stencil_export
;
133 case PIPE_CAP_TGSI_INSTANCEID
:
134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
137 return vscreen
->caps
.caps
.v1
.bset
.seamless_cube_map
;
138 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
139 return vscreen
->caps
.caps
.v1
.bset
.seamless_cube_map_per_texture
;
140 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
141 return vscreen
->caps
.caps
.v1
.max_texture_array_layers
;
142 case PIPE_CAP_MIN_TEXEL_OFFSET
:
143 return vscreen
->caps
.caps
.v2
.min_texel_offset
;
144 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
145 return vscreen
->caps
.caps
.v2
.min_texture_gather_offset
;
146 case PIPE_CAP_MAX_TEXEL_OFFSET
:
147 return vscreen
->caps
.caps
.v2
.max_texel_offset
;
148 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
149 return vscreen
->caps
.caps
.v2
.max_texture_gather_offset
;
150 case PIPE_CAP_CONDITIONAL_RENDER
:
151 return vscreen
->caps
.caps
.v1
.bset
.conditional_render
;
152 case PIPE_CAP_TEXTURE_BARRIER
:
153 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
;
154 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
156 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
157 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
158 return vscreen
->caps
.caps
.v1
.bset
.color_clamping
;
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
160 return (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FBO_MIXED_COLOR_FORMATS
) ||
161 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 1);
162 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
163 return vscreen
->caps
.caps
.v1
.glsl_level
;
164 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
165 return MIN2(vscreen
->caps
.caps
.v1
.glsl_level
, 140);
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
167 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
169 case PIPE_CAP_COMPUTE
:
170 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
;
171 case PIPE_CAP_USER_VERTEX_BUFFERS
:
173 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
174 return vscreen
->caps
.caps
.v2
.uniform_buffer_offset_alignment
;
175 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
176 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
177 return vscreen
->caps
.caps
.v1
.bset
.streamout_pause_resume
;
178 case PIPE_CAP_START_INSTANCE
:
179 return vscreen
->caps
.caps
.v1
.bset
.start_instance
;
180 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
181 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
182 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
183 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
184 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
186 case PIPE_CAP_QUERY_TIMESTAMP
:
188 case PIPE_CAP_QUERY_TIME_ELAPSED
:
190 case PIPE_CAP_TGSI_TEXCOORD
:
192 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
193 return VIRGL_MAP_BUFFER_ALIGNMENT
;
194 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
195 return vscreen
->caps
.caps
.v1
.max_tbo_size
> 0;
196 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
197 return vscreen
->caps
.caps
.v2
.texture_buffer_offset_alignment
;
198 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
200 case PIPE_CAP_CUBE_MAP_ARRAY
:
201 return vscreen
->caps
.caps
.v1
.bset
.cube_map_array
;
202 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
203 return vscreen
->caps
.caps
.v1
.bset
.texture_multisample
;
204 case PIPE_CAP_MAX_VIEWPORTS
:
205 return vscreen
->caps
.caps
.v1
.max_viewports
;
206 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
207 return vscreen
->caps
.caps
.v1
.max_tbo_size
;
208 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
209 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
210 case PIPE_CAP_ENDIANNESS
:
212 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
213 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
215 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
217 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
218 return vscreen
->caps
.caps
.v2
.max_geom_output_vertices
;
219 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
220 return vscreen
->caps
.caps
.v2
.max_geom_total_output_components
;
221 case PIPE_CAP_TEXTURE_QUERY_LOD
:
222 return vscreen
->caps
.caps
.v1
.bset
.texture_query_lod
;
223 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
224 return vscreen
->caps
.caps
.v1
.max_texture_gather_components
;
225 case PIPE_CAP_DRAW_INDIRECT
:
226 return vscreen
->caps
.caps
.v1
.bset
.has_indirect_draw
;
227 case PIPE_CAP_SAMPLE_SHADING
:
228 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
229 return vscreen
->caps
.caps
.v1
.bset
.has_sample_shading
;
230 case PIPE_CAP_CULL_DISTANCE
:
231 return vscreen
->caps
.caps
.v1
.bset
.has_cull
;
232 case PIPE_CAP_MAX_VERTEX_STREAMS
:
233 return ((vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TRANSFORM_FEEDBACK3
) ||
234 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 2)) ? 4 : 1;
235 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
236 return vscreen
->caps
.caps
.v1
.bset
.conditional_render_inverted
;
237 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
238 return vscreen
->caps
.caps
.v1
.bset
.derivative_control
;
239 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
240 return vscreen
->caps
.caps
.v1
.bset
.polygon_offset_clamp
;
241 case PIPE_CAP_QUERY_SO_OVERFLOW
:
242 return vscreen
->caps
.caps
.v1
.bset
.transform_feedback_overflow_query
;
243 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
244 return vscreen
->caps
.caps
.v2
.shader_buffer_offset_alignment
;
245 case PIPE_CAP_DOUBLES
:
246 return vscreen
->caps
.caps
.v1
.bset
.has_fp64
||
247 (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FAKE_FP64
);
248 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
249 return vscreen
->caps
.caps
.v2
.max_shader_patch_varyings
;
250 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
251 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_VIEW
;
252 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
253 return vscreen
->caps
.caps
.v2
.max_vertex_attrib_stride
;
254 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
255 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COPY_IMAGE
;
256 case PIPE_CAP_TGSI_TXQS
:
257 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TXQS
;
258 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
259 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FB_NO_ATTACH
;
260 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
261 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_ROBUST_BUFFER_ACCESS
;
262 case PIPE_CAP_FBFETCH
:
263 return (vscreen
->caps
.caps
.v2
.capability_bits
&
264 VIRGL_CAP_TGSI_FBFETCH
) ? 1 : 0;
265 case PIPE_CAP_BLEND_EQUATION_ADVANCED
:
266 return vscreen
->caps
.caps
.v2
.capability_bits_v2
& VIRGL_CAP_V2_BLEND_EQUATION
;
267 case PIPE_CAP_TGSI_CLOCK
:
268 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SHADER_CLOCK
;
269 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
270 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TGSI_COMPONENTS
;
271 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
272 return vscreen
->caps
.caps
.v2
.max_combined_shader_buffers
;
273 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
274 return vscreen
->caps
.caps
.v2
.max_combined_atomic_counters
;
275 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
276 return vscreen
->caps
.caps
.v2
.max_combined_atomic_counter_buffers
;
277 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
278 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
279 return 1; /* TODO: need to introduce a hw-cap for this */
280 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
281 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_QBO
;
282 case PIPE_CAP_MAX_VARYINGS
:
283 if (vscreen
->caps
.caps
.v1
.glsl_level
< 150)
284 return vscreen
->caps
.caps
.v2
.max_vertex_attribs
;
286 case PIPE_CAP_FAKE_SW_MSAA
:
287 /* If the host supports only one sample (e.g., if it is using softpipe),
288 * fake multisampling to able to advertise higher GL versions. */
289 return (vscreen
->caps
.caps
.v1
.max_samples
== 1) ? 1 : 0;
290 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
291 return !!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MULTI_DRAW_INDIRECT
);
292 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
293 return !!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_PARAMS
);
294 case PIPE_CAP_PCI_GROUP
:
295 case PIPE_CAP_PCI_BUS
:
296 case PIPE_CAP_PCI_DEVICE
:
297 case PIPE_CAP_PCI_FUNCTION
:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
299 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
301 case PIPE_CAP_CLEAR_TEXTURE
:
302 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_CLEAR_TEXTURE
;
303 case PIPE_CAP_CLIP_HALFZ
:
304 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_CLIP_HALFZ
;
305 case PIPE_CAP_MAX_GS_INVOCATIONS
:
307 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
309 case PIPE_CAP_VENDOR_ID
:
311 case PIPE_CAP_DEVICE_ID
:
313 case PIPE_CAP_ACCELERATED
:
316 case PIPE_CAP_VIDEO_MEMORY
:
318 case PIPE_CAP_NATIVE_FENCE_FD
:
319 return vscreen
->vws
->supports_fences
;
320 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
:
321 return (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SRGB_WRITE_CONTROL
) ||
322 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 1);
323 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
:
324 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_INPUT_ADDR
;
326 return u_pipe_screen_get_param_defaults(screen
, param
);
331 virgl_get_shader_param(struct pipe_screen
*screen
,
332 enum pipe_shader_type shader
,
333 enum pipe_shader_cap param
)
335 struct virgl_screen
*vscreen
= virgl_screen(screen
);
337 if ((shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
) &&
338 !vscreen
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
341 if (shader
== PIPE_SHADER_COMPUTE
&&
342 !(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
))
347 case PIPE_SHADER_FRAGMENT
:
348 case PIPE_SHADER_VERTEX
:
349 case PIPE_SHADER_GEOMETRY
:
350 case PIPE_SHADER_TESS_CTRL
:
351 case PIPE_SHADER_TESS_EVAL
:
352 case PIPE_SHADER_COMPUTE
:
354 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
355 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
356 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
357 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
359 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
360 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
361 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
363 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
364 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
365 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_INPUT_ADDR
;
366 case PIPE_SHADER_CAP_MAX_INPUTS
:
367 if (vscreen
->caps
.caps
.v1
.glsl_level
< 150)
368 return vscreen
->caps
.caps
.v2
.max_vertex_attribs
;
369 return (shader
== PIPE_SHADER_VERTEX
||
370 shader
== PIPE_SHADER_GEOMETRY
) ? vscreen
->caps
.caps
.v2
.max_vertex_attribs
: 32;
371 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
372 if (shader
== PIPE_SHADER_FRAGMENT
)
373 return vscreen
->caps
.caps
.v1
.max_render_targets
;
374 return vscreen
->caps
.caps
.v2
.max_vertex_outputs
;
375 // case PIPE_SHADER_CAP_MAX_CONSTS:
377 case PIPE_SHADER_CAP_MAX_TEMPS
:
379 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
380 return vscreen
->caps
.caps
.v1
.max_uniform_blocks
;
381 // case PIPE_SHADER_CAP_MAX_ADDRS:
383 case PIPE_SHADER_CAP_SUBROUTINES
:
385 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
387 case PIPE_SHADER_CAP_INTEGERS
:
388 return vscreen
->caps
.caps
.v1
.glsl_level
>= 130;
389 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
391 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
392 return 4096 * sizeof(float[4]);
393 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
394 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
395 return vscreen
->caps
.caps
.v2
.max_shader_buffer_frag_compute
;
397 return vscreen
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
398 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
399 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
400 return vscreen
->caps
.caps
.v2
.max_shader_image_frag_compute
;
402 return vscreen
->caps
.caps
.v2
.max_shader_image_other_stages
;
403 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
404 return (1 << PIPE_SHADER_IR_TGSI
);
405 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
406 return vscreen
->caps
.caps
.v2
.max_atomic_counters
[shader
];
407 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
408 return vscreen
->caps
.caps
.v2
.max_atomic_counter_buffers
[shader
];
409 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
410 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
411 case PIPE_SHADER_CAP_INT64_ATOMICS
:
412 case PIPE_SHADER_CAP_FP16
:
413 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
414 case PIPE_SHADER_CAP_INT16
:
415 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
426 virgl_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
428 struct virgl_screen
*vscreen
= virgl_screen(screen
);
430 case PIPE_CAPF_MAX_LINE_WIDTH
:
431 return vscreen
->caps
.caps
.v2
.max_aliased_line_width
;
432 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
433 return vscreen
->caps
.caps
.v2
.max_smooth_line_width
;
434 case PIPE_CAPF_MAX_POINT_WIDTH
:
435 return vscreen
->caps
.caps
.v2
.max_aliased_point_size
;
436 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
437 return vscreen
->caps
.caps
.v2
.max_smooth_point_size
;
438 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
440 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
441 return vscreen
->caps
.caps
.v2
.max_texture_lod_bias
;
442 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
443 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
444 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
447 /* should only get here on unhandled cases */
448 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
453 virgl_get_compute_param(struct pipe_screen
*screen
,
454 enum pipe_shader_ir ir_type
,
455 enum pipe_compute_cap param
,
458 struct virgl_screen
*vscreen
= virgl_screen(screen
);
459 if (!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
))
462 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
464 uint64_t *grid_size
= ret
;
465 grid_size
[0] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[0];
466 grid_size
[1] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[1];
467 grid_size
[2] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[2];
469 return 3 * sizeof(uint64_t) ;
470 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
472 uint64_t *block_size
= ret
;
473 block_size
[0] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[0];
474 block_size
[1] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[1];
475 block_size
[2] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[2];
477 return 3 * sizeof(uint64_t);
478 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
480 uint64_t *max_threads_per_block
= ret
;
481 *max_threads_per_block
= vscreen
->caps
.caps
.v2
.max_compute_work_group_invocations
;
483 return sizeof(uint64_t);
484 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
486 uint64_t *max_local_size
= ret
;
487 /* Value reported by the closed source driver. */
488 *max_local_size
= vscreen
->caps
.caps
.v2
.max_compute_shared_memory_size
;
490 return sizeof(uint64_t);
498 has_format_bit(struct virgl_supported_format_mask
*mask
,
499 enum virgl_formats fmt
)
501 assert(fmt
< VIRGL_FORMAT_MAX
);
502 unsigned val
= (unsigned)fmt
;
503 unsigned idx
= val
/ 32;
504 unsigned bit
= val
% 32;
505 assert(idx
< ARRAY_SIZE(mask
->bitmask
));
506 return (mask
->bitmask
[idx
] & (1u << bit
)) != 0;
510 virgl_has_readback_format(struct pipe_screen
*screen
,
511 enum virgl_formats fmt
)
513 struct virgl_screen
*vscreen
= virgl_screen(screen
);
514 return has_format_bit(&vscreen
->caps
.caps
.v2
.supported_readback_formats
,
519 virgl_is_vertex_format_supported(struct pipe_screen
*screen
,
520 enum pipe_format format
)
522 struct virgl_screen
*vscreen
= virgl_screen(screen
);
523 const struct util_format_description
*format_desc
;
526 format_desc
= util_format_description(format
);
530 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
531 int vformat
= VIRGL_FORMAT_R11G11B10_FLOAT
;
532 int big
= vformat
/ 32;
533 int small
= vformat
% 32;
534 if (!(vscreen
->caps
.caps
.v1
.vertexbuffer
.bitmask
[big
] & (1 << small
)))
539 /* Find the first non-VOID channel. */
540 for (i
= 0; i
< 4; i
++) {
541 if (format_desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
549 if (format_desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
552 if (format_desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FIXED
)
558 virgl_format_check_bitmask(enum pipe_format format
,
559 uint32_t bitmask
[16],
560 bool may_emulate_bgra
)
562 enum virgl_formats vformat
= pipe_to_virgl_format(format
);
563 int big
= vformat
/ 32;
564 int small
= vformat
% 32;
565 if ((bitmask
[big
] & (1 << small
)))
568 /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
569 * emulate it by using a swizzled RGBx */
570 if (may_emulate_bgra
) {
571 if (format
== PIPE_FORMAT_B8G8R8A8_SRGB
)
572 format
= PIPE_FORMAT_R8G8B8A8_SRGB
;
573 else if (format
== PIPE_FORMAT_B8G8R8X8_SRGB
)
574 format
= PIPE_FORMAT_R8G8B8X8_SRGB
;
579 vformat
= pipe_to_virgl_format(format
);
581 small
= vformat
% 32;
582 if (bitmask
[big
] & (1 << small
))
589 * Query format support for creating a texture, drawing surface, etc.
590 * \param format the format to test
591 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
594 virgl_is_format_supported( struct pipe_screen
*screen
,
595 enum pipe_format format
,
596 enum pipe_texture_target target
,
597 unsigned sample_count
,
598 unsigned storage_sample_count
,
601 struct virgl_screen
*vscreen
= virgl_screen(screen
);
602 const struct util_format_description
*format_desc
;
605 union virgl_caps
*caps
= &vscreen
->caps
.caps
;
606 boolean may_emulate_bgra
= (caps
->v2
.capability_bits
&
607 VIRGL_CAP_APP_TWEAK_SUPPORT
) &&
608 vscreen
->tweak_gles_emulate_bgra
;
610 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
613 if (!util_is_power_of_two_or_zero(sample_count
))
616 assert(target
== PIPE_BUFFER
||
617 target
== PIPE_TEXTURE_1D
||
618 target
== PIPE_TEXTURE_1D_ARRAY
||
619 target
== PIPE_TEXTURE_2D
||
620 target
== PIPE_TEXTURE_2D_ARRAY
||
621 target
== PIPE_TEXTURE_RECT
||
622 target
== PIPE_TEXTURE_3D
||
623 target
== PIPE_TEXTURE_CUBE
||
624 target
== PIPE_TEXTURE_CUBE_ARRAY
);
626 format_desc
= util_format_description(format
);
630 if (util_format_is_intensity(format
))
633 if (sample_count
> 1) {
634 if (!caps
->v1
.bset
.texture_multisample
)
637 if (bind
& PIPE_BIND_SHADER_IMAGE
) {
638 if (sample_count
> caps
->v2
.max_image_samples
)
642 if (sample_count
> caps
->v1
.max_samples
)
646 if (bind
& PIPE_BIND_VERTEX_BUFFER
) {
647 return virgl_is_vertex_format_supported(screen
, format
);
650 if (util_format_is_compressed(format
) && target
== PIPE_BUFFER
)
653 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
654 if ((format
== PIPE_FORMAT_R32G32B32_FLOAT
||
655 format
== PIPE_FORMAT_R32G32B32_SINT
||
656 format
== PIPE_FORMAT_R32G32B32_UINT
) &&
657 target
!= PIPE_BUFFER
)
660 if ((format_desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
||
661 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
||
662 format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) &&
663 target
== PIPE_TEXTURE_3D
)
667 if (bind
& PIPE_BIND_RENDER_TARGET
) {
668 /* For ARB_framebuffer_no_attachments. */
669 if (format
== PIPE_FORMAT_NONE
)
672 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
676 * Although possible, it is unnatural to render into compressed or YUV
677 * surfaces. So disable these here to avoid going into weird paths
678 * inside gallium frontends.
680 if (format_desc
->block
.width
!= 1 ||
681 format_desc
->block
.height
!= 1)
684 if (!virgl_format_check_bitmask(format
,
685 caps
->v1
.render
.bitmask
,
690 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
691 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
695 if (bind
& PIPE_BIND_SCANOUT
) {
696 if (!virgl_format_check_bitmask(format
, caps
->v2
.scanout
.bitmask
, false))
701 * All other operations (sampling, transfer, etc).
704 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
707 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
710 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
713 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
) {
717 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
719 } else if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
723 /* Find the first non-VOID channel. */
724 for (i
= 0; i
< 4; i
++) {
725 if (format_desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
734 if (format_desc
->nr_channels
< 4 && format_desc
->channel
[i
].size
== 4)
738 return virgl_format_check_bitmask(format
,
739 caps
->v1
.sampler
.bitmask
,
743 static void virgl_flush_frontbuffer(struct pipe_screen
*screen
,
744 struct pipe_resource
*res
,
745 unsigned level
, unsigned layer
,
746 void *winsys_drawable_handle
, struct pipe_box
*sub_box
)
748 struct virgl_screen
*vscreen
= virgl_screen(screen
);
749 struct virgl_winsys
*vws
= vscreen
->vws
;
750 struct virgl_resource
*vres
= virgl_resource(res
);
752 if (vws
->flush_frontbuffer
)
753 vws
->flush_frontbuffer(vws
, vres
->hw_res
, level
, layer
, winsys_drawable_handle
,
757 static void virgl_fence_reference(struct pipe_screen
*screen
,
758 struct pipe_fence_handle
**ptr
,
759 struct pipe_fence_handle
*fence
)
761 struct virgl_screen
*vscreen
= virgl_screen(screen
);
762 struct virgl_winsys
*vws
= vscreen
->vws
;
764 vws
->fence_reference(vws
, ptr
, fence
);
767 static bool virgl_fence_finish(struct pipe_screen
*screen
,
768 struct pipe_context
*ctx
,
769 struct pipe_fence_handle
*fence
,
772 struct virgl_screen
*vscreen
= virgl_screen(screen
);
773 struct virgl_winsys
*vws
= vscreen
->vws
;
775 return vws
->fence_wait(vws
, fence
, timeout
);
778 static int virgl_fence_get_fd(struct pipe_screen
*screen
,
779 struct pipe_fence_handle
*fence
)
781 struct virgl_screen
*vscreen
= virgl_screen(screen
);
782 struct virgl_winsys
*vws
= vscreen
->vws
;
784 return vws
->fence_get_fd(vws
, fence
);
788 virgl_get_timestamp(struct pipe_screen
*_screen
)
790 return os_time_get_nano();
794 virgl_destroy_screen(struct pipe_screen
*screen
)
796 struct virgl_screen
*vscreen
= virgl_screen(screen
);
797 struct virgl_winsys
*vws
= vscreen
->vws
;
799 slab_destroy_parent(&vscreen
->transfer_pool
);
807 fixup_formats(union virgl_caps
*caps
, struct virgl_supported_format_mask
*mask
)
809 const size_t size
= ARRAY_SIZE(mask
->bitmask
);
810 for (int i
= 0; i
< size
; ++i
) {
811 if (mask
->bitmask
[i
] != 0)
812 return; /* we got some formats, we definately have a new protocol */
815 /* old protocol used; fall back to considering all sampleable formats valid
818 for (int i
= 0; i
< size
; ++i
)
819 mask
->bitmask
[i
] = caps
->v1
.sampler
.bitmask
[i
];
823 virgl_create_screen(struct virgl_winsys
*vws
, const struct pipe_screen_config
*config
)
825 struct virgl_screen
*screen
= CALLOC_STRUCT(virgl_screen
);
827 const char *VIRGL_GLES_EMULATE_BGRA
= "gles_emulate_bgra";
828 const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE
= "gles_apply_bgra_dest_swizzle";
829 const char *VIRGL_GLES_SAMPLES_PASSED_VALUE
= "gles_samples_passed_value";
834 virgl_debug
= debug_get_option_virgl_debug();
836 if (config
&& config
->options
) {
837 screen
->tweak_gles_emulate_bgra
=
838 driQueryOptionb(config
->options
, VIRGL_GLES_EMULATE_BGRA
);
839 screen
->tweak_gles_apply_bgra_dest_swizzle
=
840 driQueryOptionb(config
->options
, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE
);
841 screen
->tweak_gles_tf3_value
=
842 driQueryOptioni(config
->options
, VIRGL_GLES_SAMPLES_PASSED_VALUE
);
845 screen
->tweak_gles_emulate_bgra
|= !!(virgl_debug
& VIRGL_DEBUG_EMULATE_BGRA
);
846 screen
->tweak_gles_apply_bgra_dest_swizzle
|= !!(virgl_debug
& VIRGL_DEBUG_BGRA_DEST_SWIZZLE
);
849 screen
->base
.get_name
= virgl_get_name
;
850 screen
->base
.get_vendor
= virgl_get_vendor
;
851 screen
->base
.get_param
= virgl_get_param
;
852 screen
->base
.get_shader_param
= virgl_get_shader_param
;
853 screen
->base
.get_compute_param
= virgl_get_compute_param
;
854 screen
->base
.get_paramf
= virgl_get_paramf
;
855 screen
->base
.is_format_supported
= virgl_is_format_supported
;
856 screen
->base
.destroy
= virgl_destroy_screen
;
857 screen
->base
.context_create
= virgl_context_create
;
858 screen
->base
.flush_frontbuffer
= virgl_flush_frontbuffer
;
859 screen
->base
.get_timestamp
= virgl_get_timestamp
;
860 screen
->base
.fence_reference
= virgl_fence_reference
;
861 //screen->base.fence_signalled = virgl_fence_signalled;
862 screen
->base
.fence_finish
= virgl_fence_finish
;
863 screen
->base
.fence_get_fd
= virgl_fence_get_fd
;
865 virgl_init_screen_resource_functions(&screen
->base
);
867 vws
->get_caps(vws
, &screen
->caps
);
868 fixup_formats(&screen
->caps
.caps
,
869 &screen
->caps
.caps
.v2
.supported_readback_formats
);
870 fixup_formats(&screen
->caps
.caps
, &screen
->caps
.caps
.v2
.scanout
);
874 slab_create_parent(&screen
->transfer_pool
, sizeof(struct virgl_transfer
), 16);
876 return &screen
->base
;