src/gallium/drivers/virgl/virgl_screen.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "util/u_memory.h"
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_screen.h"
  27 #include "util/u_video.h"
  28 #include "util/u_math.h"
  29 #include "util/os_time.h"
  30 #include "util/xmlconfig.h"
  31 #include "pipe/p_defines.h"
  32 #include "pipe/p_screen.h"
  33
  34 #include "tgsi/tgsi_exec.h"
  35
  36 #include "virgl_screen.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_public.h"
  39 #include "virgl_context.h"
  40 #include "virgl_protocol.h"
  41
  42 int virgl_debug = 0;
  43 static const struct debug_named_value debug_options[] = {
  44    { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
  45    { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
  46    { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
  47    { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
  48    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
  49    { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
  50    DEBUG_NAMED_VALUE_END
  51 };
  52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
  53
  54 static const char *
  55 virgl_get_vendor(struct pipe_screen *screen)
  56 {
  57    return "Red Hat";
  58 }
  59
  60
  61 static const char *
  62 virgl_get_name(struct pipe_screen *screen)
  63 {
  64    return "virgl";
  65 }
  66
  67 static int
  68 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
  69 {
  70    struct virgl_screen *vscreen = virgl_screen(screen);
  71    switch (param) {
  72    case PIPE_CAP_NPOT_TEXTURES:
  73       return 1;
  74    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77       return 1;
  78    case PIPE_CAP_ANISOTROPIC_FILTER:
  79       return 1;
  80    case PIPE_CAP_POINT_SPRITE:
  81       return 1;
  82    case PIPE_CAP_MAX_RENDER_TARGETS:
  83       return vscreen->caps.caps.v1.max_render_targets;
  84    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  85       return vscreen->caps.caps.v1.max_dual_source_render_targets;
  86    case PIPE_CAP_OCCLUSION_QUERY:
  87       return vscreen->caps.caps.v1.bset.occlusion_query;
  88    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  90       return vscreen->caps.caps.v1.bset.mirror_clamp;
  91    case PIPE_CAP_TEXTURE_SWIZZLE:
  92       return 1;
  93    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  94       if (vscreen->caps.caps.v2.max_texture_2d_size)
  95          return vscreen->caps.caps.v2.max_texture_2d_size;
  96       return 16384;
  97    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  98       if (vscreen->caps.caps.v2.max_texture_3d_size)
  99          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
 100       return 9; /* 256 x 256 x 256 */
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       if (vscreen->caps.caps.v2.max_texture_cube_size)
 103          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
 104       return 13; /* 4K x 4K */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106       return 1;
 107    case PIPE_CAP_INDEP_BLEND_ENABLE:
 108       return vscreen->caps.caps.v1.bset.indep_blend_enable;
 109    case PIPE_CAP_INDEP_BLEND_FUNC:
 110       return vscreen->caps.caps.v1.bset.indep_blend_func;
 111    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 112    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 113    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114       return 1;
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 116       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118       return vscreen->caps.caps.v1.bset.depth_clip_disable;
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120       return vscreen->caps.caps.v1.max_streamout_buffers;
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123       return 16*4;
 124    case PIPE_CAP_PRIMITIVE_RESTART:
 125       return vscreen->caps.caps.v1.bset.primitive_restart;
 126    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 127       return vscreen->caps.caps.v1.bset.shader_stencil_export;
 128    case PIPE_CAP_TGSI_INSTANCEID:
 129    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 130       return 1;
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 132       return vscreen->caps.caps.v1.bset.seamless_cube_map;
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 134       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
 135    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 136       return vscreen->caps.caps.v1.max_texture_array_layers;
 137    case PIPE_CAP_MIN_TEXEL_OFFSET:
 138       return vscreen->caps.caps.v2.min_texel_offset;
 139    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 140       return vscreen->caps.caps.v2.min_texture_gather_offset;
 141    case PIPE_CAP_MAX_TEXEL_OFFSET:
 142       return vscreen->caps.caps.v2.max_texel_offset;
 143    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 144       return vscreen->caps.caps.v2.max_texture_gather_offset;
 145    case PIPE_CAP_CONDITIONAL_RENDER:
 146       return vscreen->caps.caps.v1.bset.conditional_render;
 147    case PIPE_CAP_TEXTURE_BARRIER:
 148       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
 149    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 150       return 1;
 151    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 152    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 153       return vscreen->caps.caps.v1.bset.color_clamping;
 154    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 155       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
 156             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 157    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 158       return vscreen->caps.caps.v1.glsl_level;
 159    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 160       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
 161    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 162    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 163       return 0;
 164    case PIPE_CAP_COMPUTE:
 165       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
 166    case PIPE_CAP_USER_VERTEX_BUFFERS:
 167       return 0;
 168    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 169       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
 170    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 171    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 172       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
 173    case PIPE_CAP_START_INSTANCE:
 174       return vscreen->caps.caps.v1.bset.start_instance;
 175    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 176    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 177    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 178    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 179    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180       return 0;
 181    case PIPE_CAP_QUERY_TIMESTAMP:
 182       return 1;
 183    case PIPE_CAP_QUERY_TIME_ELAPSED:
 184       return 1;
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186       return 0;
 187    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 188       return VIRGL_MAP_BUFFER_ALIGNMENT;
 189    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 190       return vscreen->caps.caps.v1.max_tbo_size > 0;
 191    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 192       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
 193    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 194       return 0;
 195    case PIPE_CAP_CUBE_MAP_ARRAY:
 196       return vscreen->caps.caps.v1.bset.cube_map_array;
 197    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 198       return vscreen->caps.caps.v1.bset.texture_multisample;
 199    case PIPE_CAP_MAX_VIEWPORTS:
 200       return vscreen->caps.caps.v1.max_viewports;
 201    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 202       return vscreen->caps.caps.v1.max_tbo_size;
 203    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 204    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 205    case PIPE_CAP_ENDIANNESS:
 206       return 0;
 207    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 208    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 209       return 1;
 210    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 211       return 0;
 212    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 213       return vscreen->caps.caps.v2.max_geom_output_vertices;
 214    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 215       return vscreen->caps.caps.v2.max_geom_total_output_components;
 216    case PIPE_CAP_TEXTURE_QUERY_LOD:
 217       return vscreen->caps.caps.v1.bset.texture_query_lod;
 218    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 219       return vscreen->caps.caps.v1.max_texture_gather_components;
 220    case PIPE_CAP_DRAW_INDIRECT:
 221       return vscreen->caps.caps.v1.bset.has_indirect_draw;
 222    case PIPE_CAP_SAMPLE_SHADING:
 223    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 224       return vscreen->caps.caps.v1.bset.has_sample_shading;
 225    case PIPE_CAP_CULL_DISTANCE:
 226       return vscreen->caps.caps.v1.bset.has_cull;
 227    case PIPE_CAP_MAX_VERTEX_STREAMS:
 228       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
 229               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
 230    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 231       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
 232    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 233       return vscreen->caps.caps.v1.bset.derivative_control;
 234    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 235       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
 236    case PIPE_CAP_QUERY_SO_OVERFLOW:
 237       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
 238    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 239       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
 240    case PIPE_CAP_DOUBLES:
 241       return vscreen->caps.caps.v1.bset.has_fp64 ||
 242             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
 243    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 244       return vscreen->caps.caps.v2.max_shader_patch_varyings;
 245    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 246       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
 247    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 248       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
 249    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 250       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
 251    case PIPE_CAP_TGSI_TXQS:
 252       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
 255    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 256       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
 257    case PIPE_CAP_FBFETCH:
 258       return (vscreen->caps.caps.v2.capability_bits &
 259               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
 260    case PIPE_CAP_TGSI_CLOCK:
 261       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
 262    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 263       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
 264    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 265       return vscreen->caps.caps.v2.max_combined_shader_buffers;
 266    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 267       return vscreen->caps.caps.v2.max_combined_atomic_counters;
 268    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 269       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
 270    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 271    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 272       return 1; /* TODO: need to introduce a hw-cap for this */
 273    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 274       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
 275    case PIPE_CAP_MAX_VARYINGS:
 276       if (vscreen->caps.caps.v1.glsl_level < 150)
 277          return vscreen->caps.caps.v2.max_vertex_attribs;
 278       return 32;
 279    case PIPE_CAP_FAKE_SW_MSAA:
 280       /* If the host supports only one sample (e.g., if it is using softpipe),
 281        * fake multisampling to able to advertise higher GL versions. */
 282       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
 283    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 284       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
 285    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 286       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
 287    case PIPE_CAP_TEXTURE_GATHER_SM5:
 288    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 289    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 290    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 291    case PIPE_CAP_VERTEXID_NOBASE:
 292    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 293    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 295    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 296    case PIPE_CAP_SHAREABLE_SHADERS:
 297    case PIPE_CAP_CLEAR_TEXTURE:
 298    case PIPE_CAP_DRAW_PARAMETERS:
 299    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 300    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 301    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 302    case PIPE_CAP_INVALIDATE_BUFFER:
 303    case PIPE_CAP_GENERATE_MIPMAP:
 304    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 305    case PIPE_CAP_STRING_MARKER:
 306    case PIPE_CAP_QUERY_MEMORY_INFO:
 307    case PIPE_CAP_PCI_GROUP:
 308    case PIPE_CAP_PCI_BUS:
 309    case PIPE_CAP_PCI_DEVICE:
 310    case PIPE_CAP_PCI_FUNCTION:
 311    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 312    case PIPE_CAP_TGSI_VOTE:
 313    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 314    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 315    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 316    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 317    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 318    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 319    case PIPE_CAP_INT64:
 320    case PIPE_CAP_INT64_DIVMOD:
 321    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 322    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 323    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 324    case PIPE_CAP_TGSI_BALLOT:
 325    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 326    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 327    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 328    case PIPE_CAP_POST_DEPTH_COVERAGE:
 329    case PIPE_CAP_BINDLESS_TEXTURE:
 330    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 331    case PIPE_CAP_MEMOBJ:
 332    case PIPE_CAP_LOAD_CONSTBUF:
 333    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 334    case PIPE_CAP_TILE_RASTER_ORDER:
 335    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 336    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 337    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 338    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 339    case PIPE_CAP_FENCE_SIGNAL:
 340    case PIPE_CAP_CONSTBUF0_FLAGS:
 341    case PIPE_CAP_PACKED_UNIFORMS:
 342    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 343    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 344    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 345    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 346    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 347    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 348    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 349    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 350       return 0;
 351    case PIPE_CAP_CLIP_HALFZ:
 352       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
 353    case PIPE_CAP_MAX_GS_INVOCATIONS:
 354       return 32;
 355    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 356       return 1 << 27;
 357    case PIPE_CAP_VENDOR_ID:
 358       return 0x1af4;
 359    case PIPE_CAP_DEVICE_ID:
 360       return 0x1010;
 361    case PIPE_CAP_ACCELERATED:
 362       return 1;
 363    case PIPE_CAP_UMA:
 364    case PIPE_CAP_VIDEO_MEMORY:
 365       return 0;
 366    case PIPE_CAP_NATIVE_FENCE_FD:
 367       return vscreen->vws->supports_fences;
 368    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 369       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
 370             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 371    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 372       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 373    default:
 374       return u_pipe_screen_get_param_defaults(screen, param);
 375    }
 376 }
 377
 378 static int
 379 virgl_get_shader_param(struct pipe_screen *screen,
 380                        enum pipe_shader_type shader,
 381                        enum pipe_shader_cap param)
 382 {
 383    struct virgl_screen *vscreen = virgl_screen(screen);
 384
 385    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
 386        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
 387       return 0;
 388
 389    if (shader == PIPE_SHADER_COMPUTE &&
 390        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 391      return 0;
 392
 393    switch(shader)
 394    {
 395    case PIPE_SHADER_FRAGMENT:
 396    case PIPE_SHADER_VERTEX:
 397    case PIPE_SHADER_GEOMETRY:
 398    case PIPE_SHADER_TESS_CTRL:
 399    case PIPE_SHADER_TESS_EVAL:
 400    case PIPE_SHADER_COMPUTE:
 401       switch (param) {
 402       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 403       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 404       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 405       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 406          return INT_MAX;
 407       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 408       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 409       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 410          return 1;
 411       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 412       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 413          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 414       case PIPE_SHADER_CAP_MAX_INPUTS:
 415          if (vscreen->caps.caps.v1.glsl_level < 150)
 416             return vscreen->caps.caps.v2.max_vertex_attribs;
 417          return (shader == PIPE_SHADER_VERTEX ||
 418                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
 419       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 420          if (shader == PIPE_SHADER_FRAGMENT)
 421             return vscreen->caps.caps.v1.max_render_targets;
 422          return vscreen->caps.caps.v2.max_vertex_outputs;
 423      // case PIPE_SHADER_CAP_MAX_CONSTS:
 424      //    return 4096;
 425       case PIPE_SHADER_CAP_MAX_TEMPS:
 426          return 256;
 427       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 428          return vscreen->caps.caps.v1.max_uniform_blocks;
 429     //  case PIPE_SHADER_CAP_MAX_ADDRS:
 430      //    return 1;
 431       case PIPE_SHADER_CAP_SUBROUTINES:
 432          return 1;
 433       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 434             return 16;
 435       case PIPE_SHADER_CAP_INTEGERS:
 436          return vscreen->caps.caps.v1.glsl_level >= 130;
 437       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 438          return 32;
 439       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 440          return 4096 * sizeof(float[4]);
 441       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 442          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 443             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
 444          else
 445             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
 446       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 447          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 448             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
 449          else
 450             return vscreen->caps.caps.v2.max_shader_image_other_stages;
 451       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 452          return (1 << PIPE_SHADER_IR_TGSI);
 453       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 454          return vscreen->caps.caps.v2.max_atomic_counters[shader];
 455       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 456          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
 457       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 458       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 459       case PIPE_SHADER_CAP_INT64_ATOMICS:
 460       case PIPE_SHADER_CAP_FP16:
 461          return 0;
 462       case PIPE_SHADER_CAP_SCALAR_ISA:
 463          return 1;
 464       default:
 465          return 0;
 466       }
 467    default:
 468       return 0;
 469    }
 470 }
 471
 472 static float
 473 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 474 {
 475    struct virgl_screen *vscreen = virgl_screen(screen);
 476    switch (param) {
 477    case PIPE_CAPF_MAX_LINE_WIDTH:
 478       return vscreen->caps.caps.v2.max_aliased_line_width;
 479    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 480       return vscreen->caps.caps.v2.max_smooth_line_width;
 481    case PIPE_CAPF_MAX_POINT_WIDTH:
 482       return vscreen->caps.caps.v2.max_aliased_point_size;
 483    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 484       return vscreen->caps.caps.v2.max_smooth_point_size;
 485    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 486       return 16.0;
 487    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 488       return vscreen->caps.caps.v2.max_texture_lod_bias;
 489    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 490    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 491    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 492       return 0.0f;
 493    }
 494    /* should only get here on unhandled cases */
 495    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 496    return 0.0;
 497 }
 498
 499 static int
 500 virgl_get_compute_param(struct pipe_screen *screen,
 501                         enum pipe_shader_ir ir_type,
 502                         enum pipe_compute_cap param,
 503                         void *ret)
 504 {
 505    struct virgl_screen *vscreen = virgl_screen(screen);
 506    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 507       return 0;
 508    switch (param) {
 509    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 510       if (ret) {
 511          uint64_t *grid_size = ret;
 512          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
 513          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
 514          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
 515       }
 516       return 3 * sizeof(uint64_t) ;
 517    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 518       if (ret) {
 519          uint64_t *block_size = ret;
 520          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
 521          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
 522          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
 523       }
 524       return 3 * sizeof(uint64_t);
 525    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 526       if (ret) {
 527          uint64_t *max_threads_per_block = ret;
 528          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
 529       }
 530       return sizeof(uint64_t);
 531    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 532       if (ret) {
 533          uint64_t *max_local_size = ret;
 534          /* Value reported by the closed source driver. */
 535          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
 536       }
 537       return sizeof(uint64_t);
 538    default:
 539       break;
 540    }
 541    return 0;
 542 }
 543
 544 static bool
 545 has_format_bit(struct virgl_supported_format_mask *mask,
 546                enum virgl_formats fmt)
 547 {
 548    assert(fmt < VIRGL_FORMAT_MAX);
 549    unsigned val = (unsigned)fmt;
 550    unsigned idx = val / 32;
 551    unsigned bit = val % 32;
 552    assert(idx < ARRAY_SIZE(mask->bitmask));
 553    return (mask->bitmask[val / 32] & (1u << bit)) != 0;
 554 }
 555
 556 bool
 557 virgl_has_readback_format(struct pipe_screen *screen,
 558                           enum virgl_formats fmt)
 559 {
 560    struct virgl_screen *vscreen = virgl_screen(screen);
 561    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
 562                          fmt);
 563 }
 564
 565 static bool
 566 virgl_is_vertex_format_supported(struct pipe_screen *screen,
 567                                  enum pipe_format format)
 568 {
 569    struct virgl_screen *vscreen = virgl_screen(screen);
 570    const struct util_format_description *format_desc;
 571    int i;
 572
 573    format_desc = util_format_description(format);
 574    if (!format_desc)
 575       return false;
 576
 577    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 578       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
 579       int big = vformat / 32;
 580       int small = vformat % 32;
 581       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
 582          return false;
 583       return true;
 584    }
 585
 586    /* Find the first non-VOID channel. */
 587    for (i = 0; i < 4; i++) {
 588       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 589          break;
 590       }
 591    }
 592
 593    if (i == 4)
 594       return false;
 595
 596    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 597       return false;
 598
 599    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
 600       return false;
 601    return true;
 602 }
 603
 604 static bool
 605 virgl_format_check_bitmask(enum pipe_format format,
 606                            uint32_t bitmask[16],
 607                            bool may_emulate_bgra)
 608 {
 609    int big = format / 32;
 610    int small = format % 32;
 611    if ((bitmask[big] & (1 << small)))
 612       return true;
 613
 614    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
 615     * emulate it by using a swizzled RGBx */
 616    if (may_emulate_bgra) {
 617       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
 618          format = PIPE_FORMAT_R8G8B8A8_SRGB;
 619       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
 620          format = PIPE_FORMAT_R8G8B8X8_SRGB;
 621       else {
 622          return false;
 623       }
 624
 625       big = format / 32;
 626       small = format % 32;
 627       if (bitmask[big] & (1 << small))
 628          return true;
 629    }
 630    return false;
 631 }
 632
 633 /**
 634  * Query format support for creating a texture, drawing surface, etc.
 635  * \param format  the format to test
 636  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 637  */
 638 static bool
 639 virgl_is_format_supported( struct pipe_screen *screen,
 640                                  enum pipe_format format,
 641                                  enum pipe_texture_target target,
 642                                  unsigned sample_count,
 643                                  unsigned storage_sample_count,
 644                                  unsigned bind)
 645 {
 646    struct virgl_screen *vscreen = virgl_screen(screen);
 647    const struct util_format_description *format_desc;
 648    int i;
 649
 650    boolean may_emulate_bgra = false;
 651
 652    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 653       return false;
 654
 655    assert(target == PIPE_BUFFER ||
 656           target == PIPE_TEXTURE_1D ||
 657           target == PIPE_TEXTURE_1D_ARRAY ||
 658           target == PIPE_TEXTURE_2D ||
 659           target == PIPE_TEXTURE_2D_ARRAY ||
 660           target == PIPE_TEXTURE_RECT ||
 661           target == PIPE_TEXTURE_3D ||
 662           target == PIPE_TEXTURE_CUBE ||
 663           target == PIPE_TEXTURE_CUBE_ARRAY);
 664
 665    format_desc = util_format_description(format);
 666    if (!format_desc)
 667       return false;
 668
 669    if (util_format_is_intensity(format))
 670       return false;
 671
 672    if (sample_count > 1) {
 673       if (!vscreen->caps.caps.v1.bset.texture_multisample)
 674          return false;
 675
 676       if (bind & PIPE_BIND_SHADER_IMAGE) {
 677          if (sample_count > vscreen->caps.caps.v2.max_image_samples)
 678             return false;
 679       }
 680
 681       if (sample_count > vscreen->caps.caps.v1.max_samples)
 682          return false;
 683    }
 684
 685    if (bind & PIPE_BIND_VERTEX_BUFFER) {
 686       return virgl_is_vertex_format_supported(screen, format);
 687    }
 688
 689    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
 690       return false;
 691
 692    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
 693    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
 694        format == PIPE_FORMAT_R32G32B32_SINT ||
 695        format == PIPE_FORMAT_R32G32B32_UINT) &&
 696        target != PIPE_BUFFER)
 697       return false;
 698
 699    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
 700         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
 701         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
 702        target == PIPE_TEXTURE_3D)
 703       return false;
 704
 705    may_emulate_bgra = (vscreen->caps.caps.v2.capability_bits &
 706                        VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 707                       vscreen->tweak_gles_emulate_bgra;
 708
 709    if (bind & PIPE_BIND_RENDER_TARGET) {
 710       /* For ARB_framebuffer_no_attachments. */
 711       if (format == PIPE_FORMAT_NONE)
 712          return TRUE;
 713
 714       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 715          return false;
 716
 717       /*
 718        * Although possible, it is unnatural to render into compressed or YUV
 719        * surfaces. So disable these here to avoid going into weird paths
 720        * inside the state trackers.
 721        */
 722       if (format_desc->block.width != 1 ||
 723           format_desc->block.height != 1)
 724          return false;
 725
 726       if (!virgl_format_check_bitmask(format,
 727                                       vscreen->caps.caps.v1.render.bitmask,
 728                                       may_emulate_bgra))
 729          return false;
 730    }
 731
 732    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 733       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 734          return false;
 735    }
 736
 737    /*
 738     * All other operations (sampling, transfer, etc).
 739     */
 740
 741    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 742       goto out_lookup;
 743    }
 744    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 745       goto out_lookup;
 746    }
 747    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
 748       goto out_lookup;
 749    }
 750
 751    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 752       goto out_lookup;
 753    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 754       goto out_lookup;
 755    }
 756
 757    /* Find the first non-VOID channel. */
 758    for (i = 0; i < 4; i++) {
 759       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 760          break;
 761       }
 762    }
 763
 764    if (i == 4)
 765       return false;
 766
 767    /* no L4A4 */
 768    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
 769       return false;
 770
 771  out_lookup:
 772    return virgl_format_check_bitmask(format,
 773                                      vscreen->caps.caps.v1.sampler.bitmask,
 774                                      may_emulate_bgra);
 775 }
 776
 777 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
 778                                       struct pipe_resource *res,
 779                                       unsigned level, unsigned layer,
 780                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
 781 {
 782    struct virgl_screen *vscreen = virgl_screen(screen);
 783    struct virgl_winsys *vws = vscreen->vws;
 784    struct virgl_resource *vres = virgl_resource(res);
 785
 786    if (vws->flush_frontbuffer)
 787       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
 788                              sub_box);
 789 }
 790
 791 static void virgl_fence_reference(struct pipe_screen *screen,
 792                                   struct pipe_fence_handle **ptr,
 793                                   struct pipe_fence_handle *fence)
 794 {
 795    struct virgl_screen *vscreen = virgl_screen(screen);
 796    struct virgl_winsys *vws = vscreen->vws;
 797
 798    vws->fence_reference(vws, ptr, fence);
 799 }
 800
 801 static bool virgl_fence_finish(struct pipe_screen *screen,
 802                                struct pipe_context *ctx,
 803                                struct pipe_fence_handle *fence,
 804                                uint64_t timeout)
 805 {
 806    struct virgl_screen *vscreen = virgl_screen(screen);
 807    struct virgl_winsys *vws = vscreen->vws;
 808
 809    return vws->fence_wait(vws, fence, timeout);
 810 }
 811
 812 static int virgl_fence_get_fd(struct pipe_screen *screen,
 813             struct pipe_fence_handle *fence)
 814 {
 815    struct virgl_screen *vscreen = virgl_screen(screen);
 816    struct virgl_winsys *vws = vscreen->vws;
 817
 818    return vws->fence_get_fd(vws, fence);
 819 }
 820
 821 static uint64_t
 822 virgl_get_timestamp(struct pipe_screen *_screen)
 823 {
 824    return os_time_get_nano();
 825 }
 826
 827 static void
 828 virgl_destroy_screen(struct pipe_screen *screen)
 829 {
 830    struct virgl_screen *vscreen = virgl_screen(screen);
 831    struct virgl_winsys *vws = vscreen->vws;
 832
 833    slab_destroy_parent(&vscreen->transfer_pool);
 834
 835    if (vws)
 836       vws->destroy(vws);
 837    FREE(vscreen);
 838 }
 839
 840 static void
 841 fixup_readback_format(union virgl_caps *caps)
 842 {
 843    const size_t size = ARRAY_SIZE(caps->v2.supported_readback_formats.bitmask);
 844    for (int i = 0; i < size; ++i) {
 845       if (caps->v2.supported_readback_formats.bitmask[i] != 0)
 846          return; /* we got some formats, we definately have a new protocol */
 847    }
 848
 849    /* old protocol used; fall back to considering all sampleable formats valid
 850     * readback-formats
 851     */
 852    for (int i = 0; i < size; ++i) {
 853       caps->v2.supported_readback_formats.bitmask[i] =
 854          caps->v1.sampler.bitmask[i];
 855    }
 856 }
 857
 858 struct pipe_screen *
 859 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
 860 {
 861    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
 862
 863    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
 864    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
 865    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
 866
 867    if (!screen)
 868       return NULL;
 869
 870    virgl_debug = debug_get_option_virgl_debug();
 871
 872    if (config && config->options) {
 873       screen->tweak_gles_emulate_bgra =
 874             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
 875       screen->tweak_gles_apply_bgra_dest_swizzle =
 876             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
 877       screen->tweak_gles_tf3_value =
 878             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
 879    }
 880
 881    screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
 882    screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
 883
 884    screen->vws = vws;
 885    screen->base.get_name = virgl_get_name;
 886    screen->base.get_vendor = virgl_get_vendor;
 887    screen->base.get_param = virgl_get_param;
 888    screen->base.get_shader_param = virgl_get_shader_param;
 889    screen->base.get_compute_param = virgl_get_compute_param;
 890    screen->base.get_paramf = virgl_get_paramf;
 891    screen->base.is_format_supported = virgl_is_format_supported;
 892    screen->base.destroy = virgl_destroy_screen;
 893    screen->base.context_create = virgl_context_create;
 894    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
 895    screen->base.get_timestamp = virgl_get_timestamp;
 896    screen->base.fence_reference = virgl_fence_reference;
 897    //screen->base.fence_signalled = virgl_fence_signalled;
 898    screen->base.fence_finish = virgl_fence_finish;
 899    screen->base.fence_get_fd = virgl_fence_get_fd;
 900
 901    virgl_init_screen_resource_functions(&screen->base);
 902
 903    vws->get_caps(vws, &screen->caps);
 904    fixup_readback_format(&screen->caps.caps);
 905
 906    screen->refcnt = 1;
 907
 908    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 909
 910    return &screen->base;
 911 }