gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.
[mesa.git] / src / gallium / drivers / virgl / virgl_screen.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "util/u_memory.h"
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_video.h"
27 #include "util/u_math.h"
28 #include "util/os_time.h"
29 #include "pipe/p_defines.h"
30 #include "pipe/p_screen.h"
31
32 #include "tgsi/tgsi_exec.h"
33
34 #include "virgl_screen.h"
35 #include "virgl_resource.h"
36 #include "virgl_public.h"
37 #include "virgl_context.h"
38
39 static const char *
40 virgl_get_vendor(struct pipe_screen *screen)
41 {
42 return "Red Hat";
43 }
44
45
46 static const char *
47 virgl_get_name(struct pipe_screen *screen)
48 {
49 return "virgl";
50 }
51
52 static int
53 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
54 {
55 struct virgl_screen *vscreen = virgl_screen(screen);
56 switch (param) {
57 case PIPE_CAP_NPOT_TEXTURES:
58 return 1;
59 case PIPE_CAP_SM3:
60 return 1;
61 case PIPE_CAP_ANISOTROPIC_FILTER:
62 return 1;
63 case PIPE_CAP_POINT_SPRITE:
64 return 1;
65 case PIPE_CAP_MAX_RENDER_TARGETS:
66 return vscreen->caps.caps.v1.max_render_targets;
67 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
68 return vscreen->caps.caps.v1.max_dual_source_render_targets;
69 case PIPE_CAP_OCCLUSION_QUERY:
70 return vscreen->caps.caps.v1.bset.occlusion_query;
71 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
72 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
73 return vscreen->caps.caps.v1.bset.mirror_clamp;
74 case PIPE_CAP_TEXTURE_SWIZZLE:
75 return 1;
76 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
77 if (vscreen->caps.caps.v2.max_texture_2d_size)
78 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_2d_size);
79 return 15; /* 16K x 16K */
80 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
81 if (vscreen->caps.caps.v2.max_texture_3d_size)
82 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
83 return 9; /* 256 x 256 x 256 */
84 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
85 if (vscreen->caps.caps.v2.max_texture_cube_size)
86 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
87 return 13; /* 4K x 4K */
88 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
89 return 1;
90 case PIPE_CAP_INDEP_BLEND_ENABLE:
91 return vscreen->caps.caps.v1.bset.indep_blend_enable;
92 case PIPE_CAP_INDEP_BLEND_FUNC:
93 return vscreen->caps.caps.v1.bset.indep_blend_func;
94 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
95 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
97 return 1;
98 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
99 return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
100 case PIPE_CAP_DEPTH_CLIP_DISABLE:
101 return vscreen->caps.caps.v1.bset.depth_clip_disable;
102 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
103 return vscreen->caps.caps.v1.max_streamout_buffers;
104 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
105 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
106 return 16*4;
107 case PIPE_CAP_PRIMITIVE_RESTART:
108 return vscreen->caps.caps.v1.bset.primitive_restart;
109 case PIPE_CAP_SHADER_STENCIL_EXPORT:
110 return vscreen->caps.caps.v1.bset.shader_stencil_export;
111 case PIPE_CAP_TGSI_INSTANCEID:
112 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
113 return 1;
114 case PIPE_CAP_SEAMLESS_CUBE_MAP:
115 return vscreen->caps.caps.v1.bset.seamless_cube_map;
116 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
117 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
118 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
119 return vscreen->caps.caps.v1.max_texture_array_layers;
120 case PIPE_CAP_MIN_TEXEL_OFFSET:
121 return vscreen->caps.caps.v2.min_texel_offset;
122 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
123 return vscreen->caps.caps.v2.min_texture_gather_offset;
124 case PIPE_CAP_MAX_TEXEL_OFFSET:
125 return vscreen->caps.caps.v2.max_texel_offset;
126 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
127 return vscreen->caps.caps.v2.max_texture_gather_offset;
128 case PIPE_CAP_CONDITIONAL_RENDER:
129 return vscreen->caps.caps.v1.bset.conditional_render;
130 case PIPE_CAP_TEXTURE_BARRIER:
131 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
132 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
133 return 1;
134 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
135 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
136 return vscreen->caps.caps.v1.bset.color_clamping;
137 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
138 return 1;
139 case PIPE_CAP_GLSL_FEATURE_LEVEL:
140 return vscreen->caps.caps.v1.glsl_level;
141 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
142 return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
143 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
144 return 0;
145 case PIPE_CAP_COMPUTE:
146 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
147 case PIPE_CAP_USER_VERTEX_BUFFERS:
148 return 0;
149 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
150 return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
151 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
152 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
153 return vscreen->caps.caps.v1.bset.streamout_pause_resume;
154 case PIPE_CAP_START_INSTANCE:
155 return vscreen->caps.caps.v1.bset.start_instance;
156 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
157 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
158 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
159 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
160 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
161 return 0;
162 case PIPE_CAP_QUERY_TIMESTAMP:
163 return 1;
164 case PIPE_CAP_QUERY_TIME_ELAPSED:
165 return 0;
166 case PIPE_CAP_TGSI_TEXCOORD:
167 return 0;
168 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
169 return VIRGL_MAP_BUFFER_ALIGNMENT;
170 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
171 return vscreen->caps.caps.v1.max_tbo_size > 0;
172 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
173 return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
174 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
175 return 0;
176 case PIPE_CAP_CUBE_MAP_ARRAY:
177 return vscreen->caps.caps.v1.bset.cube_map_array;
178 case PIPE_CAP_TEXTURE_MULTISAMPLE:
179 return vscreen->caps.caps.v1.bset.texture_multisample;
180 case PIPE_CAP_MAX_VIEWPORTS:
181 return vscreen->caps.caps.v1.max_viewports;
182 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
183 return vscreen->caps.caps.v1.max_tbo_size;
184 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
185 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
186 case PIPE_CAP_ENDIANNESS:
187 return 0;
188 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
189 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
190 return 1;
191 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
192 return 0;
193 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
194 return vscreen->caps.caps.v2.max_geom_output_vertices;
195 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
196 return vscreen->caps.caps.v2.max_geom_total_output_components;
197 case PIPE_CAP_TEXTURE_QUERY_LOD:
198 return vscreen->caps.caps.v1.bset.texture_query_lod;
199 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
200 return vscreen->caps.caps.v1.max_texture_gather_components;
201 case PIPE_CAP_DRAW_INDIRECT:
202 return vscreen->caps.caps.v1.bset.has_indirect_draw;
203 case PIPE_CAP_SAMPLE_SHADING:
204 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
205 return vscreen->caps.caps.v1.bset.has_sample_shading;
206 case PIPE_CAP_CULL_DISTANCE:
207 return vscreen->caps.caps.v1.bset.has_cull;
208 case PIPE_CAP_MAX_VERTEX_STREAMS:
209 return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1;
210 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
211 return vscreen->caps.caps.v1.bset.conditional_render_inverted;
212 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
213 return vscreen->caps.caps.v1.bset.derivative_control;
214 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
215 return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
216 case PIPE_CAP_QUERY_SO_OVERFLOW:
217 return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
218 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
219 return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
220 case PIPE_CAP_DOUBLES:
221 return vscreen->caps.caps.v1.bset.has_fp64;
222 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
223 return vscreen->caps.caps.v2.max_shader_patch_varyings;
224 case PIPE_CAP_SAMPLER_VIEW_TARGET:
225 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
226 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
227 return vscreen->caps.caps.v2.max_vertex_attrib_stride;
228 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
229 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
230 case PIPE_CAP_TGSI_TXQS:
231 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
232 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
233 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
234 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
235 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
236 case PIPE_CAP_TGSI_FS_FBFETCH:
237 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH;
238 case PIPE_CAP_TGSI_CLOCK:
239 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
240 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
241 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
242 case PIPE_CAP_TEXTURE_GATHER_SM5:
243 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
244 case PIPE_CAP_FAKE_SW_MSAA:
245 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
246 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
247 case PIPE_CAP_MULTI_DRAW_INDIRECT:
248 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
249 case PIPE_CAP_CLIP_HALFZ:
250 case PIPE_CAP_VERTEXID_NOBASE:
251 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
252 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
253 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
254 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
255 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
256 case PIPE_CAP_DEPTH_BOUNDS_TEST:
257 case PIPE_CAP_SHAREABLE_SHADERS:
258 case PIPE_CAP_CLEAR_TEXTURE:
259 case PIPE_CAP_DRAW_PARAMETERS:
260 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
261 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
262 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
263 case PIPE_CAP_INVALIDATE_BUFFER:
264 case PIPE_CAP_GENERATE_MIPMAP:
265 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
266 case PIPE_CAP_QUERY_BUFFER_OBJECT:
267 case PIPE_CAP_STRING_MARKER:
268 case PIPE_CAP_QUERY_MEMORY_INFO:
269 case PIPE_CAP_PCI_GROUP:
270 case PIPE_CAP_PCI_BUS:
271 case PIPE_CAP_PCI_DEVICE:
272 case PIPE_CAP_PCI_FUNCTION:
273 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
274 case PIPE_CAP_TGSI_VOTE:
275 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
276 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
277 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
278 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
279 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
280 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
281 case PIPE_CAP_INT64:
282 case PIPE_CAP_INT64_DIVMOD:
283 case PIPE_CAP_TGSI_TEX_TXF_LZ:
284 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
285 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
286 case PIPE_CAP_TGSI_BALLOT:
287 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
288 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
289 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
290 case PIPE_CAP_POST_DEPTH_COVERAGE:
291 case PIPE_CAP_BINDLESS_TEXTURE:
292 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
293 case PIPE_CAP_MEMOBJ:
294 case PIPE_CAP_LOAD_CONSTBUF:
295 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
296 case PIPE_CAP_TILE_RASTER_ORDER:
297 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
298 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
299 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
300 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
301 case PIPE_CAP_FENCE_SIGNAL:
302 case PIPE_CAP_CONSTBUF0_FLAGS:
303 case PIPE_CAP_PACKED_UNIFORMS:
304 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
305 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
306 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
307 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
308 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
309 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
310 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
311 return 0;
312 case PIPE_CAP_MAX_GS_INVOCATIONS:
313 return 32;
314 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
315 return 1 << 27;
316 case PIPE_CAP_VENDOR_ID:
317 return 0x1af4;
318 case PIPE_CAP_DEVICE_ID:
319 return 0x1010;
320 case PIPE_CAP_ACCELERATED:
321 return 1;
322 case PIPE_CAP_UMA:
323 case PIPE_CAP_VIDEO_MEMORY:
324 return 0;
325 case PIPE_CAP_NATIVE_FENCE_FD:
326 return 0;
327 }
328 /* should only get here on unhandled cases */
329 debug_printf("Unexpected PIPE_CAP %d query\n", param);
330 return 0;
331 }
332
333 static int
334 virgl_get_shader_param(struct pipe_screen *screen,
335 enum pipe_shader_type shader,
336 enum pipe_shader_cap param)
337 {
338 struct virgl_screen *vscreen = virgl_screen(screen);
339
340 if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
341 !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
342 return 0;
343
344 if (shader == PIPE_SHADER_COMPUTE &&
345 !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
346 return 0;
347
348 switch(shader)
349 {
350 case PIPE_SHADER_FRAGMENT:
351 case PIPE_SHADER_VERTEX:
352 case PIPE_SHADER_GEOMETRY:
353 case PIPE_SHADER_TESS_CTRL:
354 case PIPE_SHADER_TESS_EVAL:
355 case PIPE_SHADER_COMPUTE:
356 switch (param) {
357 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
358 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
359 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
360 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
361 return INT_MAX;
362 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
363 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
364 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
365 return 1;
366 case PIPE_SHADER_CAP_MAX_INPUTS:
367 if (vscreen->caps.caps.v1.glsl_level < 150)
368 return vscreen->caps.caps.v2.max_vertex_attribs;
369 return (shader == PIPE_SHADER_VERTEX ||
370 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
371 case PIPE_SHADER_CAP_MAX_OUTPUTS:
372 if (shader == PIPE_SHADER_FRAGMENT)
373 return vscreen->caps.caps.v1.max_render_targets;
374 return vscreen->caps.caps.v2.max_vertex_outputs;
375 // case PIPE_SHADER_CAP_MAX_CONSTS:
376 // return 4096;
377 case PIPE_SHADER_CAP_MAX_TEMPS:
378 return 256;
379 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
380 return vscreen->caps.caps.v1.max_uniform_blocks;
381 // case PIPE_SHADER_CAP_MAX_ADDRS:
382 // return 1;
383 case PIPE_SHADER_CAP_SUBROUTINES:
384 return 1;
385 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
386 return 16;
387 case PIPE_SHADER_CAP_INTEGERS:
388 return vscreen->caps.caps.v1.glsl_level >= 130;
389 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
390 return 32;
391 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
392 return 4096 * sizeof(float[4]);
393 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
394 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
395 return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
396 else
397 return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
398 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
399 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
400 return vscreen->caps.caps.v2.max_shader_image_frag_compute;
401 else
402 return vscreen->caps.caps.v2.max_shader_image_other_stages;
403 case PIPE_SHADER_CAP_SUPPORTED_IRS:
404 return (1 << PIPE_SHADER_IR_TGSI);
405 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
406 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
407 case PIPE_SHADER_CAP_INT64_ATOMICS:
408 case PIPE_SHADER_CAP_FP16:
409 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
410 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
411 return 0;
412 case PIPE_SHADER_CAP_SCALAR_ISA:
413 return 1;
414 default:
415 return 0;
416 }
417 default:
418 return 0;
419 }
420 }
421
422 static float
423 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
424 {
425 struct virgl_screen *vscreen = virgl_screen(screen);
426 switch (param) {
427 case PIPE_CAPF_MAX_LINE_WIDTH:
428 return vscreen->caps.caps.v2.max_aliased_line_width;
429 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
430 return vscreen->caps.caps.v2.max_smooth_line_width;
431 case PIPE_CAPF_MAX_POINT_WIDTH:
432 return vscreen->caps.caps.v2.max_aliased_point_size;
433 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
434 return vscreen->caps.caps.v2.max_smooth_point_size;
435 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
436 return 16.0;
437 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
438 return vscreen->caps.caps.v2.max_texture_lod_bias;
439 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
440 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
441 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
442 return 0.0f;
443 }
444 /* should only get here on unhandled cases */
445 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
446 return 0.0;
447 }
448
449 static int
450 virgl_get_compute_param(struct pipe_screen *screen,
451 enum pipe_shader_ir ir_type,
452 enum pipe_compute_cap param,
453 void *ret)
454 {
455 struct virgl_screen *vscreen = virgl_screen(screen);
456 if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
457 return 0;
458 switch (param) {
459 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
460 if (ret) {
461 uint64_t *grid_size = ret;
462 grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
463 grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
464 grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
465 }
466 return 3 * sizeof(uint64_t) ;
467 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
468 if (ret) {
469 uint64_t *block_size = ret;
470 block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
471 block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
472 block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
473 }
474 return 3 * sizeof(uint64_t);
475 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
476 if (ret) {
477 uint64_t *max_threads_per_block = ret;
478 *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
479 }
480 return sizeof(uint64_t);
481 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
482 if (ret) {
483 uint64_t *max_local_size = ret;
484 /* Value reported by the closed source driver. */
485 *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
486 }
487 return sizeof(uint64_t);
488 default:
489 break;
490 }
491 return 0;
492 }
493
494 static boolean
495 virgl_is_vertex_format_supported(struct pipe_screen *screen,
496 enum pipe_format format)
497 {
498 struct virgl_screen *vscreen = virgl_screen(screen);
499 const struct util_format_description *format_desc;
500 int i;
501
502 format_desc = util_format_description(format);
503 if (!format_desc)
504 return FALSE;
505
506 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
507 int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
508 int big = vformat / 32;
509 int small = vformat % 32;
510 if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
511 return FALSE;
512 return TRUE;
513 }
514
515 /* Find the first non-VOID channel. */
516 for (i = 0; i < 4; i++) {
517 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
518 break;
519 }
520 }
521
522 if (i == 4)
523 return FALSE;
524
525 if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
526 return FALSE;
527
528 if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
529 return FALSE;
530 return TRUE;
531 }
532
533 /**
534 * Query format support for creating a texture, drawing surface, etc.
535 * \param format the format to test
536 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
537 */
538 static boolean
539 virgl_is_format_supported( struct pipe_screen *screen,
540 enum pipe_format format,
541 enum pipe_texture_target target,
542 unsigned sample_count,
543 unsigned storage_sample_count,
544 unsigned bind)
545 {
546 struct virgl_screen *vscreen = virgl_screen(screen);
547 const struct util_format_description *format_desc;
548 int i;
549
550 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
551 return false;
552
553 assert(target == PIPE_BUFFER ||
554 target == PIPE_TEXTURE_1D ||
555 target == PIPE_TEXTURE_1D_ARRAY ||
556 target == PIPE_TEXTURE_2D ||
557 target == PIPE_TEXTURE_2D_ARRAY ||
558 target == PIPE_TEXTURE_RECT ||
559 target == PIPE_TEXTURE_3D ||
560 target == PIPE_TEXTURE_CUBE ||
561 target == PIPE_TEXTURE_CUBE_ARRAY);
562
563 format_desc = util_format_description(format);
564 if (!format_desc)
565 return FALSE;
566
567 if (util_format_is_intensity(format))
568 return FALSE;
569
570 if (sample_count > 1) {
571 if (!vscreen->caps.caps.v1.bset.texture_multisample)
572 return FALSE;
573
574 if (bind & PIPE_BIND_SHADER_IMAGE) {
575 if (sample_count > vscreen->caps.caps.v2.max_image_samples)
576 return FALSE;
577 }
578
579 if (sample_count > vscreen->caps.caps.v1.max_samples)
580 return FALSE;
581 }
582
583 if (bind & PIPE_BIND_VERTEX_BUFFER) {
584 return virgl_is_vertex_format_supported(screen, format);
585 }
586
587 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
588 if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
589 format == PIPE_FORMAT_R32G32B32_SINT ||
590 format == PIPE_FORMAT_R32G32B32_UINT) &&
591 target != PIPE_BUFFER)
592 return FALSE;
593
594 if (bind & PIPE_BIND_RENDER_TARGET) {
595 /* For ARB_framebuffer_no_attachments. */
596 if (format == PIPE_FORMAT_NONE)
597 return TRUE;
598
599 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
600 return FALSE;
601
602 /*
603 * Although possible, it is unnatural to render into compressed or YUV
604 * surfaces. So disable these here to avoid going into weird paths
605 * inside the state trackers.
606 */
607 if (format_desc->block.width != 1 ||
608 format_desc->block.height != 1)
609 return FALSE;
610
611 {
612 int big = format / 32;
613 int small = format % 32;
614 if (!(vscreen->caps.caps.v1.render.bitmask[big] & (1 << small)))
615 return FALSE;
616 }
617 }
618
619 if (bind & PIPE_BIND_DEPTH_STENCIL) {
620 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
621 return FALSE;
622 }
623
624 /*
625 * All other operations (sampling, transfer, etc).
626 */
627
628 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
629 goto out_lookup;
630 }
631 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
632 goto out_lookup;
633 }
634 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
635 goto out_lookup;
636 }
637
638 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
639 goto out_lookup;
640 } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
641 goto out_lookup;
642 }
643
644 /* Find the first non-VOID channel. */
645 for (i = 0; i < 4; i++) {
646 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
647 break;
648 }
649 }
650
651 if (i == 4)
652 return FALSE;
653
654 /* no L4A4 */
655 if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
656 return FALSE;
657
658 out_lookup:
659 {
660 int big = format / 32;
661 int small = format % 32;
662 if (!(vscreen->caps.caps.v1.sampler.bitmask[big] & (1 << small)))
663 return FALSE;
664 }
665 /*
666 * Everything else should be supported by u_format.
667 */
668 return TRUE;
669 }
670
671 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
672 struct pipe_resource *res,
673 unsigned level, unsigned layer,
674 void *winsys_drawable_handle, struct pipe_box *sub_box)
675 {
676 struct virgl_screen *vscreen = virgl_screen(screen);
677 struct virgl_winsys *vws = vscreen->vws;
678 struct virgl_resource *vres = virgl_resource(res);
679
680 if (vws->flush_frontbuffer)
681 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
682 sub_box);
683 }
684
685 static void virgl_fence_reference(struct pipe_screen *screen,
686 struct pipe_fence_handle **ptr,
687 struct pipe_fence_handle *fence)
688 {
689 struct virgl_screen *vscreen = virgl_screen(screen);
690 struct virgl_winsys *vws = vscreen->vws;
691
692 vws->fence_reference(vws, ptr, fence);
693 }
694
695 static boolean virgl_fence_finish(struct pipe_screen *screen,
696 struct pipe_context *ctx,
697 struct pipe_fence_handle *fence,
698 uint64_t timeout)
699 {
700 struct virgl_screen *vscreen = virgl_screen(screen);
701 struct virgl_winsys *vws = vscreen->vws;
702
703 return vws->fence_wait(vws, fence, timeout);
704 }
705
706 static uint64_t
707 virgl_get_timestamp(struct pipe_screen *_screen)
708 {
709 return os_time_get_nano();
710 }
711
712 static void
713 virgl_destroy_screen(struct pipe_screen *screen)
714 {
715 struct virgl_screen *vscreen = virgl_screen(screen);
716 struct virgl_winsys *vws = vscreen->vws;
717
718 slab_destroy_parent(&vscreen->texture_transfer_pool);
719
720 if (vws)
721 vws->destroy(vws);
722 FREE(vscreen);
723 }
724
725 struct pipe_screen *
726 virgl_create_screen(struct virgl_winsys *vws)
727 {
728 struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
729
730 if (!screen)
731 return NULL;
732
733 screen->vws = vws;
734 screen->base.get_name = virgl_get_name;
735 screen->base.get_vendor = virgl_get_vendor;
736 screen->base.get_param = virgl_get_param;
737 screen->base.get_shader_param = virgl_get_shader_param;
738 screen->base.get_compute_param = virgl_get_compute_param;
739 screen->base.get_paramf = virgl_get_paramf;
740 screen->base.is_format_supported = virgl_is_format_supported;
741 screen->base.destroy = virgl_destroy_screen;
742 screen->base.context_create = virgl_context_create;
743 screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
744 screen->base.get_timestamp = virgl_get_timestamp;
745 screen->base.fence_reference = virgl_fence_reference;
746 //screen->base.fence_signalled = virgl_fence_signalled;
747 screen->base.fence_finish = virgl_fence_finish;
748
749 virgl_init_screen_resource_functions(&screen->base);
750
751 vws->get_caps(vws, &screen->caps);
752
753 screen->refcnt = 1;
754
755 slab_create_parent(&screen->texture_transfer_pool, sizeof(struct virgl_transfer), 16);
756
757 return &screen->base;
758 }