2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "util/u_memory.h"
24 #include "util/format/u_format.h"
25 #include "util/format/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/os_time.h"
30 #include "util/xmlconfig.h"
31 #include "pipe/p_defines.h"
32 #include "pipe/p_screen.h"
34 #include "tgsi/tgsi_exec.h"
36 #include "virgl_screen.h"
37 #include "virgl_resource.h"
38 #include "virgl_public.h"
39 #include "virgl_context.h"
40 #include "virgl_protocol.h"
43 static const struct debug_named_value debug_options
[] = {
44 { "verbose", VIRGL_DEBUG_VERBOSE
, NULL
},
45 { "tgsi", VIRGL_DEBUG_TGSI
, NULL
},
46 { "emubgra", VIRGL_DEBUG_EMULATE_BGRA
, "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
47 { "bgraswz", VIRGL_DEBUG_BGRA_DEST_SWIZZLE
, "Enable tweak to swizzle emulated BGRA on GLES hosts" },
48 { "sync", VIRGL_DEBUG_SYNC
, "Sync after every flush" },
49 { "xfer", VIRGL_DEBUG_XFER
, "Do not optimize for transfers" },
52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug
, "VIRGL_DEBUG", debug_options
, 0)
55 virgl_get_vendor(struct pipe_screen
*screen
)
62 virgl_get_name(struct pipe_screen
*screen
)
68 virgl_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
70 struct virgl_screen
*vscreen
= virgl_screen(screen
);
72 case PIPE_CAP_NPOT_TEXTURES
:
74 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
75 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
76 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
78 case PIPE_CAP_ANISOTROPIC_FILTER
:
80 case PIPE_CAP_POINT_SPRITE
:
82 case PIPE_CAP_MAX_RENDER_TARGETS
:
83 return vscreen
->caps
.caps
.v1
.max_render_targets
;
84 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
85 return vscreen
->caps
.caps
.v1
.max_dual_source_render_targets
;
86 case PIPE_CAP_OCCLUSION_QUERY
:
87 return vscreen
->caps
.caps
.v1
.bset
.occlusion_query
;
88 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
90 return vscreen
->caps
.caps
.v1
.bset
.mirror_clamp
;
91 case PIPE_CAP_TEXTURE_SWIZZLE
:
93 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
94 if (vscreen
->caps
.caps
.v2
.max_texture_2d_size
)
95 return vscreen
->caps
.caps
.v2
.max_texture_2d_size
;
97 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
98 if (vscreen
->caps
.caps
.v2
.max_texture_3d_size
)
99 return 1 + util_logbase2(vscreen
->caps
.caps
.v2
.max_texture_3d_size
);
100 return 9; /* 256 x 256 x 256 */
101 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
102 if (vscreen
->caps
.caps
.v2
.max_texture_cube_size
)
103 return 1 + util_logbase2(vscreen
->caps
.caps
.v2
.max_texture_cube_size
);
104 return 13; /* 4K x 4K */
105 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
107 case PIPE_CAP_INDEP_BLEND_ENABLE
:
108 return vscreen
->caps
.caps
.v1
.bset
.indep_blend_enable
;
109 case PIPE_CAP_INDEP_BLEND_FUNC
:
110 return vscreen
->caps
.caps
.v1
.bset
.indep_blend_func
;
111 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
112 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
113 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
115 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
116 return vscreen
->caps
.caps
.v1
.bset
.fragment_coord_conventions
;
117 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
118 if (vscreen
->caps
.caps
.v1
.bset
.depth_clip_disable
)
120 if (vscreen
->caps
.caps
.v2
.host_feature_check_version
>= 3)
123 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
124 return vscreen
->caps
.caps
.v1
.max_streamout_buffers
;
125 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
128 case PIPE_CAP_PRIMITIVE_RESTART
:
129 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
130 return vscreen
->caps
.caps
.v1
.bset
.primitive_restart
;
131 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
132 return vscreen
->caps
.caps
.v1
.bset
.shader_stencil_export
;
133 case PIPE_CAP_TGSI_INSTANCEID
:
134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
137 return vscreen
->caps
.caps
.v1
.bset
.seamless_cube_map
;
138 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
139 return vscreen
->caps
.caps
.v1
.bset
.seamless_cube_map_per_texture
;
140 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
141 return vscreen
->caps
.caps
.v1
.max_texture_array_layers
;
142 case PIPE_CAP_MIN_TEXEL_OFFSET
:
143 return vscreen
->caps
.caps
.v2
.min_texel_offset
;
144 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
145 return vscreen
->caps
.caps
.v2
.min_texture_gather_offset
;
146 case PIPE_CAP_MAX_TEXEL_OFFSET
:
147 return vscreen
->caps
.caps
.v2
.max_texel_offset
;
148 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
149 return vscreen
->caps
.caps
.v2
.max_texture_gather_offset
;
150 case PIPE_CAP_CONDITIONAL_RENDER
:
151 return vscreen
->caps
.caps
.v1
.bset
.conditional_render
;
152 case PIPE_CAP_TEXTURE_BARRIER
:
153 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
;
154 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
156 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
157 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
158 return vscreen
->caps
.caps
.v1
.bset
.color_clamping
;
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
160 return (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FBO_MIXED_COLOR_FORMATS
) ||
161 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 1);
162 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
163 return vscreen
->caps
.caps
.v1
.glsl_level
;
164 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
165 return MIN2(vscreen
->caps
.caps
.v1
.glsl_level
, 140);
166 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
167 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
169 case PIPE_CAP_COMPUTE
:
170 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
;
171 case PIPE_CAP_USER_VERTEX_BUFFERS
:
173 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
174 return vscreen
->caps
.caps
.v2
.uniform_buffer_offset_alignment
;
175 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
176 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
177 return vscreen
->caps
.caps
.v1
.bset
.streamout_pause_resume
;
178 case PIPE_CAP_START_INSTANCE
:
179 return vscreen
->caps
.caps
.v1
.bset
.start_instance
;
180 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
181 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
182 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
183 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
184 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
186 case PIPE_CAP_QUERY_TIMESTAMP
:
188 case PIPE_CAP_QUERY_TIME_ELAPSED
:
190 case PIPE_CAP_TGSI_TEXCOORD
:
192 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
193 return VIRGL_MAP_BUFFER_ALIGNMENT
;
194 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
195 return vscreen
->caps
.caps
.v1
.max_tbo_size
> 0;
196 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
197 return vscreen
->caps
.caps
.v2
.texture_buffer_offset_alignment
;
198 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
200 case PIPE_CAP_CUBE_MAP_ARRAY
:
201 return vscreen
->caps
.caps
.v1
.bset
.cube_map_array
;
202 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
203 return vscreen
->caps
.caps
.v1
.bset
.texture_multisample
;
204 case PIPE_CAP_MAX_VIEWPORTS
:
205 return vscreen
->caps
.caps
.v1
.max_viewports
;
206 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
207 return vscreen
->caps
.caps
.v1
.max_tbo_size
;
208 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
209 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
210 case PIPE_CAP_ENDIANNESS
:
212 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
213 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
215 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
217 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
218 return vscreen
->caps
.caps
.v2
.max_geom_output_vertices
;
219 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
220 return vscreen
->caps
.caps
.v2
.max_geom_total_output_components
;
221 case PIPE_CAP_TEXTURE_QUERY_LOD
:
222 return vscreen
->caps
.caps
.v1
.bset
.texture_query_lod
;
223 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
224 return vscreen
->caps
.caps
.v1
.max_texture_gather_components
;
225 case PIPE_CAP_DRAW_INDIRECT
:
226 return vscreen
->caps
.caps
.v1
.bset
.has_indirect_draw
;
227 case PIPE_CAP_SAMPLE_SHADING
:
228 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
229 return vscreen
->caps
.caps
.v1
.bset
.has_sample_shading
;
230 case PIPE_CAP_CULL_DISTANCE
:
231 return vscreen
->caps
.caps
.v1
.bset
.has_cull
;
232 case PIPE_CAP_MAX_VERTEX_STREAMS
:
233 return ((vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TRANSFORM_FEEDBACK3
) ||
234 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 2)) ? 4 : 1;
235 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
236 return vscreen
->caps
.caps
.v1
.bset
.conditional_render_inverted
;
237 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
238 return vscreen
->caps
.caps
.v1
.bset
.derivative_control
;
239 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
240 return vscreen
->caps
.caps
.v1
.bset
.polygon_offset_clamp
;
241 case PIPE_CAP_QUERY_SO_OVERFLOW
:
242 return vscreen
->caps
.caps
.v1
.bset
.transform_feedback_overflow_query
;
243 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
244 return vscreen
->caps
.caps
.v2
.shader_buffer_offset_alignment
;
245 case PIPE_CAP_DOUBLES
:
246 return vscreen
->caps
.caps
.v1
.bset
.has_fp64
||
247 (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FAKE_FP64
);
248 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
249 return vscreen
->caps
.caps
.v2
.max_shader_patch_varyings
;
250 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
251 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_VIEW
;
252 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
253 return vscreen
->caps
.caps
.v2
.max_vertex_attrib_stride
;
254 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
255 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COPY_IMAGE
;
256 case PIPE_CAP_TGSI_TXQS
:
257 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TXQS
;
258 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
259 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_FB_NO_ATTACH
;
260 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
261 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_ROBUST_BUFFER_ACCESS
;
262 case PIPE_CAP_FBFETCH
:
263 return (vscreen
->caps
.caps
.v2
.capability_bits
&
264 VIRGL_CAP_TGSI_FBFETCH
) ? 1 : 0;
265 case PIPE_CAP_BLEND_EQUATION_ADVANCED
:
266 return vscreen
->caps
.caps
.v2
.capability_bits_v2
& VIRGL_CAP_V2_BLEND_EQUATION
;
267 case PIPE_CAP_TGSI_CLOCK
:
268 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SHADER_CLOCK
;
269 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
270 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TGSI_COMPONENTS
;
271 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
272 return vscreen
->caps
.caps
.v2
.max_combined_shader_buffers
;
273 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
274 return vscreen
->caps
.caps
.v2
.max_combined_atomic_counters
;
275 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
276 return vscreen
->caps
.caps
.v2
.max_combined_atomic_counter_buffers
;
277 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
278 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
279 return 1; /* TODO: need to introduce a hw-cap for this */
280 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
281 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_QBO
;
282 case PIPE_CAP_MAX_VARYINGS
:
283 if (vscreen
->caps
.caps
.v1
.glsl_level
< 150)
284 return vscreen
->caps
.caps
.v2
.max_vertex_attribs
;
286 case PIPE_CAP_FAKE_SW_MSAA
:
287 /* If the host supports only one sample (e.g., if it is using softpipe),
288 * fake multisampling to able to advertise higher GL versions. */
289 return (vscreen
->caps
.caps
.v1
.max_samples
== 1) ? 1 : 0;
290 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
291 return !!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MULTI_DRAW_INDIRECT
);
292 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
293 return !!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_PARAMS
);
294 case PIPE_CAP_TEXTURE_GATHER_SM5
:
295 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
296 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
297 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
298 case PIPE_CAP_VERTEXID_NOBASE
:
299 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
300 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
301 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
302 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
303 case PIPE_CAP_SHAREABLE_SHADERS
:
304 case PIPE_CAP_DRAW_PARAMETERS
:
305 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
306 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
307 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
308 case PIPE_CAP_INVALIDATE_BUFFER
:
309 case PIPE_CAP_GENERATE_MIPMAP
:
310 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
311 case PIPE_CAP_STRING_MARKER
:
312 case PIPE_CAP_QUERY_MEMORY_INFO
:
313 case PIPE_CAP_PCI_GROUP
:
314 case PIPE_CAP_PCI_BUS
:
315 case PIPE_CAP_PCI_DEVICE
:
316 case PIPE_CAP_PCI_FUNCTION
:
317 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
318 case PIPE_CAP_TGSI_VOTE
:
319 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
320 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
321 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
322 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
323 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
324 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
326 case PIPE_CAP_INT64_DIVMOD
:
327 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
328 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
329 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
330 case PIPE_CAP_TGSI_BALLOT
:
331 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
332 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
333 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
334 case PIPE_CAP_POST_DEPTH_COVERAGE
:
335 case PIPE_CAP_BINDLESS_TEXTURE
:
336 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
337 case PIPE_CAP_MEMOBJ
:
338 case PIPE_CAP_LOAD_CONSTBUF
:
339 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
340 case PIPE_CAP_TILE_RASTER_ORDER
:
341 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
342 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
343 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
344 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
345 case PIPE_CAP_FENCE_SIGNAL
:
346 case PIPE_CAP_CONSTBUF0_FLAGS
:
347 case PIPE_CAP_PACKED_UNIFORMS
:
348 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
349 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
350 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
351 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
352 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
353 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
354 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
355 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
357 case PIPE_CAP_CLEAR_TEXTURE
:
358 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_CLEAR_TEXTURE
;
359 case PIPE_CAP_CLIP_HALFZ
:
360 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_CLIP_HALFZ
;
361 case PIPE_CAP_MAX_GS_INVOCATIONS
:
363 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
365 case PIPE_CAP_VENDOR_ID
:
367 case PIPE_CAP_DEVICE_ID
:
369 case PIPE_CAP_ACCELERATED
:
372 case PIPE_CAP_VIDEO_MEMORY
:
374 case PIPE_CAP_NATIVE_FENCE_FD
:
375 return vscreen
->vws
->supports_fences
;
376 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
:
377 return (vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SRGB_WRITE_CONTROL
) ||
378 (vscreen
->caps
.caps
.v2
.host_feature_check_version
< 1);
379 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
:
380 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_INPUT_ADDR
;
382 return u_pipe_screen_get_param_defaults(screen
, param
);
387 virgl_get_shader_param(struct pipe_screen
*screen
,
388 enum pipe_shader_type shader
,
389 enum pipe_shader_cap param
)
391 struct virgl_screen
*vscreen
= virgl_screen(screen
);
393 if ((shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
) &&
394 !vscreen
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
397 if (shader
== PIPE_SHADER_COMPUTE
&&
398 !(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
))
403 case PIPE_SHADER_FRAGMENT
:
404 case PIPE_SHADER_VERTEX
:
405 case PIPE_SHADER_GEOMETRY
:
406 case PIPE_SHADER_TESS_CTRL
:
407 case PIPE_SHADER_TESS_EVAL
:
408 case PIPE_SHADER_COMPUTE
:
410 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
411 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
412 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
413 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
415 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
416 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
417 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
419 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
420 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
421 return vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_INDIRECT_INPUT_ADDR
;
422 case PIPE_SHADER_CAP_MAX_INPUTS
:
423 if (vscreen
->caps
.caps
.v1
.glsl_level
< 150)
424 return vscreen
->caps
.caps
.v2
.max_vertex_attribs
;
425 return (shader
== PIPE_SHADER_VERTEX
||
426 shader
== PIPE_SHADER_GEOMETRY
) ? vscreen
->caps
.caps
.v2
.max_vertex_attribs
: 32;
427 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
428 if (shader
== PIPE_SHADER_FRAGMENT
)
429 return vscreen
->caps
.caps
.v1
.max_render_targets
;
430 return vscreen
->caps
.caps
.v2
.max_vertex_outputs
;
431 // case PIPE_SHADER_CAP_MAX_CONSTS:
433 case PIPE_SHADER_CAP_MAX_TEMPS
:
435 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
436 return vscreen
->caps
.caps
.v1
.max_uniform_blocks
;
437 // case PIPE_SHADER_CAP_MAX_ADDRS:
439 case PIPE_SHADER_CAP_SUBROUTINES
:
441 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
443 case PIPE_SHADER_CAP_INTEGERS
:
444 return vscreen
->caps
.caps
.v1
.glsl_level
>= 130;
445 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
447 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
448 return 4096 * sizeof(float[4]);
449 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
450 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
451 return vscreen
->caps
.caps
.v2
.max_shader_buffer_frag_compute
;
453 return vscreen
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
454 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
455 if (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
)
456 return vscreen
->caps
.caps
.v2
.max_shader_image_frag_compute
;
458 return vscreen
->caps
.caps
.v2
.max_shader_image_other_stages
;
459 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
460 return (1 << PIPE_SHADER_IR_TGSI
);
461 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
462 return vscreen
->caps
.caps
.v2
.max_atomic_counters
[shader
];
463 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
464 return vscreen
->caps
.caps
.v2
.max_atomic_counter_buffers
[shader
];
465 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
466 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
467 case PIPE_SHADER_CAP_INT64_ATOMICS
:
468 case PIPE_SHADER_CAP_FP16
:
469 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
470 case PIPE_SHADER_CAP_INT16
:
471 case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS
:
482 virgl_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
484 struct virgl_screen
*vscreen
= virgl_screen(screen
);
486 case PIPE_CAPF_MAX_LINE_WIDTH
:
487 return vscreen
->caps
.caps
.v2
.max_aliased_line_width
;
488 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
489 return vscreen
->caps
.caps
.v2
.max_smooth_line_width
;
490 case PIPE_CAPF_MAX_POINT_WIDTH
:
491 return vscreen
->caps
.caps
.v2
.max_aliased_point_size
;
492 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
493 return vscreen
->caps
.caps
.v2
.max_smooth_point_size
;
494 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
496 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
497 return vscreen
->caps
.caps
.v2
.max_texture_lod_bias
;
498 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
499 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
500 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
503 /* should only get here on unhandled cases */
504 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
509 virgl_get_compute_param(struct pipe_screen
*screen
,
510 enum pipe_shader_ir ir_type
,
511 enum pipe_compute_cap param
,
514 struct virgl_screen
*vscreen
= virgl_screen(screen
);
515 if (!(vscreen
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COMPUTE_SHADER
))
518 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
520 uint64_t *grid_size
= ret
;
521 grid_size
[0] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[0];
522 grid_size
[1] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[1];
523 grid_size
[2] = vscreen
->caps
.caps
.v2
.max_compute_grid_size
[2];
525 return 3 * sizeof(uint64_t) ;
526 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
528 uint64_t *block_size
= ret
;
529 block_size
[0] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[0];
530 block_size
[1] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[1];
531 block_size
[2] = vscreen
->caps
.caps
.v2
.max_compute_block_size
[2];
533 return 3 * sizeof(uint64_t);
534 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
536 uint64_t *max_threads_per_block
= ret
;
537 *max_threads_per_block
= vscreen
->caps
.caps
.v2
.max_compute_work_group_invocations
;
539 return sizeof(uint64_t);
540 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
542 uint64_t *max_local_size
= ret
;
543 /* Value reported by the closed source driver. */
544 *max_local_size
= vscreen
->caps
.caps
.v2
.max_compute_shared_memory_size
;
546 return sizeof(uint64_t);
554 has_format_bit(struct virgl_supported_format_mask
*mask
,
555 enum virgl_formats fmt
)
557 assert(fmt
< VIRGL_FORMAT_MAX
);
558 unsigned val
= (unsigned)fmt
;
559 unsigned idx
= val
/ 32;
560 unsigned bit
= val
% 32;
561 assert(idx
< ARRAY_SIZE(mask
->bitmask
));
562 return (mask
->bitmask
[idx
] & (1u << bit
)) != 0;
566 virgl_has_readback_format(struct pipe_screen
*screen
,
567 enum virgl_formats fmt
)
569 struct virgl_screen
*vscreen
= virgl_screen(screen
);
570 return has_format_bit(&vscreen
->caps
.caps
.v2
.supported_readback_formats
,
575 virgl_is_vertex_format_supported(struct pipe_screen
*screen
,
576 enum pipe_format format
)
578 struct virgl_screen
*vscreen
= virgl_screen(screen
);
579 const struct util_format_description
*format_desc
;
582 format_desc
= util_format_description(format
);
586 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
587 int vformat
= VIRGL_FORMAT_R11G11B10_FLOAT
;
588 int big
= vformat
/ 32;
589 int small
= vformat
% 32;
590 if (!(vscreen
->caps
.caps
.v1
.vertexbuffer
.bitmask
[big
] & (1 << small
)))
595 /* Find the first non-VOID channel. */
596 for (i
= 0; i
< 4; i
++) {
597 if (format_desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
605 if (format_desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
608 if (format_desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FIXED
)
614 virgl_format_check_bitmask(enum pipe_format format
,
615 uint32_t bitmask
[16],
616 bool may_emulate_bgra
)
618 enum virgl_formats vformat
= pipe_to_virgl_format(format
);
619 int big
= vformat
/ 32;
620 int small
= vformat
% 32;
621 if ((bitmask
[big
] & (1 << small
)))
624 /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
625 * emulate it by using a swizzled RGBx */
626 if (may_emulate_bgra
) {
627 if (format
== PIPE_FORMAT_B8G8R8A8_SRGB
)
628 format
= PIPE_FORMAT_R8G8B8A8_SRGB
;
629 else if (format
== PIPE_FORMAT_B8G8R8X8_SRGB
)
630 format
= PIPE_FORMAT_R8G8B8X8_SRGB
;
635 vformat
= pipe_to_virgl_format(format
);
637 small
= vformat
% 32;
638 if (bitmask
[big
] & (1 << small
))
645 * Query format support for creating a texture, drawing surface, etc.
646 * \param format the format to test
647 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
650 virgl_is_format_supported( struct pipe_screen
*screen
,
651 enum pipe_format format
,
652 enum pipe_texture_target target
,
653 unsigned sample_count
,
654 unsigned storage_sample_count
,
657 struct virgl_screen
*vscreen
= virgl_screen(screen
);
658 const struct util_format_description
*format_desc
;
661 union virgl_caps
*caps
= &vscreen
->caps
.caps
;
662 boolean may_emulate_bgra
= (caps
->v2
.capability_bits
&
663 VIRGL_CAP_APP_TWEAK_SUPPORT
) &&
664 vscreen
->tweak_gles_emulate_bgra
;
666 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
669 if (!util_is_power_of_two_or_zero(sample_count
))
672 assert(target
== PIPE_BUFFER
||
673 target
== PIPE_TEXTURE_1D
||
674 target
== PIPE_TEXTURE_1D_ARRAY
||
675 target
== PIPE_TEXTURE_2D
||
676 target
== PIPE_TEXTURE_2D_ARRAY
||
677 target
== PIPE_TEXTURE_RECT
||
678 target
== PIPE_TEXTURE_3D
||
679 target
== PIPE_TEXTURE_CUBE
||
680 target
== PIPE_TEXTURE_CUBE_ARRAY
);
682 format_desc
= util_format_description(format
);
686 if (util_format_is_intensity(format
))
689 if (sample_count
> 1) {
690 if (!caps
->v1
.bset
.texture_multisample
)
693 if (bind
& PIPE_BIND_SHADER_IMAGE
) {
694 if (sample_count
> caps
->v2
.max_image_samples
)
698 if (sample_count
> caps
->v1
.max_samples
)
702 if (bind
& PIPE_BIND_VERTEX_BUFFER
) {
703 return virgl_is_vertex_format_supported(screen
, format
);
706 if (util_format_is_compressed(format
) && target
== PIPE_BUFFER
)
709 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
710 if ((format
== PIPE_FORMAT_R32G32B32_FLOAT
||
711 format
== PIPE_FORMAT_R32G32B32_SINT
||
712 format
== PIPE_FORMAT_R32G32B32_UINT
) &&
713 target
!= PIPE_BUFFER
)
716 if ((format_desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
||
717 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
||
718 format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) &&
719 target
== PIPE_TEXTURE_3D
)
723 if (bind
& PIPE_BIND_RENDER_TARGET
) {
724 /* For ARB_framebuffer_no_attachments. */
725 if (format
== PIPE_FORMAT_NONE
)
728 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
732 * Although possible, it is unnatural to render into compressed or YUV
733 * surfaces. So disable these here to avoid going into weird paths
734 * inside gallium frontends.
736 if (format_desc
->block
.width
!= 1 ||
737 format_desc
->block
.height
!= 1)
740 if (!virgl_format_check_bitmask(format
,
741 caps
->v1
.render
.bitmask
,
746 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
747 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
751 if (bind
& PIPE_BIND_SCANOUT
) {
752 if (!virgl_format_check_bitmask(format
, caps
->v2
.scanout
.bitmask
, false))
757 * All other operations (sampling, transfer, etc).
760 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
763 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
766 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
769 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
) {
773 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
775 } else if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
779 /* Find the first non-VOID channel. */
780 for (i
= 0; i
< 4; i
++) {
781 if (format_desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
790 if (format_desc
->nr_channels
< 4 && format_desc
->channel
[i
].size
== 4)
794 return virgl_format_check_bitmask(format
,
795 caps
->v1
.sampler
.bitmask
,
799 static void virgl_flush_frontbuffer(struct pipe_screen
*screen
,
800 struct pipe_resource
*res
,
801 unsigned level
, unsigned layer
,
802 void *winsys_drawable_handle
, struct pipe_box
*sub_box
)
804 struct virgl_screen
*vscreen
= virgl_screen(screen
);
805 struct virgl_winsys
*vws
= vscreen
->vws
;
806 struct virgl_resource
*vres
= virgl_resource(res
);
808 if (vws
->flush_frontbuffer
)
809 vws
->flush_frontbuffer(vws
, vres
->hw_res
, level
, layer
, winsys_drawable_handle
,
813 static void virgl_fence_reference(struct pipe_screen
*screen
,
814 struct pipe_fence_handle
**ptr
,
815 struct pipe_fence_handle
*fence
)
817 struct virgl_screen
*vscreen
= virgl_screen(screen
);
818 struct virgl_winsys
*vws
= vscreen
->vws
;
820 vws
->fence_reference(vws
, ptr
, fence
);
823 static bool virgl_fence_finish(struct pipe_screen
*screen
,
824 struct pipe_context
*ctx
,
825 struct pipe_fence_handle
*fence
,
828 struct virgl_screen
*vscreen
= virgl_screen(screen
);
829 struct virgl_winsys
*vws
= vscreen
->vws
;
831 return vws
->fence_wait(vws
, fence
, timeout
);
834 static int virgl_fence_get_fd(struct pipe_screen
*screen
,
835 struct pipe_fence_handle
*fence
)
837 struct virgl_screen
*vscreen
= virgl_screen(screen
);
838 struct virgl_winsys
*vws
= vscreen
->vws
;
840 return vws
->fence_get_fd(vws
, fence
);
844 virgl_get_timestamp(struct pipe_screen
*_screen
)
846 return os_time_get_nano();
850 virgl_destroy_screen(struct pipe_screen
*screen
)
852 struct virgl_screen
*vscreen
= virgl_screen(screen
);
853 struct virgl_winsys
*vws
= vscreen
->vws
;
855 slab_destroy_parent(&vscreen
->transfer_pool
);
863 fixup_formats(union virgl_caps
*caps
, struct virgl_supported_format_mask
*mask
)
865 const size_t size
= ARRAY_SIZE(mask
->bitmask
);
866 for (int i
= 0; i
< size
; ++i
) {
867 if (mask
->bitmask
[i
] != 0)
868 return; /* we got some formats, we definately have a new protocol */
871 /* old protocol used; fall back to considering all sampleable formats valid
874 for (int i
= 0; i
< size
; ++i
)
875 mask
->bitmask
[i
] = caps
->v1
.sampler
.bitmask
[i
];
879 virgl_create_screen(struct virgl_winsys
*vws
, const struct pipe_screen_config
*config
)
881 struct virgl_screen
*screen
= CALLOC_STRUCT(virgl_screen
);
883 const char *VIRGL_GLES_EMULATE_BGRA
= "gles_emulate_bgra";
884 const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE
= "gles_apply_bgra_dest_swizzle";
885 const char *VIRGL_GLES_SAMPLES_PASSED_VALUE
= "gles_samples_passed_value";
890 virgl_debug
= debug_get_option_virgl_debug();
892 if (config
&& config
->options
) {
893 screen
->tweak_gles_emulate_bgra
=
894 driQueryOptionb(config
->options
, VIRGL_GLES_EMULATE_BGRA
);
895 screen
->tweak_gles_apply_bgra_dest_swizzle
=
896 driQueryOptionb(config
->options
, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE
);
897 screen
->tweak_gles_tf3_value
=
898 driQueryOptioni(config
->options
, VIRGL_GLES_SAMPLES_PASSED_VALUE
);
901 screen
->tweak_gles_emulate_bgra
|= !!(virgl_debug
& VIRGL_DEBUG_EMULATE_BGRA
);
902 screen
->tweak_gles_apply_bgra_dest_swizzle
|= !!(virgl_debug
& VIRGL_DEBUG_BGRA_DEST_SWIZZLE
);
905 screen
->base
.get_name
= virgl_get_name
;
906 screen
->base
.get_vendor
= virgl_get_vendor
;
907 screen
->base
.get_param
= virgl_get_param
;
908 screen
->base
.get_shader_param
= virgl_get_shader_param
;
909 screen
->base
.get_compute_param
= virgl_get_compute_param
;
910 screen
->base
.get_paramf
= virgl_get_paramf
;
911 screen
->base
.is_format_supported
= virgl_is_format_supported
;
912 screen
->base
.destroy
= virgl_destroy_screen
;
913 screen
->base
.context_create
= virgl_context_create
;
914 screen
->base
.flush_frontbuffer
= virgl_flush_frontbuffer
;
915 screen
->base
.get_timestamp
= virgl_get_timestamp
;
916 screen
->base
.fence_reference
= virgl_fence_reference
;
917 //screen->base.fence_signalled = virgl_fence_signalled;
918 screen
->base
.fence_finish
= virgl_fence_finish
;
919 screen
->base
.fence_get_fd
= virgl_fence_get_fd
;
921 virgl_init_screen_resource_functions(&screen
->base
);
923 vws
->get_caps(vws
, &screen
->caps
);
924 fixup_formats(&screen
->caps
.caps
,
925 &screen
->caps
.caps
.v2
.supported_readback_formats
);
926 fixup_formats(&screen
->caps
.caps
, &screen
->caps
.caps
.v2
.scanout
);
930 slab_create_parent(&screen
->transfer_pool
, sizeof(struct virgl_transfer
), 16);
932 return &screen
->base
;