virgl: enable robustness if the host exposes it
[mesa.git] / src / gallium / drivers / virgl / virgl_screen.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "util/u_memory.h"
24 #include "util/u_format.h"
25 #include "util/u_format_s3tc.h"
26 #include "util/u_video.h"
27 #include "util/os_time.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30
31 #include "tgsi/tgsi_exec.h"
32
33 #include "virgl_screen.h"
34 #include "virgl_resource.h"
35 #include "virgl_public.h"
36 #include "virgl_context.h"
37
38 #define SP_MAX_TEXTURE_2D_LEVELS 15 /* 16K x 16K */
39 #define SP_MAX_TEXTURE_3D_LEVELS 9 /* 512 x 512 x 512 */
40 #define SP_MAX_TEXTURE_CUBE_LEVELS 13 /* 4K x 4K */
41
42 static const char *
43 virgl_get_vendor(struct pipe_screen *screen)
44 {
45 return "Red Hat";
46 }
47
48
49 static const char *
50 virgl_get_name(struct pipe_screen *screen)
51 {
52 return "virgl";
53 }
54
55 static int
56 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
57 {
58 struct virgl_screen *vscreen = virgl_screen(screen);
59 switch (param) {
60 case PIPE_CAP_NPOT_TEXTURES:
61 return 1;
62 case PIPE_CAP_SM3:
63 return 1;
64 case PIPE_CAP_ANISOTROPIC_FILTER:
65 return 1;
66 case PIPE_CAP_POINT_SPRITE:
67 return 1;
68 case PIPE_CAP_MAX_RENDER_TARGETS:
69 return vscreen->caps.caps.v1.max_render_targets;
70 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
71 return vscreen->caps.caps.v1.max_dual_source_render_targets;
72 case PIPE_CAP_OCCLUSION_QUERY:
73 return vscreen->caps.caps.v1.bset.occlusion_query;
74 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
75 return vscreen->caps.caps.v1.bset.mirror_clamp;
76 case PIPE_CAP_TEXTURE_SWIZZLE:
77 return 1;
78 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
79 return SP_MAX_TEXTURE_2D_LEVELS;
80 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
81 return SP_MAX_TEXTURE_3D_LEVELS;
82 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
83 return SP_MAX_TEXTURE_CUBE_LEVELS;
84 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
85 return 1;
86 case PIPE_CAP_INDEP_BLEND_ENABLE:
87 return vscreen->caps.caps.v1.bset.indep_blend_enable;
88 case PIPE_CAP_INDEP_BLEND_FUNC:
89 return vscreen->caps.caps.v1.bset.indep_blend_func;
90 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
91 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
92 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
93 return 1;
94 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
95 return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
96 case PIPE_CAP_DEPTH_CLIP_DISABLE:
97 return vscreen->caps.caps.v1.bset.depth_clip_disable;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return vscreen->caps.caps.v1.max_streamout_buffers;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 16*4;
103 case PIPE_CAP_PRIMITIVE_RESTART:
104 return vscreen->caps.caps.v1.bset.primitive_restart;
105 case PIPE_CAP_SHADER_STENCIL_EXPORT:
106 return vscreen->caps.caps.v1.bset.shader_stencil_export;
107 case PIPE_CAP_TGSI_INSTANCEID:
108 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
109 return 1;
110 case PIPE_CAP_SEAMLESS_CUBE_MAP:
111 return vscreen->caps.caps.v1.bset.seamless_cube_map;
112 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
113 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
114 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
115 return vscreen->caps.caps.v1.max_texture_array_layers;
116 case PIPE_CAP_MIN_TEXEL_OFFSET:
117 return vscreen->caps.caps.v2.min_texel_offset;
118 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
119 return vscreen->caps.caps.v2.min_texture_gather_offset;
120 case PIPE_CAP_MAX_TEXEL_OFFSET:
121 return vscreen->caps.caps.v2.max_texel_offset;
122 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
123 return vscreen->caps.caps.v2.max_texture_gather_offset;
124 case PIPE_CAP_CONDITIONAL_RENDER:
125 return vscreen->caps.caps.v1.bset.conditional_render;
126 case PIPE_CAP_TEXTURE_BARRIER:
127 return 0;
128 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
129 return 1;
130 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
131 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
132 return vscreen->caps.caps.v1.bset.color_clamping;
133 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
134 return 1;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return vscreen->caps.caps.v1.glsl_level;
137 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
138 return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
139 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
140 return 0;
141 case PIPE_CAP_COMPUTE:
142 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
143 case PIPE_CAP_USER_VERTEX_BUFFERS:
144 return 0;
145 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
146 return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
147 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
148 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
149 return vscreen->caps.caps.v1.bset.streamout_pause_resume;
150 case PIPE_CAP_START_INSTANCE:
151 return vscreen->caps.caps.v1.bset.start_instance;
152 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
153 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
154 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
155 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
156 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
157 return 0;
158 case PIPE_CAP_QUERY_TIMESTAMP:
159 return 1;
160 case PIPE_CAP_QUERY_TIME_ELAPSED:
161 return 0;
162 case PIPE_CAP_TGSI_TEXCOORD:
163 return 0;
164 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
165 return VIRGL_MAP_BUFFER_ALIGNMENT;
166 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
167 return vscreen->caps.caps.v1.max_tbo_size > 0;
168 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
169 return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
170 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
171 return 0;
172 case PIPE_CAP_CUBE_MAP_ARRAY:
173 return vscreen->caps.caps.v1.bset.cube_map_array;
174 case PIPE_CAP_TEXTURE_MULTISAMPLE:
175 return vscreen->caps.caps.v1.bset.texture_multisample;
176 case PIPE_CAP_MAX_VIEWPORTS:
177 return vscreen->caps.caps.v1.max_viewports;
178 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
179 return vscreen->caps.caps.v1.max_tbo_size;
180 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
181 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
182 case PIPE_CAP_ENDIANNESS:
183 return 0;
184 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
185 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
186 return 1;
187 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
188 return 0;
189 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
190 return vscreen->caps.caps.v2.max_geom_output_vertices;
191 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
192 return vscreen->caps.caps.v2.max_geom_total_output_components;
193 case PIPE_CAP_TEXTURE_QUERY_LOD:
194 return vscreen->caps.caps.v1.bset.texture_query_lod;
195 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
196 return vscreen->caps.caps.v1.max_texture_gather_components;
197 case PIPE_CAP_DRAW_INDIRECT:
198 return vscreen->caps.caps.v1.bset.has_indirect_draw;
199 case PIPE_CAP_SAMPLE_SHADING:
200 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
201 return vscreen->caps.caps.v1.bset.has_sample_shading;
202 case PIPE_CAP_CULL_DISTANCE:
203 return vscreen->caps.caps.v1.bset.has_cull;
204 case PIPE_CAP_MAX_VERTEX_STREAMS:
205 return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1;
206 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
207 return vscreen->caps.caps.v1.bset.conditional_render_inverted;
208 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
209 return vscreen->caps.caps.v1.bset.derivative_control;
210 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
211 return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
212 case PIPE_CAP_QUERY_SO_OVERFLOW:
213 return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
214 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
215 return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
216 case PIPE_CAP_DOUBLES:
217 return vscreen->caps.caps.v1.bset.has_fp64;
218 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
219 return vscreen->caps.caps.v2.max_shader_patch_varyings;
220 case PIPE_CAP_SAMPLER_VIEW_TARGET:
221 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
222 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
223 return vscreen->caps.caps.v2.max_vertex_attrib_stride;
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
225 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
226 case PIPE_CAP_TGSI_TXQS:
227 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
228 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
229 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
230 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
231 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
232 case PIPE_CAP_TEXTURE_GATHER_SM5:
233 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
234 case PIPE_CAP_FAKE_SW_MSAA:
235 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
236 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
237 case PIPE_CAP_MULTI_DRAW_INDIRECT:
238 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
239 case PIPE_CAP_CLIP_HALFZ:
240 case PIPE_CAP_VERTEXID_NOBASE:
241 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
242 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
243 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
244 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
245 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
246 case PIPE_CAP_DEPTH_BOUNDS_TEST:
247 case PIPE_CAP_SHAREABLE_SHADERS:
248 case PIPE_CAP_CLEAR_TEXTURE:
249 case PIPE_CAP_DRAW_PARAMETERS:
250 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
251 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
252 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
253 case PIPE_CAP_INVALIDATE_BUFFER:
254 case PIPE_CAP_GENERATE_MIPMAP:
255 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
256 case PIPE_CAP_QUERY_BUFFER_OBJECT:
257 case PIPE_CAP_STRING_MARKER:
258 case PIPE_CAP_QUERY_MEMORY_INFO:
259 case PIPE_CAP_PCI_GROUP:
260 case PIPE_CAP_PCI_BUS:
261 case PIPE_CAP_PCI_DEVICE:
262 case PIPE_CAP_PCI_FUNCTION:
263 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
264 case PIPE_CAP_TGSI_VOTE:
265 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
266 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
267 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
268 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
269 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
270 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
271 case PIPE_CAP_TGSI_FS_FBFETCH:
272 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
273 case PIPE_CAP_INT64:
274 case PIPE_CAP_INT64_DIVMOD:
275 case PIPE_CAP_TGSI_TEX_TXF_LZ:
276 case PIPE_CAP_TGSI_CLOCK:
277 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
278 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
279 case PIPE_CAP_TGSI_BALLOT:
280 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
281 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
282 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
283 case PIPE_CAP_POST_DEPTH_COVERAGE:
284 case PIPE_CAP_BINDLESS_TEXTURE:
285 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
286 case PIPE_CAP_MEMOBJ:
287 case PIPE_CAP_LOAD_CONSTBUF:
288 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
289 case PIPE_CAP_TILE_RASTER_ORDER:
290 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
291 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
292 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
293 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
294 case PIPE_CAP_FENCE_SIGNAL:
295 case PIPE_CAP_CONSTBUF0_FLAGS:
296 case PIPE_CAP_PACKED_UNIFORMS:
297 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
298 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
299 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
300 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
301 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
302 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
303 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
304 return 0;
305 case PIPE_CAP_VENDOR_ID:
306 return 0x1af4;
307 case PIPE_CAP_DEVICE_ID:
308 return 0x1010;
309 case PIPE_CAP_ACCELERATED:
310 return 1;
311 case PIPE_CAP_UMA:
312 case PIPE_CAP_VIDEO_MEMORY:
313 return 0;
314 case PIPE_CAP_NATIVE_FENCE_FD:
315 return 0;
316 }
317 /* should only get here on unhandled cases */
318 debug_printf("Unexpected PIPE_CAP %d query\n", param);
319 return 0;
320 }
321
322 static int
323 virgl_get_shader_param(struct pipe_screen *screen,
324 enum pipe_shader_type shader,
325 enum pipe_shader_cap param)
326 {
327 struct virgl_screen *vscreen = virgl_screen(screen);
328
329 if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
330 !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
331 return 0;
332
333 if (shader == PIPE_SHADER_COMPUTE &&
334 !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
335 return 0;
336
337 switch(shader)
338 {
339 case PIPE_SHADER_FRAGMENT:
340 case PIPE_SHADER_VERTEX:
341 case PIPE_SHADER_GEOMETRY:
342 case PIPE_SHADER_TESS_CTRL:
343 case PIPE_SHADER_TESS_EVAL:
344 case PIPE_SHADER_COMPUTE:
345 switch (param) {
346 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
347 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
348 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
349 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
350 return INT_MAX;
351 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
352 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
353 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
354 return 1;
355 case PIPE_SHADER_CAP_MAX_INPUTS:
356 if (vscreen->caps.caps.v1.glsl_level < 150)
357 return vscreen->caps.caps.v2.max_vertex_attribs;
358 return (shader == PIPE_SHADER_VERTEX ||
359 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
360 case PIPE_SHADER_CAP_MAX_OUTPUTS:
361 if (shader == PIPE_SHADER_FRAGMENT)
362 return vscreen->caps.caps.v1.max_render_targets;
363 return vscreen->caps.caps.v2.max_vertex_outputs;
364 // case PIPE_SHADER_CAP_MAX_CONSTS:
365 // return 4096;
366 case PIPE_SHADER_CAP_MAX_TEMPS:
367 return 256;
368 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
369 return vscreen->caps.caps.v1.max_uniform_blocks;
370 // case PIPE_SHADER_CAP_MAX_ADDRS:
371 // return 1;
372 case PIPE_SHADER_CAP_SUBROUTINES:
373 return 1;
374 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
375 return 16;
376 case PIPE_SHADER_CAP_INTEGERS:
377 return vscreen->caps.caps.v1.glsl_level >= 130;
378 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
379 return 32;
380 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
381 return 4096 * sizeof(float[4]);
382 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
383 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
384 return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
385 else
386 return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
387 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
388 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
389 return vscreen->caps.caps.v2.max_shader_image_frag_compute;
390 else
391 return vscreen->caps.caps.v2.max_shader_image_other_stages;
392 case PIPE_SHADER_CAP_SUPPORTED_IRS:
393 return (1 << PIPE_SHADER_IR_TGSI);
394 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
395 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
396 case PIPE_SHADER_CAP_INT64_ATOMICS:
397 case PIPE_SHADER_CAP_FP16:
398 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
399 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
400 return 0;
401 case PIPE_SHADER_CAP_SCALAR_ISA:
402 return 1;
403 default:
404 return 0;
405 }
406 default:
407 return 0;
408 }
409 }
410
411 static float
412 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
413 {
414 struct virgl_screen *vscreen = virgl_screen(screen);
415 switch (param) {
416 case PIPE_CAPF_MAX_LINE_WIDTH:
417 return vscreen->caps.caps.v2.max_aliased_line_width;
418 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
419 return vscreen->caps.caps.v2.max_smooth_line_width;
420 case PIPE_CAPF_MAX_POINT_WIDTH:
421 return vscreen->caps.caps.v2.max_aliased_point_size;
422 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
423 return vscreen->caps.caps.v2.max_smooth_point_size;
424 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
425 return 16.0;
426 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
427 return vscreen->caps.caps.v2.max_texture_lod_bias;
428 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
429 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
430 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
431 return 0.0f;
432 }
433 /* should only get here on unhandled cases */
434 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
435 return 0.0;
436 }
437
438 static int
439 virgl_get_compute_param(struct pipe_screen *screen,
440 enum pipe_shader_ir ir_type,
441 enum pipe_compute_cap param,
442 void *ret)
443 {
444 struct virgl_screen *vscreen = virgl_screen(screen);
445 if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
446 return 0;
447 switch (param) {
448 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
449 if (ret) {
450 uint64_t *grid_size = ret;
451 grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
452 grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
453 grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
454 }
455 return 3 * sizeof(uint64_t) ;
456 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
457 if (ret) {
458 uint64_t *block_size = ret;
459 block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
460 block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
461 block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
462 }
463 return 3 * sizeof(uint64_t);
464 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
465 if (ret) {
466 uint64_t *max_threads_per_block = ret;
467 *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
468 }
469 return sizeof(uint64_t);
470 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
471 if (ret) {
472 uint64_t *max_local_size = ret;
473 /* Value reported by the closed source driver. */
474 *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
475 }
476 return sizeof(uint64_t);
477 default:
478 break;
479 }
480 return 0;
481 }
482
483 static boolean
484 virgl_is_vertex_format_supported(struct pipe_screen *screen,
485 enum pipe_format format)
486 {
487 struct virgl_screen *vscreen = virgl_screen(screen);
488 const struct util_format_description *format_desc;
489 int i;
490
491 format_desc = util_format_description(format);
492 if (!format_desc)
493 return FALSE;
494
495 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
496 int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
497 int big = vformat / 32;
498 int small = vformat % 32;
499 if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
500 return FALSE;
501 return TRUE;
502 }
503
504 /* Find the first non-VOID channel. */
505 for (i = 0; i < 4; i++) {
506 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
507 break;
508 }
509 }
510
511 if (i == 4)
512 return FALSE;
513
514 if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
515 return FALSE;
516
517 if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
518 return FALSE;
519 return TRUE;
520 }
521
522 /**
523 * Query format support for creating a texture, drawing surface, etc.
524 * \param format the format to test
525 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
526 */
527 static boolean
528 virgl_is_format_supported( struct pipe_screen *screen,
529 enum pipe_format format,
530 enum pipe_texture_target target,
531 unsigned sample_count,
532 unsigned storage_sample_count,
533 unsigned bind)
534 {
535 struct virgl_screen *vscreen = virgl_screen(screen);
536 const struct util_format_description *format_desc;
537 int i;
538
539 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
540 return false;
541
542 assert(target == PIPE_BUFFER ||
543 target == PIPE_TEXTURE_1D ||
544 target == PIPE_TEXTURE_1D_ARRAY ||
545 target == PIPE_TEXTURE_2D ||
546 target == PIPE_TEXTURE_2D_ARRAY ||
547 target == PIPE_TEXTURE_RECT ||
548 target == PIPE_TEXTURE_3D ||
549 target == PIPE_TEXTURE_CUBE ||
550 target == PIPE_TEXTURE_CUBE_ARRAY);
551
552 format_desc = util_format_description(format);
553 if (!format_desc)
554 return FALSE;
555
556 if (util_format_is_intensity(format))
557 return FALSE;
558
559 if (sample_count > 1) {
560 if (!vscreen->caps.caps.v1.bset.texture_multisample)
561 return FALSE;
562
563 if (bind & PIPE_BIND_SHADER_IMAGE) {
564 if (sample_count > vscreen->caps.caps.v2.max_image_samples)
565 return FALSE;
566 }
567
568 if (sample_count > vscreen->caps.caps.v1.max_samples)
569 return FALSE;
570 }
571
572 if (bind & PIPE_BIND_VERTEX_BUFFER) {
573 return virgl_is_vertex_format_supported(screen, format);
574 }
575
576 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
577 if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
578 format == PIPE_FORMAT_R32G32B32_SINT ||
579 format == PIPE_FORMAT_R32G32B32_UINT) &&
580 target != PIPE_BUFFER)
581 return FALSE;
582
583 if (bind & PIPE_BIND_RENDER_TARGET) {
584 /* For ARB_framebuffer_no_attachments. */
585 if (format == PIPE_FORMAT_NONE)
586 return TRUE;
587
588 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
589 return FALSE;
590
591 /*
592 * Although possible, it is unnatural to render into compressed or YUV
593 * surfaces. So disable these here to avoid going into weird paths
594 * inside the state trackers.
595 */
596 if (format_desc->block.width != 1 ||
597 format_desc->block.height != 1)
598 return FALSE;
599
600 {
601 int big = format / 32;
602 int small = format % 32;
603 if (!(vscreen->caps.caps.v1.render.bitmask[big] & (1 << small)))
604 return FALSE;
605 }
606 }
607
608 if (bind & PIPE_BIND_DEPTH_STENCIL) {
609 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
610 return FALSE;
611 }
612
613 /*
614 * All other operations (sampling, transfer, etc).
615 */
616
617 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
618 goto out_lookup;
619 }
620 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
621 goto out_lookup;
622 }
623 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
624 goto out_lookup;
625 }
626
627 if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
628 goto out_lookup;
629 } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
630 goto out_lookup;
631 }
632
633 /* Find the first non-VOID channel. */
634 for (i = 0; i < 4; i++) {
635 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
636 break;
637 }
638 }
639
640 if (i == 4)
641 return FALSE;
642
643 /* no L4A4 */
644 if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
645 return FALSE;
646
647 out_lookup:
648 {
649 int big = format / 32;
650 int small = format % 32;
651 if (!(vscreen->caps.caps.v1.sampler.bitmask[big] & (1 << small)))
652 return FALSE;
653 }
654 /*
655 * Everything else should be supported by u_format.
656 */
657 return TRUE;
658 }
659
660 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
661 struct pipe_resource *res,
662 unsigned level, unsigned layer,
663 void *winsys_drawable_handle, struct pipe_box *sub_box)
664 {
665 struct virgl_screen *vscreen = virgl_screen(screen);
666 struct virgl_winsys *vws = vscreen->vws;
667 struct virgl_resource *vres = virgl_resource(res);
668
669 if (vws->flush_frontbuffer)
670 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
671 sub_box);
672 }
673
674 static void virgl_fence_reference(struct pipe_screen *screen,
675 struct pipe_fence_handle **ptr,
676 struct pipe_fence_handle *fence)
677 {
678 struct virgl_screen *vscreen = virgl_screen(screen);
679 struct virgl_winsys *vws = vscreen->vws;
680
681 vws->fence_reference(vws, ptr, fence);
682 }
683
684 static boolean virgl_fence_finish(struct pipe_screen *screen,
685 struct pipe_context *ctx,
686 struct pipe_fence_handle *fence,
687 uint64_t timeout)
688 {
689 struct virgl_screen *vscreen = virgl_screen(screen);
690 struct virgl_winsys *vws = vscreen->vws;
691
692 return vws->fence_wait(vws, fence, timeout);
693 }
694
695 static uint64_t
696 virgl_get_timestamp(struct pipe_screen *_screen)
697 {
698 return os_time_get_nano();
699 }
700
701 static void
702 virgl_destroy_screen(struct pipe_screen *screen)
703 {
704 struct virgl_screen *vscreen = virgl_screen(screen);
705 struct virgl_winsys *vws = vscreen->vws;
706
707 slab_destroy_parent(&vscreen->texture_transfer_pool);
708
709 if (vws)
710 vws->destroy(vws);
711 FREE(vscreen);
712 }
713
714 struct pipe_screen *
715 virgl_create_screen(struct virgl_winsys *vws)
716 {
717 struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
718
719 if (!screen)
720 return NULL;
721
722 screen->vws = vws;
723 screen->base.get_name = virgl_get_name;
724 screen->base.get_vendor = virgl_get_vendor;
725 screen->base.get_param = virgl_get_param;
726 screen->base.get_shader_param = virgl_get_shader_param;
727 screen->base.get_compute_param = virgl_get_compute_param;
728 screen->base.get_paramf = virgl_get_paramf;
729 screen->base.is_format_supported = virgl_is_format_supported;
730 screen->base.destroy = virgl_destroy_screen;
731 screen->base.context_create = virgl_context_create;
732 screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
733 screen->base.get_timestamp = virgl_get_timestamp;
734 screen->base.fence_reference = virgl_fence_reference;
735 //screen->base.fence_signalled = virgl_fence_signalled;
736 screen->base.fence_finish = virgl_fence_finish;
737
738 virgl_init_screen_resource_functions(&screen->base);
739
740 vws->get_caps(vws, &screen->caps);
741
742 screen->refcnt = 1;
743
744 slab_create_parent(&screen->texture_transfer_pool, sizeof(struct virgl_transfer), 16);
745
746 return &screen->base;
747 }