src/gallium/drivers/virgl/virgl_screen.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "util/u_memory.h"
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_screen.h"
  27 #include "util/u_video.h"
  28 #include "util/u_math.h"
  29 #include "util/os_time.h"
  30 #include "util/xmlconfig.h"
  31 #include "pipe/p_defines.h"
  32 #include "pipe/p_screen.h"
  33
  34 #include "tgsi/tgsi_exec.h"
  35
  36 #include "virgl_screen.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_public.h"
  39 #include "virgl_context.h"
  40 #include "virgl_protocol.h"
  41
  42 int virgl_debug = 0;
  43 static const struct debug_named_value debug_options[] = {
  44    { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
  45    { "tgsi", VIRGL_DEBUG_TGSI, NULL },
  46    { "emubgra", VIRGL_DEBUG_EMULATE_BGRA, "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
  47    { "bgraswz", VIRGL_DEBUG_BGRA_DEST_SWIZZLE, "Enable tweak to swizzle emulated BGRA on GLES hosts" },
  48    DEBUG_NAMED_VALUE_END
  49 };
  50 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
  51
  52 static const char *
  53 virgl_get_vendor(struct pipe_screen *screen)
  54 {
  55    return "Red Hat";
  56 }
  57
  58
  59 static const char *
  60 virgl_get_name(struct pipe_screen *screen)
  61 {
  62    return "virgl";
  63 }
  64
  65 static int
  66 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
  67 {
  68    struct virgl_screen *vscreen = virgl_screen(screen);
  69    switch (param) {
  70    case PIPE_CAP_NPOT_TEXTURES:
  71       return 1;
  72    case PIPE_CAP_SM3:
  73       return 1;
  74    case PIPE_CAP_ANISOTROPIC_FILTER:
  75       return 1;
  76    case PIPE_CAP_POINT_SPRITE:
  77       return 1;
  78    case PIPE_CAP_MAX_RENDER_TARGETS:
  79       return vscreen->caps.caps.v1.max_render_targets;
  80    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  81       return vscreen->caps.caps.v1.max_dual_source_render_targets;
  82    case PIPE_CAP_OCCLUSION_QUERY:
  83       return vscreen->caps.caps.v1.bset.occlusion_query;
  84    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  85    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  86       return vscreen->caps.caps.v1.bset.mirror_clamp;
  87    case PIPE_CAP_TEXTURE_SWIZZLE:
  88       return 1;
  89    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  90       if (vscreen->caps.caps.v2.max_texture_2d_size)
  91          return vscreen->caps.caps.v2.max_texture_2d_size;
  92       return 16384;
  93    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  94       if (vscreen->caps.caps.v2.max_texture_3d_size)
  95          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
  96       return 9; /* 256 x 256 x 256 */
  97    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  98       if (vscreen->caps.caps.v2.max_texture_cube_size)
  99          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
 100       return 13; /* 4K x 4K */
 101    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 102       return 1;
 103    case PIPE_CAP_INDEP_BLEND_ENABLE:
 104       return vscreen->caps.caps.v1.bset.indep_blend_enable;
 105    case PIPE_CAP_INDEP_BLEND_FUNC:
 106       return vscreen->caps.caps.v1.bset.indep_blend_func;
 107    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 108    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 109    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110       return 1;
 111    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 112       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
 113    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 114       return vscreen->caps.caps.v1.bset.depth_clip_disable;
 115    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 116       return vscreen->caps.caps.v1.max_streamout_buffers;
 117    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119       return 16*4;
 120    case PIPE_CAP_PRIMITIVE_RESTART:
 121       return vscreen->caps.caps.v1.bset.primitive_restart;
 122    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 123       return vscreen->caps.caps.v1.bset.shader_stencil_export;
 124    case PIPE_CAP_TGSI_INSTANCEID:
 125    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 126       return 1;
 127    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 128       return vscreen->caps.caps.v1.bset.seamless_cube_map;
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 130       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
 131    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 132       return vscreen->caps.caps.v1.max_texture_array_layers;
 133    case PIPE_CAP_MIN_TEXEL_OFFSET:
 134       return vscreen->caps.caps.v2.min_texel_offset;
 135    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 136       return vscreen->caps.caps.v2.min_texture_gather_offset;
 137    case PIPE_CAP_MAX_TEXEL_OFFSET:
 138       return vscreen->caps.caps.v2.max_texel_offset;
 139    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 140       return vscreen->caps.caps.v2.max_texture_gather_offset;
 141    case PIPE_CAP_CONDITIONAL_RENDER:
 142       return vscreen->caps.caps.v1.bset.conditional_render;
 143    case PIPE_CAP_TEXTURE_BARRIER:
 144       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
 145    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 146       return 1;
 147    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 148    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 149       return vscreen->caps.caps.v1.bset.color_clamping;
 150    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 151       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
 152             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 153    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 154       return vscreen->caps.caps.v1.glsl_level;
 155    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 156       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
 157    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 158    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 159       return 0;
 160    case PIPE_CAP_COMPUTE:
 161       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
 162    case PIPE_CAP_USER_VERTEX_BUFFERS:
 163       return 0;
 164    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 165       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
 166    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 167    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 168       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
 169    case PIPE_CAP_START_INSTANCE:
 170       return vscreen->caps.caps.v1.bset.start_instance;
 171    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 172    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 173    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 174    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 175    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 176       return 0;
 177    case PIPE_CAP_QUERY_TIMESTAMP:
 178       return 1;
 179    case PIPE_CAP_QUERY_TIME_ELAPSED:
 180       return 1;
 181    case PIPE_CAP_TGSI_TEXCOORD:
 182       return 0;
 183    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 184       return VIRGL_MAP_BUFFER_ALIGNMENT;
 185    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 186       return vscreen->caps.caps.v1.max_tbo_size > 0;
 187    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 188       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
 189    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 190       return 0;
 191    case PIPE_CAP_CUBE_MAP_ARRAY:
 192       return vscreen->caps.caps.v1.bset.cube_map_array;
 193    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 194       return vscreen->caps.caps.v1.bset.texture_multisample;
 195    case PIPE_CAP_MAX_VIEWPORTS:
 196       return vscreen->caps.caps.v1.max_viewports;
 197    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198       return vscreen->caps.caps.v1.max_tbo_size;
 199    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 200    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 201    case PIPE_CAP_ENDIANNESS:
 202       return 0;
 203    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 204    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 205       return 1;
 206    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 207       return 0;
 208    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 209       return vscreen->caps.caps.v2.max_geom_output_vertices;
 210    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 211       return vscreen->caps.caps.v2.max_geom_total_output_components;
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213       return vscreen->caps.caps.v1.bset.texture_query_lod;
 214    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 215       return vscreen->caps.caps.v1.max_texture_gather_components;
 216    case PIPE_CAP_DRAW_INDIRECT:
 217       return vscreen->caps.caps.v1.bset.has_indirect_draw;
 218    case PIPE_CAP_SAMPLE_SHADING:
 219    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 220       return vscreen->caps.caps.v1.bset.has_sample_shading;
 221    case PIPE_CAP_CULL_DISTANCE:
 222       return vscreen->caps.caps.v1.bset.has_cull;
 223    case PIPE_CAP_MAX_VERTEX_STREAMS:
 224       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
 225               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
 226    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 227       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
 228    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 229       return vscreen->caps.caps.v1.bset.derivative_control;
 230    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 231       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
 232    case PIPE_CAP_QUERY_SO_OVERFLOW:
 233       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
 234    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 235       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
 236    case PIPE_CAP_DOUBLES:
 237       return vscreen->caps.caps.v1.bset.has_fp64 ||
 238             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
 239    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 240       return vscreen->caps.caps.v2.max_shader_patch_varyings;
 241    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 242       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
 243    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 244       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
 245    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 246       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
 247    case PIPE_CAP_TGSI_TXQS:
 248       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
 249    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 250       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
 251    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 252       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
 253    case PIPE_CAP_FBFETCH:
 254       return (vscreen->caps.caps.v2.capability_bits &
 255               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
 256    case PIPE_CAP_TGSI_CLOCK:
 257       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
 258    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 259       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
 260    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 261       return vscreen->caps.caps.v2.max_combined_shader_buffers;
 262    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 263       return vscreen->caps.caps.v2.max_combined_atomic_counters;
 264    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 265       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
 266    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 267    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 268       return 1; /* TODO: need to introduce a hw-cap for this */
 269    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 270       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
 271    case PIPE_CAP_MAX_VARYINGS:
 272       if (vscreen->caps.caps.v1.glsl_level < 150)
 273          return vscreen->caps.caps.v2.max_vertex_attribs;
 274       return 32;
 275    case PIPE_CAP_FAKE_SW_MSAA:
 276       /* If the host supports only one sample (e.g., if it is using softpipe),
 277        * fake multisampling to able to advertise higher GL versions. */
 278       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
 279    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 280       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
 281    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 282       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
 283    case PIPE_CAP_TEXTURE_GATHER_SM5:
 284    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 285    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 286    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 287    case PIPE_CAP_VERTEXID_NOBASE:
 288    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 289    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 290    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 291    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 292    case PIPE_CAP_SHAREABLE_SHADERS:
 293    case PIPE_CAP_CLEAR_TEXTURE:
 294    case PIPE_CAP_DRAW_PARAMETERS:
 295    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 296    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 297    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 298    case PIPE_CAP_INVALIDATE_BUFFER:
 299    case PIPE_CAP_GENERATE_MIPMAP:
 300    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 301    case PIPE_CAP_STRING_MARKER:
 302    case PIPE_CAP_QUERY_MEMORY_INFO:
 303    case PIPE_CAP_PCI_GROUP:
 304    case PIPE_CAP_PCI_BUS:
 305    case PIPE_CAP_PCI_DEVICE:
 306    case PIPE_CAP_PCI_FUNCTION:
 307    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 308    case PIPE_CAP_TGSI_VOTE:
 309    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 310    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 311    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 312    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 313    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 314    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 315    case PIPE_CAP_INT64:
 316    case PIPE_CAP_INT64_DIVMOD:
 317    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 318    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 319    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 320    case PIPE_CAP_TGSI_BALLOT:
 321    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 322    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 323    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 324    case PIPE_CAP_POST_DEPTH_COVERAGE:
 325    case PIPE_CAP_BINDLESS_TEXTURE:
 326    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 327    case PIPE_CAP_MEMOBJ:
 328    case PIPE_CAP_LOAD_CONSTBUF:
 329    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 330    case PIPE_CAP_TILE_RASTER_ORDER:
 331    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 332    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 333    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 334    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 335    case PIPE_CAP_FENCE_SIGNAL:
 336    case PIPE_CAP_CONSTBUF0_FLAGS:
 337    case PIPE_CAP_PACKED_UNIFORMS:
 338    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 339    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 340    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 341    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 342    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 343    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 344    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 345    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 346       return 0;
 347    case PIPE_CAP_CLIP_HALFZ:
 348       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
 349    case PIPE_CAP_MAX_GS_INVOCATIONS:
 350       return 32;
 351    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 352       return 1 << 27;
 353    case PIPE_CAP_VENDOR_ID:
 354       return 0x1af4;
 355    case PIPE_CAP_DEVICE_ID:
 356       return 0x1010;
 357    case PIPE_CAP_ACCELERATED:
 358       return 1;
 359    case PIPE_CAP_UMA:
 360    case PIPE_CAP_VIDEO_MEMORY:
 361       return 0;
 362    case PIPE_CAP_NATIVE_FENCE_FD:
 363       return vscreen->vws->supports_fences;
 364    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 365       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
 366             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 367    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 368       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 369    default:
 370       return u_pipe_screen_get_param_defaults(screen, param);
 371    }
 372 }
 373
 374 static int
 375 virgl_get_shader_param(struct pipe_screen *screen,
 376                        enum pipe_shader_type shader,
 377                        enum pipe_shader_cap param)
 378 {
 379    struct virgl_screen *vscreen = virgl_screen(screen);
 380
 381    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
 382        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
 383       return 0;
 384
 385    if (shader == PIPE_SHADER_COMPUTE &&
 386        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 387      return 0;
 388
 389    switch(shader)
 390    {
 391    case PIPE_SHADER_FRAGMENT:
 392    case PIPE_SHADER_VERTEX:
 393    case PIPE_SHADER_GEOMETRY:
 394    case PIPE_SHADER_TESS_CTRL:
 395    case PIPE_SHADER_TESS_EVAL:
 396    case PIPE_SHADER_COMPUTE:
 397       switch (param) {
 398       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 399       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 400       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 401       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 402          return INT_MAX;
 403       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 404       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 405       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 406          return 1;
 407       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 408       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 409          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 410       case PIPE_SHADER_CAP_MAX_INPUTS:
 411          if (vscreen->caps.caps.v1.glsl_level < 150)
 412             return vscreen->caps.caps.v2.max_vertex_attribs;
 413          return (shader == PIPE_SHADER_VERTEX ||
 414                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
 415       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 416          if (shader == PIPE_SHADER_FRAGMENT)
 417             return vscreen->caps.caps.v1.max_render_targets;
 418          return vscreen->caps.caps.v2.max_vertex_outputs;
 419      // case PIPE_SHADER_CAP_MAX_CONSTS:
 420      //    return 4096;
 421       case PIPE_SHADER_CAP_MAX_TEMPS:
 422          return 256;
 423       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 424          return vscreen->caps.caps.v1.max_uniform_blocks;
 425     //  case PIPE_SHADER_CAP_MAX_ADDRS:
 426      //    return 1;
 427       case PIPE_SHADER_CAP_SUBROUTINES:
 428          return 1;
 429       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 430             return 16;
 431       case PIPE_SHADER_CAP_INTEGERS:
 432          return vscreen->caps.caps.v1.glsl_level >= 130;
 433       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 434          return 32;
 435       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 436          return 4096 * sizeof(float[4]);
 437       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 438          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 439             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
 440          else
 441             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
 442       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 443          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 444             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
 445          else
 446             return vscreen->caps.caps.v2.max_shader_image_other_stages;
 447       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 448          return (1 << PIPE_SHADER_IR_TGSI);
 449       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 450          return vscreen->caps.caps.v2.max_atomic_counters[shader];
 451       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 452          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
 453       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 454       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 455       case PIPE_SHADER_CAP_INT64_ATOMICS:
 456       case PIPE_SHADER_CAP_FP16:
 457          return 0;
 458       case PIPE_SHADER_CAP_SCALAR_ISA:
 459          return 1;
 460       default:
 461          return 0;
 462       }
 463    default:
 464       return 0;
 465    }
 466 }
 467
 468 static float
 469 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 470 {
 471    struct virgl_screen *vscreen = virgl_screen(screen);
 472    switch (param) {
 473    case PIPE_CAPF_MAX_LINE_WIDTH:
 474       return vscreen->caps.caps.v2.max_aliased_line_width;
 475    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 476       return vscreen->caps.caps.v2.max_smooth_line_width;
 477    case PIPE_CAPF_MAX_POINT_WIDTH:
 478       return vscreen->caps.caps.v2.max_aliased_point_size;
 479    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 480       return vscreen->caps.caps.v2.max_smooth_point_size;
 481    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 482       return 16.0;
 483    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 484       return vscreen->caps.caps.v2.max_texture_lod_bias;
 485    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 486    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 487    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 488       return 0.0f;
 489    }
 490    /* should only get here on unhandled cases */
 491    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 492    return 0.0;
 493 }
 494
 495 static int
 496 virgl_get_compute_param(struct pipe_screen *screen,
 497                         enum pipe_shader_ir ir_type,
 498                         enum pipe_compute_cap param,
 499                         void *ret)
 500 {
 501    struct virgl_screen *vscreen = virgl_screen(screen);
 502    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 503       return 0;
 504    switch (param) {
 505    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 506       if (ret) {
 507          uint64_t *grid_size = ret;
 508          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
 509          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
 510          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
 511       }
 512       return 3 * sizeof(uint64_t) ;
 513    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 514       if (ret) {
 515          uint64_t *block_size = ret;
 516          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
 517          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
 518          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
 519       }
 520       return 3 * sizeof(uint64_t);
 521    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 522       if (ret) {
 523          uint64_t *max_threads_per_block = ret;
 524          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
 525       }
 526       return sizeof(uint64_t);
 527    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 528       if (ret) {
 529          uint64_t *max_local_size = ret;
 530          /* Value reported by the closed source driver. */
 531          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
 532       }
 533       return sizeof(uint64_t);
 534    default:
 535       break;
 536    }
 537    return 0;
 538 }
 539
 540 static boolean
 541 has_format_bit(struct virgl_supported_format_mask *mask,
 542                enum virgl_formats fmt)
 543 {
 544    assert(fmt < VIRGL_FORMAT_MAX);
 545    unsigned val = (unsigned)fmt;
 546    unsigned idx = val / 32;
 547    unsigned bit = val % 32;
 548    assert(idx < ARRAY_SIZE(mask->bitmask));
 549    return (mask->bitmask[val / 32] & (1u << bit)) != 0;
 550 }
 551
 552 boolean
 553 virgl_has_readback_format(struct pipe_screen *screen,
 554                           enum virgl_formats fmt)
 555 {
 556    struct virgl_screen *vscreen = virgl_screen(screen);
 557    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
 558                          fmt);
 559 }
 560
 561 static boolean
 562 virgl_is_vertex_format_supported(struct pipe_screen *screen,
 563                                  enum pipe_format format)
 564 {
 565    struct virgl_screen *vscreen = virgl_screen(screen);
 566    const struct util_format_description *format_desc;
 567    int i;
 568
 569    format_desc = util_format_description(format);
 570    if (!format_desc)
 571       return FALSE;
 572
 573    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 574       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
 575       int big = vformat / 32;
 576       int small = vformat % 32;
 577       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
 578          return FALSE;
 579       return TRUE;
 580    }
 581
 582    /* Find the first non-VOID channel. */
 583    for (i = 0; i < 4; i++) {
 584       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 585          break;
 586       }
 587    }
 588
 589    if (i == 4)
 590       return FALSE;
 591
 592    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 593       return FALSE;
 594
 595    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
 596       return FALSE;
 597    return TRUE;
 598 }
 599
 600 static boolean
 601 virgl_format_check_bitmask(enum pipe_format format,
 602                            uint32_t bitmask[16],
 603                            boolean may_emulate_bgra)
 604 {
 605    int big = format / 32;
 606    int small = format % 32;
 607    if ((bitmask[big] & (1 << small)))
 608       return TRUE;
 609
 610    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
 611     * emulate it by using a swizzled RGBx */
 612    if (may_emulate_bgra) {
 613       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
 614          format = PIPE_FORMAT_R8G8B8A8_SRGB;
 615       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
 616          format = PIPE_FORMAT_R8G8B8X8_SRGB;
 617       else {
 618          return FALSE;
 619       }
 620
 621       big = format / 32;
 622       small = format % 32;
 623       if (bitmask[big] & (1 << small))
 624          return TRUE;
 625    }
 626    return FALSE;
 627 }
 628
 629 /**
 630  * Query format support for creating a texture, drawing surface, etc.
 631  * \param format  the format to test
 632  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 633  */
 634 static boolean
 635 virgl_is_format_supported( struct pipe_screen *screen,
 636                                  enum pipe_format format,
 637                                  enum pipe_texture_target target,
 638                                  unsigned sample_count,
 639                                  unsigned storage_sample_count,
 640                                  unsigned bind)
 641 {
 642    struct virgl_screen *vscreen = virgl_screen(screen);
 643    const struct util_format_description *format_desc;
 644    int i;
 645
 646    boolean may_emulate_bgra = false;
 647
 648    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 649       return false;
 650
 651    assert(target == PIPE_BUFFER ||
 652           target == PIPE_TEXTURE_1D ||
 653           target == PIPE_TEXTURE_1D_ARRAY ||
 654           target == PIPE_TEXTURE_2D ||
 655           target == PIPE_TEXTURE_2D_ARRAY ||
 656           target == PIPE_TEXTURE_RECT ||
 657           target == PIPE_TEXTURE_3D ||
 658           target == PIPE_TEXTURE_CUBE ||
 659           target == PIPE_TEXTURE_CUBE_ARRAY);
 660
 661    format_desc = util_format_description(format);
 662    if (!format_desc)
 663       return FALSE;
 664
 665    if (util_format_is_intensity(format))
 666       return FALSE;
 667
 668    if (sample_count > 1) {
 669       if (!vscreen->caps.caps.v1.bset.texture_multisample)
 670          return FALSE;
 671
 672       if (bind & PIPE_BIND_SHADER_IMAGE) {
 673          if (sample_count > vscreen->caps.caps.v2.max_image_samples)
 674             return FALSE;
 675       }
 676
 677       if (sample_count > vscreen->caps.caps.v1.max_samples)
 678          return FALSE;
 679    }
 680
 681    if (bind & PIPE_BIND_VERTEX_BUFFER) {
 682       return virgl_is_vertex_format_supported(screen, format);
 683    }
 684
 685    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
 686       return FALSE;
 687
 688    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
 689    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
 690        format == PIPE_FORMAT_R32G32B32_SINT ||
 691        format == PIPE_FORMAT_R32G32B32_UINT) &&
 692        target != PIPE_BUFFER)
 693       return FALSE;
 694
 695    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
 696         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
 697         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
 698        target == PIPE_TEXTURE_3D)
 699       return FALSE;
 700
 701    may_emulate_bgra = (vscreen->caps.caps.v2.capability_bits &
 702                        VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 703                       vscreen->tweak_gles_emulate_bgra;
 704
 705    if (bind & PIPE_BIND_RENDER_TARGET) {
 706       /* For ARB_framebuffer_no_attachments. */
 707       if (format == PIPE_FORMAT_NONE)
 708          return TRUE;
 709
 710       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 711          return FALSE;
 712
 713       /*
 714        * Although possible, it is unnatural to render into compressed or YUV
 715        * surfaces. So disable these here to avoid going into weird paths
 716        * inside the state trackers.
 717        */
 718       if (format_desc->block.width != 1 ||
 719           format_desc->block.height != 1)
 720          return FALSE;
 721
 722       if (!virgl_format_check_bitmask(format,
 723                                       vscreen->caps.caps.v1.render.bitmask,
 724                                       may_emulate_bgra))
 725          return FALSE;
 726    }
 727
 728    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 729       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 730          return FALSE;
 731    }
 732
 733    /*
 734     * All other operations (sampling, transfer, etc).
 735     */
 736
 737    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 738       goto out_lookup;
 739    }
 740    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 741       goto out_lookup;
 742    }
 743    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
 744       goto out_lookup;
 745    }
 746
 747    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 748       goto out_lookup;
 749    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 750       goto out_lookup;
 751    }
 752
 753    /* Find the first non-VOID channel. */
 754    for (i = 0; i < 4; i++) {
 755       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 756          break;
 757       }
 758    }
 759
 760    if (i == 4)
 761       return FALSE;
 762
 763    /* no L4A4 */
 764    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
 765       return FALSE;
 766
 767  out_lookup:
 768    return virgl_format_check_bitmask(format,
 769                                      vscreen->caps.caps.v1.sampler.bitmask,
 770                                      may_emulate_bgra);
 771 }
 772
 773 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
 774                                       struct pipe_resource *res,
 775                                       unsigned level, unsigned layer,
 776                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
 777 {
 778    struct virgl_screen *vscreen = virgl_screen(screen);
 779    struct virgl_winsys *vws = vscreen->vws;
 780    struct virgl_resource *vres = virgl_resource(res);
 781
 782    if (vws->flush_frontbuffer)
 783       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
 784                              sub_box);
 785 }
 786
 787 static void virgl_fence_reference(struct pipe_screen *screen,
 788                                   struct pipe_fence_handle **ptr,
 789                                   struct pipe_fence_handle *fence)
 790 {
 791    struct virgl_screen *vscreen = virgl_screen(screen);
 792    struct virgl_winsys *vws = vscreen->vws;
 793
 794    vws->fence_reference(vws, ptr, fence);
 795 }
 796
 797 static boolean virgl_fence_finish(struct pipe_screen *screen,
 798                                   struct pipe_context *ctx,
 799                                   struct pipe_fence_handle *fence,
 800                                   uint64_t timeout)
 801 {
 802    struct virgl_screen *vscreen = virgl_screen(screen);
 803    struct virgl_winsys *vws = vscreen->vws;
 804
 805    return vws->fence_wait(vws, fence, timeout);
 806 }
 807
 808 static int virgl_fence_get_fd(struct pipe_screen *screen,
 809             struct pipe_fence_handle *fence)
 810 {
 811    struct virgl_screen *vscreen = virgl_screen(screen);
 812    struct virgl_winsys *vws = vscreen->vws;
 813
 814    return vws->fence_get_fd(vws, fence);
 815 }
 816
 817 static uint64_t
 818 virgl_get_timestamp(struct pipe_screen *_screen)
 819 {
 820    return os_time_get_nano();
 821 }
 822
 823 static void
 824 virgl_destroy_screen(struct pipe_screen *screen)
 825 {
 826    struct virgl_screen *vscreen = virgl_screen(screen);
 827    struct virgl_winsys *vws = vscreen->vws;
 828
 829    slab_destroy_parent(&vscreen->transfer_pool);
 830
 831    if (vws)
 832       vws->destroy(vws);
 833    FREE(vscreen);
 834 }
 835
 836 static void
 837 fixup_readback_format(union virgl_caps *caps)
 838 {
 839    const size_t size = ARRAY_SIZE(caps->v2.supported_readback_formats.bitmask);
 840    for (int i = 0; i < size; ++i) {
 841       if (caps->v2.supported_readback_formats.bitmask[i] != 0)
 842          return; /* we got some formats, we definately have a new protocol */
 843    }
 844
 845    /* old protocol used; fall back to considering all sampleable formats valid
 846     * readback-formats
 847     */
 848    for (int i = 0; i < size; ++i) {
 849       caps->v2.supported_readback_formats.bitmask[i] =
 850          caps->v1.sampler.bitmask[i];
 851    }
 852 }
 853
 854 struct pipe_screen *
 855 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
 856 {
 857    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
 858
 859    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
 860    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
 861    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
 862
 863    if (!screen)
 864       return NULL;
 865
 866    virgl_debug = debug_get_option_virgl_debug();
 867
 868    if (config && config->options) {
 869       screen->tweak_gles_emulate_bgra =
 870             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
 871       screen->tweak_gles_apply_bgra_dest_swizzle =
 872             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
 873       screen->tweak_gles_tf3_value =
 874             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
 875    }
 876
 877    screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
 878    screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
 879
 880    screen->vws = vws;
 881    screen->base.get_name = virgl_get_name;
 882    screen->base.get_vendor = virgl_get_vendor;
 883    screen->base.get_param = virgl_get_param;
 884    screen->base.get_shader_param = virgl_get_shader_param;
 885    screen->base.get_compute_param = virgl_get_compute_param;
 886    screen->base.get_paramf = virgl_get_paramf;
 887    screen->base.is_format_supported = virgl_is_format_supported;
 888    screen->base.destroy = virgl_destroy_screen;
 889    screen->base.context_create = virgl_context_create;
 890    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
 891    screen->base.get_timestamp = virgl_get_timestamp;
 892    screen->base.fence_reference = virgl_fence_reference;
 893    //screen->base.fence_signalled = virgl_fence_signalled;
 894    screen->base.fence_finish = virgl_fence_finish;
 895    screen->base.fence_get_fd = virgl_fence_get_fd;
 896
 897    virgl_init_screen_resource_functions(&screen->base);
 898
 899    vws->get_caps(vws, &screen->caps);
 900    fixup_readback_format(&screen->caps.caps);
 901
 902    screen->refcnt = 1;
 903
 904    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 905
 906    return &screen->base;
 907 }