src/gallium/drivers/zink/zink_context.c

   1 /*
   2  * Copyright 2018 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "zink_context.h"
  25
  26 #include "zink_batch.h"
  27 #include "zink_compiler.h"
  28 #include "zink_fence.h"
  29 #include "zink_framebuffer.h"
  30 #include "zink_pipeline.h"
  31 #include "zink_program.h"
  32 #include "zink_render_pass.h"
  33 #include "zink_resource.h"
  34 #include "zink_screen.h"
  35 #include "zink_state.h"
  36 #include "zink_surface.h"
  37
  38 #include "indices/u_primconvert.h"
  39 #include "util/u_blitter.h"
  40 #include "util/u_debug.h"
  41 #include "util/u_format.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45
  46 #include "nir.h"
  47
  48 #include "util/u_memory.h"
  49 #include "util/u_prim.h"
  50 #include "util/u_upload_mgr.h"
  51
  52 static void
  53 zink_context_destroy(struct pipe_context *pctx)
  54 {
  55    struct zink_context *ctx = zink_context(pctx);
  56    struct zink_screen *screen = zink_screen(pctx->screen);
  57
  58    if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS)
  59       debug_printf("vkQueueWaitIdle failed\n");
  60
  61    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i)
  62       vkFreeCommandBuffers(screen->dev, ctx->cmdpool, 1, &ctx->batches[i].cmdbuf);
  63    vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
  64
  65    util_primconvert_destroy(ctx->primconvert);
  66    u_upload_destroy(pctx->stream_uploader);
  67    slab_destroy_child(&ctx->transfer_pool);
  68    util_blitter_destroy(ctx->blitter);
  69    FREE(ctx);
  70 }
  71
  72 static VkFilter
  73 filter(enum pipe_tex_filter filter)
  74 {
  75    switch (filter) {
  76    case PIPE_TEX_FILTER_NEAREST: return VK_FILTER_NEAREST;
  77    case PIPE_TEX_FILTER_LINEAR: return VK_FILTER_LINEAR;
  78    }
  79    unreachable("unexpected filter");
  80 }
  81
  82 static VkSamplerMipmapMode
  83 sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
  84 {
  85    switch (filter) {
  86    case PIPE_TEX_MIPFILTER_NEAREST: return VK_SAMPLER_MIPMAP_MODE_NEAREST;
  87    case PIPE_TEX_MIPFILTER_LINEAR: return VK_SAMPLER_MIPMAP_MODE_LINEAR;
  88    case PIPE_TEX_MIPFILTER_NONE:
  89       unreachable("PIPE_TEX_MIPFILTER_NONE should be dealt with earlier");
  90    }
  91    unreachable("unexpected filter");
  92 }
  93
  94 static VkSamplerAddressMode
  95 sampler_address_mode(enum pipe_tex_wrap filter)
  96 {
  97    switch (filter) {
  98    case PIPE_TEX_WRAP_REPEAT: return VK_SAMPLER_ADDRESS_MODE_REPEAT;
  99    case PIPE_TEX_WRAP_CLAMP: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 100    case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE;
 101    case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
 102    case PIPE_TEX_WRAP_MIRROR_REPEAT: return VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT;
 103    case PIPE_TEX_WRAP_MIRROR_CLAMP: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 104    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE;
 105    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 106    }
 107    unreachable("unexpected wrap");
 108 }
 109
 110 static VkCompareOp
 111 compare_op(enum pipe_compare_func op)
 112 {
 113    switch (op) {
 114       case PIPE_FUNC_NEVER: return VK_COMPARE_OP_NEVER;
 115       case PIPE_FUNC_LESS: return VK_COMPARE_OP_LESS;
 116       case PIPE_FUNC_EQUAL: return VK_COMPARE_OP_EQUAL;
 117       case PIPE_FUNC_LEQUAL: return VK_COMPARE_OP_LESS_OR_EQUAL;
 118       case PIPE_FUNC_GREATER: return VK_COMPARE_OP_GREATER;
 119       case PIPE_FUNC_NOTEQUAL: return VK_COMPARE_OP_NOT_EQUAL;
 120       case PIPE_FUNC_GEQUAL: return VK_COMPARE_OP_GREATER_OR_EQUAL;
 121       case PIPE_FUNC_ALWAYS: return VK_COMPARE_OP_ALWAYS;
 122    }
 123    unreachable("unexpected compare");
 124 }
 125
 126 static void *
 127 zink_create_sampler_state(struct pipe_context *pctx,
 128                           const struct pipe_sampler_state *state)
 129 {
 130    struct zink_screen *screen = zink_screen(pctx->screen);
 131
 132    VkSamplerCreateInfo sci = {};
 133    sci.sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO;
 134    sci.magFilter = filter(state->mag_img_filter);
 135    sci.minFilter = filter(state->min_img_filter);
 136
 137    if (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 138       sci.mipmapMode = sampler_mipmap_mode(state->min_mip_filter);
 139       sci.minLod = state->min_lod;
 140       sci.maxLod = state->max_lod;
 141    } else {
 142       sci.mipmapMode = VK_SAMPLER_MIPMAP_MODE_NEAREST;
 143       sci.minLod = 0;
 144       sci.maxLod = 0;
 145    }
 146
 147    sci.addressModeU = sampler_address_mode(state->wrap_s);
 148    sci.addressModeV = sampler_address_mode(state->wrap_t);
 149    sci.addressModeW = sampler_address_mode(state->wrap_r);
 150    sci.mipLodBias = state->lod_bias;
 151
 152    if (state->compare_mode == PIPE_TEX_COMPARE_NONE)
 153       sci.compareOp = VK_COMPARE_OP_NEVER;
 154    else
 155       sci.compareOp = compare_op(state->compare_func);
 156
 157    sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO
 158    sci.unnormalizedCoordinates = !state->normalized_coords;
 159
 160    if (state->max_anisotropy > 1) {
 161       sci.maxAnisotropy = state->max_anisotropy;
 162       sci.anisotropyEnable = VK_TRUE;
 163    }
 164
 165    VkSampler sampler;
 166    VkResult err = vkCreateSampler(screen->dev, &sci, NULL, &sampler);
 167    if (err != VK_SUCCESS)
 168       return NULL;
 169
 170    return sampler;
 171 }
 172
 173 static void
 174 zink_bind_sampler_states(struct pipe_context *pctx,
 175                          enum pipe_shader_type shader,
 176                          unsigned start_slot,
 177                          unsigned num_samplers,
 178                          void **samplers)
 179 {
 180    struct zink_context *ctx = zink_context(pctx);
 181    for (unsigned i = 0; i < num_samplers; ++i)
 182       ctx->samplers[shader][start_slot + i] = (VkSampler)samplers[i];
 183 }
 184
 185 static void
 186 zink_delete_sampler_state(struct pipe_context *pctx,
 187                           void *sampler_state)
 188 {
 189    struct zink_batch *batch = zink_curr_batch(zink_context(pctx));
 190    util_dynarray_append(&batch->zombie_samplers,
 191                         VkSampler, sampler_state);
 192 }
 193
 194
 195 static VkImageViewType
 196 image_view_type(enum pipe_texture_target target)
 197 {
 198    switch (target) {
 199    case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
 200    case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
 201    case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
 202    case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
 203    case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
 204    case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
 205    case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
 206    case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D; /* not sure */
 207    default:
 208       unreachable("unexpected target");
 209    }
 210 }
 211
 212 static VkComponentSwizzle
 213 component_mapping(enum pipe_swizzle swizzle)
 214 {
 215    switch (swizzle) {
 216    case PIPE_SWIZZLE_X: return VK_COMPONENT_SWIZZLE_R;
 217    case PIPE_SWIZZLE_Y: return VK_COMPONENT_SWIZZLE_G;
 218    case PIPE_SWIZZLE_Z: return VK_COMPONENT_SWIZZLE_B;
 219    case PIPE_SWIZZLE_W: return VK_COMPONENT_SWIZZLE_A;
 220    case PIPE_SWIZZLE_0: return VK_COMPONENT_SWIZZLE_ZERO;
 221    case PIPE_SWIZZLE_1: return VK_COMPONENT_SWIZZLE_ONE;
 222    case PIPE_SWIZZLE_NONE: return VK_COMPONENT_SWIZZLE_IDENTITY; // ???
 223    default:
 224       unreachable("unexpected swizzle");
 225    }
 226 }
 227
 228 static struct pipe_sampler_view *
 229 zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
 230                          const struct pipe_sampler_view *state)
 231 {
 232    struct zink_screen *screen = zink_screen(pctx->screen);
 233    struct zink_resource *res = zink_resource(pres);
 234    struct zink_sampler_view *sampler_view = CALLOC_STRUCT(zink_sampler_view);
 235
 236    sampler_view->base = *state;
 237    sampler_view->base.texture = NULL;
 238    pipe_resource_reference(&sampler_view->base.texture, pres);
 239    sampler_view->base.reference.count = 1;
 240    sampler_view->base.context = pctx;
 241
 242    VkImageViewCreateInfo ivci = {};
 243    ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
 244    ivci.image = res->image;
 245    ivci.viewType = image_view_type(state->target);
 246    ivci.format = zink_get_format(state->format);
 247    ivci.components.r = component_mapping(state->swizzle_r);
 248    ivci.components.g = component_mapping(state->swizzle_g);
 249    ivci.components.b = component_mapping(state->swizzle_b);
 250    ivci.components.a = component_mapping(state->swizzle_a);
 251    ivci.subresourceRange.aspectMask = zink_aspect_from_format(state->format);
 252    ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
 253    ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
 254    ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
 255    ivci.subresourceRange.layerCount = state->u.tex.last_layer - state->u.tex.first_layer + 1;
 256
 257    VkResult err = vkCreateImageView(screen->dev, &ivci, NULL, &sampler_view->image_view);
 258    if (err != VK_SUCCESS) {
 259       FREE(sampler_view);
 260       return NULL;
 261    }
 262
 263    return &sampler_view->base;
 264 }
 265
 266 static void
 267 zink_sampler_view_destroy(struct pipe_context *pctx,
 268                           struct pipe_sampler_view *pview)
 269 {
 270    struct zink_sampler_view *view = zink_sampler_view(pview);
 271    vkDestroyImageView(zink_screen(pctx->screen)->dev, view->image_view, NULL);
 272    FREE(view);
 273 }
 274
 275 static void *
 276 zink_create_vs_state(struct pipe_context *pctx,
 277                      const struct pipe_shader_state *shader)
 278 {
 279    struct nir_shader *nir;
 280    if (shader->type != PIPE_SHADER_IR_NIR)
 281       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 282    else
 283       nir = (struct nir_shader *)shader->ir.nir;
 284
 285    return zink_compile_nir(zink_screen(pctx->screen), nir);
 286 }
 287
 288 static void
 289 bind_stage(struct zink_context *ctx, enum pipe_shader_type stage,
 290            struct zink_shader *shader)
 291 {
 292    assert(stage < PIPE_SHADER_COMPUTE);
 293    ctx->gfx_stages[stage] = shader;
 294    ctx->dirty |= ZINK_DIRTY_PROGRAM;
 295 }
 296
 297 static void
 298 zink_bind_vs_state(struct pipe_context *pctx,
 299                    void *cso)
 300 {
 301    bind_stage(zink_context(pctx), PIPE_SHADER_VERTEX, cso);
 302 }
 303
 304 static void
 305 zink_delete_vs_state(struct pipe_context *pctx,
 306                      void *cso)
 307 {
 308    zink_shader_free(zink_screen(pctx->screen), cso);
 309 }
 310
 311 static void *
 312 zink_create_fs_state(struct pipe_context *pctx,
 313                      const struct pipe_shader_state *shader)
 314 {
 315    struct nir_shader *nir;
 316    if (shader->type != PIPE_SHADER_IR_NIR)
 317       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 318    else
 319       nir = (struct nir_shader *)shader->ir.nir;
 320
 321    return zink_compile_nir(zink_screen(pctx->screen), nir);
 322 }
 323
 324 static void
 325 zink_bind_fs_state(struct pipe_context *pctx,
 326                    void *cso)
 327 {
 328    bind_stage(zink_context(pctx), PIPE_SHADER_FRAGMENT, cso);
 329 }
 330
 331 static void
 332 zink_delete_fs_state(struct pipe_context *pctx,
 333                      void *cso)
 334 {
 335    zink_shader_free(zink_screen(pctx->screen), cso);
 336 }
 337
 338 static void
 339 zink_set_polygon_stipple(struct pipe_context *pctx,
 340                          const struct pipe_poly_stipple *ps)
 341 {
 342 }
 343
 344 static void
 345 zink_set_vertex_buffers(struct pipe_context *pctx,
 346                         unsigned start_slot,
 347                         unsigned num_buffers,
 348                         const struct pipe_vertex_buffer *buffers)
 349 {
 350    struct zink_context *ctx = zink_context(pctx);
 351
 352    if (buffers) {
 353       for (int i = 0; i < num_buffers; ++i) {
 354          const struct pipe_vertex_buffer *vb = buffers + i;
 355          ctx->gfx_pipeline_state.bindings[start_slot + i].stride = vb->stride;
 356       }
 357    }
 358
 359    util_set_vertex_buffers_mask(ctx->buffers, &ctx->buffers_enabled_mask,
 360                                 buffers, start_slot, num_buffers);
 361 }
 362
 363 static void
 364 zink_set_viewport_states(struct pipe_context *pctx,
 365                          unsigned start_slot,
 366                          unsigned num_viewports,
 367                          const struct pipe_viewport_state *state)
 368 {
 369    struct zink_context *ctx = zink_context(pctx);
 370
 371    for (unsigned i = 0; i < num_viewports; ++i) {
 372       VkViewport viewport = {
 373          state[i].translate[0] - state[i].scale[0],
 374          state[i].translate[1] - state[i].scale[1],
 375          state[i].scale[0] * 2,
 376          state[i].scale[1] * 2,
 377          state[i].translate[2] - state[i].scale[2],
 378          state[i].translate[2] + state[i].scale[2]
 379       };
 380       ctx->viewports[start_slot + i] = viewport;
 381    }
 382    ctx->num_viewports = start_slot + num_viewports;
 383 }
 384
 385 static void
 386 zink_set_scissor_states(struct pipe_context *pctx,
 387                         unsigned start_slot, unsigned num_scissors,
 388                         const struct pipe_scissor_state *states)
 389 {
 390    struct zink_context *ctx = zink_context(pctx);
 391
 392    for (unsigned i = 0; i < num_scissors; i++) {
 393       VkRect2D scissor;
 394
 395       scissor.offset.x = states[i].minx;
 396       scissor.offset.y = states[i].miny;
 397       scissor.extent.width = states[i].maxx - states[i].minx;
 398       scissor.extent.height = states[i].maxy - states[i].miny;
 399       ctx->scissors[start_slot + i] = scissor;
 400    }
 401    ctx->num_scissors = start_slot + num_scissors;
 402 }
 403
 404 static void
 405 zink_set_constant_buffer(struct pipe_context *pctx,
 406                          enum pipe_shader_type shader, uint index,
 407                          const struct pipe_constant_buffer *cb)
 408 {
 409    struct zink_context *ctx = zink_context(pctx);
 410
 411    if (cb) {
 412       struct pipe_resource *buffer = cb->buffer;
 413       unsigned offset = cb->buffer_offset;
 414       if (cb->user_buffer)
 415          u_upload_data(ctx->base.const_uploader, 0, cb->buffer_size, 64,
 416                        cb->user_buffer, &offset, &buffer);
 417
 418       pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
 419       ctx->ubos[shader][index].buffer_offset = offset;
 420       ctx->ubos[shader][index].buffer_size = cb->buffer_size;
 421       ctx->ubos[shader][index].user_buffer = NULL;
 422
 423       if (cb->user_buffer)
 424          pipe_resource_reference(&buffer, NULL);
 425    } else {
 426       pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
 427       ctx->ubos[shader][index].buffer_offset = 0;
 428       ctx->ubos[shader][index].buffer_size = 0;
 429       ctx->ubos[shader][index].user_buffer = NULL;
 430    }
 431 }
 432
 433 static void
 434 zink_set_sampler_views(struct pipe_context *pctx,
 435                        enum pipe_shader_type shader_type,
 436                        unsigned start_slot,
 437                        unsigned num_views,
 438                        struct pipe_sampler_view **views)
 439 {
 440    struct zink_context *ctx = zink_context(pctx);
 441    assert(views);
 442    for (unsigned i = 0; i < num_views; ++i) {
 443       pipe_sampler_view_reference(
 444          &ctx->image_views[shader_type][start_slot + i],
 445          views[i]);
 446    }
 447 }
 448
 449 static void
 450 zink_set_stencil_ref(struct pipe_context *pctx,
 451                      const struct pipe_stencil_ref *ref)
 452 {
 453    struct zink_context *ctx = zink_context(pctx);
 454    ctx->stencil_ref[0] = ref->ref_value[0];
 455    ctx->stencil_ref[1] = ref->ref_value[1];
 456 }
 457
 458 static void
 459 zink_set_clip_state(struct pipe_context *pctx,
 460                     const struct pipe_clip_state *pcs)
 461 {
 462 }
 463
 464 static struct zink_render_pass *
 465 get_render_pass(struct zink_context *ctx)
 466 {
 467    struct zink_screen *screen = zink_screen(ctx->base.screen);
 468    const struct pipe_framebuffer_state *fb = &ctx->fb_state;
 469    struct zink_render_pass_state state;
 470
 471    for (int i = 0; i < fb->nr_cbufs; i++) {
 472       struct zink_resource *cbuf = zink_resource(fb->cbufs[i]->texture);
 473       state.rts[i].format = cbuf->format;
 474       state.rts[i].samples = cbuf->base.nr_samples > 0 ? cbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 475    }
 476    state.num_cbufs = fb->nr_cbufs;
 477
 478    if (fb->zsbuf) {
 479       struct zink_resource *zsbuf = zink_resource(fb->zsbuf->texture);
 480       state.rts[fb->nr_cbufs].format = zsbuf->format;
 481       state.rts[fb->nr_cbufs].samples = zsbuf->base.nr_samples > 0 ? zsbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 482    }
 483    state.have_zsbuf = fb->zsbuf != NULL;
 484
 485    struct hash_entry *entry = _mesa_hash_table_search(ctx->render_pass_cache,
 486                                                       &state);
 487    if (!entry) {
 488       struct zink_render_pass *rp;
 489       rp = zink_create_render_pass(screen, &state);
 490       entry = _mesa_hash_table_insert(ctx->render_pass_cache, &state, rp);
 491       if (!entry)
 492          return NULL;
 493    }
 494
 495    return entry->data;
 496 }
 497
 498 static struct zink_framebuffer *
 499 get_framebuffer(struct zink_context *ctx)
 500 {
 501    struct zink_screen *screen = zink_screen(ctx->base.screen);
 502
 503    struct zink_framebuffer_state state = {};
 504    state.rp = get_render_pass(ctx);
 505    for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
 506       struct pipe_surface *psurf = ctx->fb_state.cbufs[i];
 507       state.attachments[i] = zink_surface(psurf);
 508    }
 509
 510    state.num_attachments = ctx->fb_state.nr_cbufs;
 511    if (ctx->fb_state.zsbuf) {
 512       struct pipe_surface *psurf = ctx->fb_state.zsbuf;
 513       state.attachments[state.num_attachments++] = zink_surface(psurf);
 514    }
 515
 516    state.width = ctx->fb_state.width;
 517    state.height = ctx->fb_state.height;
 518    state.layers = MAX2(ctx->fb_state.layers, 1);
 519
 520    struct hash_entry *entry = _mesa_hash_table_search(ctx->framebuffer_cache,
 521                                                       &state);
 522    if (!entry) {
 523       struct zink_framebuffer *fb = zink_create_framebuffer(screen, &state);
 524       entry = _mesa_hash_table_insert(ctx->framebuffer_cache, &state, fb);
 525       if (!entry)
 526          return NULL;
 527    }
 528
 529    return entry->data;
 530 }
 531
 532 void
 533 zink_begin_render_pass(struct zink_context *ctx, struct zink_batch *batch)
 534 {
 535    struct zink_screen *screen = zink_screen(ctx->base.screen);
 536    assert(batch == zink_curr_batch(ctx));
 537    assert(ctx->gfx_pipeline_state.render_pass);
 538
 539    VkRenderPassBeginInfo rpbi = {};
 540    rpbi.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO;
 541    rpbi.renderPass = ctx->gfx_pipeline_state.render_pass->render_pass;
 542    rpbi.renderArea.offset.x = 0;
 543    rpbi.renderArea.offset.y = 0;
 544    rpbi.renderArea.extent.width = ctx->fb_state.width;
 545    rpbi.renderArea.extent.height = ctx->fb_state.height;
 546    rpbi.clearValueCount = 0;
 547    rpbi.pClearValues = NULL;
 548    rpbi.framebuffer = ctx->framebuffer->fb;
 549
 550    assert(ctx->gfx_pipeline_state.render_pass && ctx->framebuffer);
 551    assert(!batch->rp || batch->rp == ctx->gfx_pipeline_state.render_pass);
 552    assert(!batch->fb || batch->fb == ctx->framebuffer);
 553
 554    zink_render_pass_reference(screen, &batch->rp, ctx->gfx_pipeline_state.render_pass);
 555    zink_framebuffer_reference(screen, &batch->fb, ctx->framebuffer);
 556
 557    vkCmdBeginRenderPass(batch->cmdbuf, &rpbi, VK_SUBPASS_CONTENTS_INLINE);
 558 }
 559
 560 static void
 561 flush_batch(struct zink_context *ctx)
 562 {
 563    struct zink_batch *batch = zink_curr_batch(ctx);
 564    if (batch->rp)
 565       vkCmdEndRenderPass(batch->cmdbuf);
 566
 567    zink_end_batch(ctx, batch);
 568
 569    ctx->curr_batch++;
 570    if (ctx->curr_batch == ARRAY_SIZE(ctx->batches))
 571       ctx->curr_batch = 0;
 572
 573    zink_start_batch(ctx, zink_curr_batch(ctx));
 574 }
 575
 576 struct zink_batch *
 577 zink_batch_rp(struct zink_context *ctx)
 578 {
 579    struct zink_batch *batch = zink_curr_batch(ctx);
 580    if (!batch->rp) {
 581       zink_begin_render_pass(ctx, batch);
 582       assert(batch->rp);
 583    }
 584    return batch;
 585 }
 586
 587 struct zink_batch *
 588 zink_batch_no_rp(struct zink_context *ctx)
 589 {
 590    struct zink_batch *batch = zink_curr_batch(ctx);
 591    if (batch->rp) {
 592       /* flush batch and get a new one */
 593       flush_batch(ctx);
 594       batch = zink_curr_batch(ctx);
 595       assert(!batch->rp);
 596    }
 597    return batch;
 598 }
 599
 600 static void
 601 zink_set_framebuffer_state(struct pipe_context *pctx,
 602                            const struct pipe_framebuffer_state *state)
 603 {
 604    struct zink_context *ctx = zink_context(pctx);
 605    struct zink_screen *screen = zink_screen(pctx->screen);
 606
 607    VkSampleCountFlagBits rast_samples = VK_SAMPLE_COUNT_1_BIT;
 608    for (int i = 0; i < state->nr_cbufs; i++)
 609       rast_samples = MAX2(rast_samples, state->cbufs[i]->texture->nr_samples);
 610    if (state->zsbuf && state->zsbuf->texture->nr_samples)
 611       rast_samples = MAX2(rast_samples, state->zsbuf->texture->nr_samples);
 612
 613    util_copy_framebuffer_state(&ctx->fb_state, state);
 614
 615    struct zink_framebuffer *fb = get_framebuffer(ctx);
 616    zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
 617    zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
 618
 619    ctx->gfx_pipeline_state.rast_samples = rast_samples;
 620    ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
 621
 622    struct zink_batch *batch = zink_batch_no_rp(ctx);
 623
 624    for (int i = 0; i < state->nr_cbufs; i++) {
 625       struct zink_resource *res = zink_resource(state->cbufs[i]->texture);
 626       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 627           res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
 628          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 629                                VK_IMAGE_LAYOUT_GENERAL);
 630    }
 631
 632    if (state->zsbuf) {
 633       struct zink_resource *res = zink_resource(state->zsbuf->texture);
 634       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 635           res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
 636          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 637                                VK_IMAGE_LAYOUT_GENERAL);
 638    }
 639 }
 640
 641 static void
 642 zink_set_active_query_state(struct pipe_context *pctx, bool enable)
 643 {
 644 }
 645
 646 static void
 647 zink_set_blend_color(struct pipe_context *pctx,
 648                      const struct pipe_blend_color *color)
 649 {
 650    struct zink_context *ctx = zink_context(pctx);
 651    memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
 652 }
 653
 654 static void
 655 zink_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
 656 {
 657    struct zink_context *ctx = zink_context(pctx);
 658    ctx->gfx_pipeline_state.sample_mask = sample_mask;
 659 }
 660
 661 static VkAccessFlags
 662 access_flags(VkImageLayout layout)
 663 {
 664    switch (layout) {
 665    case VK_IMAGE_LAYOUT_UNDEFINED:
 666    case VK_IMAGE_LAYOUT_GENERAL:
 667       return 0;
 668
 669    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 670       return VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
 671    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 672       return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
 673
 674    case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
 675       return VK_ACCESS_SHADER_READ_BIT;
 676
 677    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 678       return VK_ACCESS_TRANSFER_READ_BIT;
 679
 680    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 681       return VK_ACCESS_TRANSFER_WRITE_BIT;
 682
 683    case VK_IMAGE_LAYOUT_PREINITIALIZED:
 684       return VK_ACCESS_HOST_WRITE_BIT;
 685
 686    default:
 687       unreachable("unexpected layout");
 688    }
 689 }
 690
 691 void
 692 zink_resource_barrier(VkCommandBuffer cmdbuf, struct zink_resource *res,
 693                       VkImageAspectFlags aspect, VkImageLayout new_layout)
 694 {
 695    VkImageSubresourceRange isr = {
 696       aspect,
 697       0, VK_REMAINING_MIP_LEVELS,
 698       0, VK_REMAINING_ARRAY_LAYERS
 699    };
 700
 701    VkImageMemoryBarrier imb = {
 702       VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
 703       NULL,
 704       access_flags(res->layout),
 705       access_flags(new_layout),
 706       res->layout,
 707       new_layout,
 708       VK_QUEUE_FAMILY_IGNORED,
 709       VK_QUEUE_FAMILY_IGNORED,
 710       res->image,
 711       isr
 712    };
 713    vkCmdPipelineBarrier(
 714       cmdbuf,
 715       VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
 716       VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
 717       0,
 718       0, NULL,
 719       0, NULL,
 720       1, &imb
 721    );
 722
 723    res->layout = new_layout;
 724 }
 725
 726 static void
 727 zink_clear(struct pipe_context *pctx,
 728            unsigned buffers,
 729            const union pipe_color_union *pcolor,
 730            double depth, unsigned stencil)
 731 {
 732    struct zink_context *ctx = zink_context(pctx);
 733    struct pipe_framebuffer_state *fb = &ctx->fb_state;
 734
 735    /* FIXME: this is very inefficient; if no renderpass has been started yet,
 736     * we should record the clear if it's full-screen, and apply it as we
 737     * start the render-pass. Otherwise we can do a partial out-of-renderpass
 738     * clear.
 739     */
 740    struct zink_batch *batch = zink_batch_rp(ctx);
 741
 742    VkClearAttachment attachments[1 + PIPE_MAX_COLOR_BUFS];
 743    int num_attachments = 0;
 744
 745    if (buffers & PIPE_CLEAR_COLOR) {
 746       VkClearColorValue color;
 747       color.float32[0] = pcolor->f[0];
 748       color.float32[1] = pcolor->f[1];
 749       color.float32[2] = pcolor->f[2];
 750       color.float32[3] = pcolor->f[3];
 751
 752       for (unsigned i = 0; i < fb->nr_cbufs; i++) {
 753          if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
 754             continue;
 755
 756          attachments[num_attachments].aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
 757          attachments[num_attachments].colorAttachment = i;
 758          attachments[num_attachments].clearValue.color = color;
 759          ++num_attachments;
 760       }
 761    }
 762
 763    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && fb->zsbuf) {
 764       VkImageAspectFlags aspect = 0;
 765       if (buffers & PIPE_CLEAR_DEPTH)
 766          aspect |= VK_IMAGE_ASPECT_DEPTH_BIT;
 767       if (buffers & PIPE_CLEAR_STENCIL)
 768          aspect |= VK_IMAGE_ASPECT_STENCIL_BIT;
 769
 770       attachments[num_attachments].aspectMask = aspect;
 771       attachments[num_attachments].clearValue.depthStencil.depth = depth;
 772       attachments[num_attachments].clearValue.depthStencil.stencil = stencil;
 773       ++num_attachments;
 774    }
 775
 776    unsigned num_layers = util_framebuffer_get_num_layers(fb);
 777    VkClearRect rects[PIPE_MAX_VIEWPORTS];
 778    uint32_t num_rects;
 779    if (ctx->num_scissors) {
 780       for (unsigned i = 0 ; i < ctx->num_scissors; ++i) {
 781          rects[i].rect = ctx->scissors[i];
 782          rects[i].rect.extent.width = MIN2(rects[i].rect.extent.width,
 783                                            fb->width);
 784          rects[i].rect.extent.height = MIN2(rects[i].rect.extent.height,
 785                                             fb->height);
 786          rects[i].baseArrayLayer = 0;
 787          rects[i].layerCount = num_layers;
 788       }
 789       num_rects = ctx->num_scissors;
 790    } else {
 791       rects[0].rect.offset.x = 0;
 792       rects[0].rect.offset.y = 0;
 793       rects[0].rect.extent.width = fb->width;
 794       rects[0].rect.extent.height = fb->height;
 795       rects[0].baseArrayLayer = 0;
 796       rects[0].layerCount = num_layers;
 797       num_rects = 1;
 798    }
 799
 800    vkCmdClearAttachments(batch->cmdbuf,
 801                          num_attachments, attachments,
 802                          num_rects, rects);
 803 }
 804
 805 VkShaderStageFlagBits
 806 zink_shader_stage(enum pipe_shader_type type)
 807 {
 808    VkShaderStageFlagBits stages[] = {
 809       [PIPE_SHADER_VERTEX] = VK_SHADER_STAGE_VERTEX_BIT,
 810       [PIPE_SHADER_FRAGMENT] = VK_SHADER_STAGE_FRAGMENT_BIT,
 811       [PIPE_SHADER_GEOMETRY] = VK_SHADER_STAGE_GEOMETRY_BIT,
 812       [PIPE_SHADER_TESS_CTRL] = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
 813       [PIPE_SHADER_TESS_EVAL] = VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
 814       [PIPE_SHADER_COMPUTE] = VK_SHADER_STAGE_COMPUTE_BIT,
 815    };
 816    return stages[type];
 817 }
 818
 819 static VkDescriptorSet
 820 allocate_descriptor_set(struct zink_screen *screen,
 821                         struct zink_batch *batch,
 822                         struct zink_gfx_program *prog)
 823 {
 824    assert(batch->descs_left >= prog->num_descriptors);
 825    VkDescriptorSetAllocateInfo dsai;
 826    memset((void *)&dsai, 0, sizeof(dsai));
 827    dsai.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO;
 828    dsai.pNext = NULL;
 829    dsai.descriptorPool = batch->descpool;
 830    dsai.descriptorSetCount = 1;
 831    dsai.pSetLayouts = &prog->dsl;
 832
 833    VkDescriptorSet desc_set;
 834    if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
 835       debug_printf("ZINK: failed to allocate descriptor set :/");
 836       return VK_NULL_HANDLE;
 837    }
 838
 839    batch->descs_left -= prog->num_descriptors;
 840    return desc_set;
 841 }
 842
 843 static void
 844 zink_bind_vertex_buffers(struct zink_batch *batch, struct zink_context *ctx)
 845 {
 846    VkBuffer buffers[PIPE_MAX_ATTRIBS];
 847    VkDeviceSize buffer_offsets[PIPE_MAX_ATTRIBS];
 848    const struct zink_vertex_elements_state *elems = ctx->element_state;
 849    for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) {
 850       struct pipe_vertex_buffer *vb = ctx->buffers + ctx->element_state->binding_map[i];
 851       assert(vb && vb->buffer.resource);
 852       struct zink_resource *res = zink_resource(vb->buffer.resource);
 853       buffers[i] = res->buffer;
 854       buffer_offsets[i] = vb->buffer_offset;
 855       zink_batch_reference_resoure(batch, res);
 856    }
 857
 858    if (elems->hw_state.num_bindings > 0)
 859       vkCmdBindVertexBuffers(batch->cmdbuf, 0,
 860                              elems->hw_state.num_bindings,
 861                              buffers, buffer_offsets);
 862 }
 863
 864 static uint32_t
 865 hash_gfx_program(const void *key)
 866 {
 867    return _mesa_hash_data(key, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1));
 868 }
 869
 870 static bool
 871 equals_gfx_program(const void *a, const void *b)
 872 {
 873    return memcmp(a, b, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1)) == 0;
 874 }
 875
 876 static uint32_t
 877 hash_render_pass_state(const void *key)
 878 {
 879    return _mesa_hash_data(key, sizeof(struct zink_render_pass_state));
 880 }
 881
 882 static bool
 883 equals_render_pass_state(const void *a, const void *b)
 884 {
 885    return memcmp(a, b, sizeof(struct zink_render_pass_state)) == 0;
 886 }
 887
 888 static uint32_t
 889 hash_framebuffer_state(const void *key)
 890 {
 891    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)key;
 892    return _mesa_hash_data(key, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments);
 893 }
 894
 895 static bool
 896 equals_framebuffer_state(const void *a, const void *b)
 897 {
 898    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)a;
 899    return memcmp(a, b, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments) == 0;
 900 }
 901
 902 static struct zink_gfx_program *
 903 get_gfx_program(struct zink_context *ctx)
 904 {
 905    if (ctx->dirty & ZINK_DIRTY_PROGRAM) {
 906       struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
 907                                                          ctx->gfx_stages);
 908       if (!entry) {
 909          struct zink_gfx_program *prog;
 910          prog = zink_create_gfx_program(zink_screen(ctx->base.screen),
 911                                                      ctx->gfx_stages);
 912          entry = _mesa_hash_table_insert(ctx->program_cache, prog->stages, prog);
 913          if (!entry)
 914             return NULL;
 915       }
 916       ctx->curr_program = entry->data;
 917       ctx->dirty &= ~ZINK_DIRTY_PROGRAM;
 918    }
 919
 920    assert(ctx->curr_program);
 921    return ctx->curr_program;
 922 }
 923
 924 static void
 925 zink_draw_vbo(struct pipe_context *pctx,
 926               const struct pipe_draw_info *dinfo)
 927 {
 928    struct zink_context *ctx = zink_context(pctx);
 929    struct zink_screen *screen = zink_screen(pctx->screen);
 930    struct zink_rasterizer_state *rast_state = ctx->rast_state;
 931
 932    if (dinfo->mode >= PIPE_PRIM_QUADS ||
 933        dinfo->mode == PIPE_PRIM_LINE_LOOP) {
 934       if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&dinfo->count))
 935          return;
 936
 937       util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
 938       util_primconvert_draw_vbo(ctx->primconvert, dinfo);
 939       return;
 940    }
 941
 942    struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
 943    if (!gfx_program)
 944       return;
 945
 946    VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
 947                                                &ctx->gfx_pipeline_state,
 948                                                dinfo->mode);
 949
 950    bool depth_bias = false;
 951    switch (u_reduced_prim(dinfo->mode)) {
 952    case PIPE_PRIM_POINTS:
 953       depth_bias = rast_state->offset_point;
 954       break;
 955
 956    case PIPE_PRIM_LINES:
 957       depth_bias = rast_state->offset_line;
 958       break;
 959
 960    case PIPE_PRIM_TRIANGLES:
 961       depth_bias = rast_state->offset_tri;
 962       break;
 963
 964    default:
 965       unreachable("unexpected reduced prim");
 966    }
 967
 968    unsigned index_offset = 0;
 969    struct pipe_resource *index_buffer = NULL;
 970    if (dinfo->index_size > 0) {
 971       if (dinfo->has_user_indices) {
 972          if (!util_upload_index_buffer(pctx, dinfo, &index_buffer, &index_offset)) {
 973             debug_printf("util_upload_index_buffer() failed\n");
 974             return;
 975          }
 976       } else
 977          index_buffer = dinfo->index.resource;
 978    }
 979
 980    VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS + PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 981    VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS];
 982    VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 983    int num_wds = 0, num_buffer_info = 0, num_image_info = 0;
 984
 985    struct zink_resource *transitions[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 986    int num_transitions = 0;
 987
 988    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
 989       struct zink_shader *shader = ctx->gfx_stages[i];
 990       if (!shader)
 991          continue;
 992
 993       for (int j = 0; j < shader->num_bindings; j++) {
 994          int index = shader->bindings[j].index;
 995          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
 996             assert(ctx->ubos[i][index].buffer_size > 0);
 997             assert(ctx->ubos[i][index].buffer);
 998             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
 999             buffer_infos[num_buffer_info].buffer = res->buffer;
1000             buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset;
1001             buffer_infos[num_buffer_info].range  = VK_WHOLE_SIZE;
1002             wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info;
1003             ++num_buffer_info;
1004          } else {
1005             struct pipe_sampler_view *psampler_view = ctx->image_views[i][index];
1006             assert(psampler_view);
1007             struct zink_sampler_view *sampler_view = zink_sampler_view(psampler_view);
1008
1009             struct zink_resource *res = zink_resource(psampler_view->texture);
1010             VkImageLayout layout = res->layout;
1011             if (layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL &&
1012                 layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL &&
1013                 layout != VK_IMAGE_LAYOUT_GENERAL) {
1014                transitions[num_transitions++] = res;
1015                layout = VK_IMAGE_LAYOUT_GENERAL;
1016             }
1017             image_infos[num_image_info].imageLayout = layout;
1018             image_infos[num_image_info].imageView = sampler_view->image_view;
1019             image_infos[num_image_info].sampler = ctx->samplers[i][index];
1020             wds[num_wds].pImageInfo = image_infos + num_image_info;
1021             ++num_image_info;
1022          }
1023
1024          wds[num_wds].sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET;
1025          wds[num_wds].pNext = NULL;
1026          wds[num_wds].dstBinding = shader->bindings[j].binding;
1027          wds[num_wds].dstArrayElement = 0;
1028          wds[num_wds].descriptorCount = 1;
1029          wds[num_wds].descriptorType = shader->bindings[j].type;
1030          ++num_wds;
1031       }
1032    }
1033
1034    struct zink_batch *batch;
1035    if (num_transitions > 0) {
1036       batch = zink_batch_no_rp(ctx);
1037
1038       for (int i = 0; i < num_transitions; ++i)
1039          zink_resource_barrier(batch->cmdbuf, transitions[i],
1040                                transitions[i]->aspect,
1041                                VK_IMAGE_LAYOUT_GENERAL);
1042    }
1043
1044    batch = zink_batch_rp(ctx);
1045
1046    if (batch->descs_left < gfx_program->num_descriptors) {
1047       flush_batch(ctx);
1048       batch = zink_batch_rp(ctx);
1049       assert(batch->descs_left >= gfx_program->num_descriptors);
1050    }
1051
1052    VkDescriptorSet desc_set = allocate_descriptor_set(screen, batch,
1053                                                       gfx_program);
1054    assert(desc_set != VK_NULL_HANDLE);
1055
1056    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1057       struct zink_shader *shader = ctx->gfx_stages[i];
1058       if (!shader)
1059          continue;
1060
1061       for (int j = 0; j < shader->num_bindings; j++) {
1062          int index = shader->bindings[j].index;
1063          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1064             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1065             zink_batch_reference_resoure(batch, res);
1066          } else {
1067             struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->image_views[i][index]);
1068             zink_batch_reference_sampler_view(batch, sampler_view);
1069          }
1070       }
1071    }
1072
1073    vkCmdSetViewport(batch->cmdbuf, 0, ctx->num_viewports, ctx->viewports);
1074
1075    if (ctx->num_scissors)
1076       vkCmdSetScissor(batch->cmdbuf, 0, ctx->num_scissors, ctx->scissors);
1077    else if (ctx->fb_state.width && ctx->fb_state.height) {
1078       VkRect2D fb_scissor = {};
1079       fb_scissor.extent.width = ctx->fb_state.width;
1080       fb_scissor.extent.height = ctx->fb_state.height;
1081       vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
1082    }
1083
1084    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref[0]);
1085    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref[1]);
1086
1087    if (depth_bias)
1088       vkCmdSetDepthBias(batch->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
1089    else
1090       vkCmdSetDepthBias(batch->cmdbuf, 0.0f, 0.0f, 0.0f);
1091
1092    if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
1093       vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
1094
1095    for (int i = 0; i < num_wds; ++i)
1096       wds[i].dstSet = desc_set;
1097
1098    vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
1099
1100    vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
1101    vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
1102                            gfx_program->layout, 0, 1, &desc_set, 0, NULL);
1103    zink_bind_vertex_buffers(batch, ctx);
1104
1105    if (dinfo->index_size > 0) {
1106       assert(dinfo->index_size != 1);
1107       VkIndexType index_type = dinfo->index_size == 2 ? VK_INDEX_TYPE_UINT16 : VK_INDEX_TYPE_UINT32;
1108       struct zink_resource *res = zink_resource(index_buffer);
1109       vkCmdBindIndexBuffer(batch->cmdbuf, res->buffer, index_offset, index_type);
1110       zink_batch_reference_resoure(batch, res);
1111       vkCmdDrawIndexed(batch->cmdbuf,
1112          dinfo->count, dinfo->instance_count,
1113          dinfo->start, dinfo->index_bias, dinfo->start_instance);
1114    } else
1115       vkCmdDraw(batch->cmdbuf, dinfo->count, dinfo->instance_count, dinfo->start, dinfo->start_instance);
1116
1117    if (dinfo->index_size > 0 && dinfo->has_user_indices)
1118       pipe_resource_reference(&index_buffer, NULL);
1119 }
1120
1121 static void
1122 zink_flush(struct pipe_context *pctx,
1123            struct pipe_fence_handle **pfence,
1124            enum pipe_flush_flags flags)
1125 {
1126    struct zink_context *ctx = zink_context(pctx);
1127
1128    struct zink_batch *batch = zink_curr_batch(ctx);
1129    flush_batch(ctx);
1130
1131    if (pfence)
1132       zink_fence_reference(zink_screen(pctx->screen),
1133                            (struct zink_fence **)pfence,
1134                            batch->fence);
1135
1136    if (flags & PIPE_FLUSH_END_OF_FRAME)
1137       pctx->screen->fence_finish(pctx->screen, pctx,
1138                                  (struct pipe_fence_handle *)batch->fence,
1139                                  PIPE_TIMEOUT_INFINITE);
1140 }
1141
1142 static void
1143 zink_blit(struct pipe_context *pctx,
1144           const struct pipe_blit_info *info)
1145 {
1146    struct zink_context *ctx = zink_context(pctx);
1147    bool is_resolve = false;
1148    if (info->mask != PIPE_MASK_RGBA ||
1149        info->scissor_enable ||
1150        info->alpha_blend) {
1151       if (!util_blitter_is_blit_supported(ctx->blitter, info)) {
1152          debug_printf("blit unsupported %s -> %s\n",
1153                  util_format_short_name(info->src.resource->format),
1154                  util_format_short_name(info->dst.resource->format));
1155          return;
1156       }
1157
1158       util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[PIPE_SHADER_FRAGMENT]);
1159       util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->buffers);
1160       util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
1161       util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
1162       util_blitter_save_rasterizer(ctx->blitter, ctx->gfx_pipeline_state.rast_state);
1163
1164       util_blitter_blit(ctx->blitter, info);
1165       return;
1166    }
1167
1168    struct zink_resource *src = zink_resource(info->src.resource);
1169    struct zink_resource *dst = zink_resource(info->dst.resource);
1170
1171    if (src->base.nr_samples > 1 && dst->base.nr_samples <= 1)
1172       is_resolve = true;
1173
1174    struct zink_batch *batch = zink_batch_no_rp(ctx);
1175
1176    zink_batch_reference_resoure(batch, src);
1177    zink_batch_reference_resoure(batch, dst);
1178
1179    if (is_resolve) {
1180       VkImageResolve region = {};
1181
1182       region.srcSubresource.aspectMask = src->aspect;
1183       region.srcSubresource.mipLevel = info->src.level;
1184       region.srcSubresource.baseArrayLayer = 0; // no clue
1185       region.srcSubresource.layerCount = 1; // no clue
1186       region.srcOffset.x = info->src.box.x;
1187       region.srcOffset.y = info->src.box.y;
1188       region.srcOffset.z = info->src.box.z;
1189
1190       region.dstSubresource.aspectMask = dst->aspect;
1191       region.dstSubresource.mipLevel = info->dst.level;
1192       region.dstSubresource.baseArrayLayer = 0; // no clue
1193       region.dstSubresource.layerCount = 1; // no clue
1194       region.dstOffset.x = info->dst.box.x;
1195       region.dstOffset.y = info->dst.box.y;
1196       region.dstOffset.z = info->dst.box.z;
1197
1198       region.extent.width = info->dst.box.width;
1199       region.extent.height = info->dst.box.height;
1200       region.extent.depth = info->dst.box.depth;
1201       vkCmdResolveImage(batch->cmdbuf, src->image, src->layout,
1202                         dst->image, dst->layout,
1203                         1, &region);
1204
1205    } else {
1206       if (dst->layout != VK_IMAGE_LAYOUT_GENERAL &&
1207           dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL)
1208          zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1209                                VK_IMAGE_LAYOUT_GENERAL);
1210
1211       VkImageBlit region = {};
1212       region.srcSubresource.aspectMask = src->aspect;
1213       region.srcSubresource.mipLevel = info->src.level;
1214       region.srcOffsets[0].x = info->src.box.x;
1215       region.srcOffsets[0].y = info->src.box.y;
1216       region.srcOffsets[1].x = info->src.box.x + info->src.box.width;
1217       region.srcOffsets[1].y = info->src.box.y + info->src.box.height;
1218
1219       if (src->base.array_size > 1) {
1220          region.srcOffsets[0].z = 0;
1221          region.srcOffsets[1].z = 1;
1222          region.srcSubresource.baseArrayLayer = info->src.box.z;
1223          region.srcSubresource.layerCount = info->src.box.depth;
1224       } else {
1225          region.srcOffsets[0].z = info->src.box.z;
1226          region.srcOffsets[1].z = info->src.box.z + info->src.box.depth;
1227          region.srcSubresource.baseArrayLayer = 0;
1228          region.srcSubresource.layerCount = 1;
1229       }
1230
1231       region.dstSubresource.aspectMask = dst->aspect;
1232       region.dstSubresource.mipLevel = info->dst.level;
1233       region.dstOffsets[0].x = info->dst.box.x;
1234       region.dstOffsets[0].y = info->dst.box.y;
1235       region.dstOffsets[1].x = info->dst.box.x + info->dst.box.width;
1236       region.dstOffsets[1].y = info->dst.box.y + info->dst.box.height;
1237
1238       if (dst->base.array_size > 1) {
1239          region.dstOffsets[0].z = 0;
1240          region.dstOffsets[1].z = 1;
1241          region.dstSubresource.baseArrayLayer = info->dst.box.z;
1242          region.dstSubresource.layerCount = info->dst.box.depth;
1243       } else {
1244          region.dstOffsets[0].z = info->dst.box.z;
1245          region.dstOffsets[1].z = info->dst.box.z + info->dst.box.depth;
1246          region.dstSubresource.baseArrayLayer = 0;
1247          region.dstSubresource.layerCount = 1;
1248       }
1249
1250       vkCmdBlitImage(batch->cmdbuf, src->image, src->layout,
1251                      dst->image, dst->layout,
1252                      1, &region,
1253                      filter(info->filter));
1254    }
1255
1256    /* HACK: I have no idea why this is needed, but without it ioquake3
1257     * randomly keeps fading to black.
1258     */
1259    flush_batch(ctx);
1260 }
1261
1262 static void
1263 zink_flush_resource(struct pipe_context *pipe,
1264                     struct pipe_resource *resource)
1265 {
1266 }
1267
1268 static void
1269 zink_resource_copy_region(struct pipe_context *pctx,
1270                           struct pipe_resource *pdst,
1271                           unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1272                           struct pipe_resource *psrc,
1273                           unsigned src_level, const struct pipe_box *src_box)
1274 {
1275    struct zink_resource *dst = zink_resource(pdst);
1276    struct zink_resource *src = zink_resource(psrc);
1277    struct zink_context *ctx = zink_context(pctx);
1278    if (dst->base.target != PIPE_BUFFER && src->base.target != PIPE_BUFFER) {
1279       VkImageCopy region = {};
1280
1281       region.srcSubresource.aspectMask = src->aspect;
1282       region.srcSubresource.mipLevel = src_level;
1283       region.srcSubresource.layerCount = 1;
1284       if (src->base.array_size > 1) {
1285          region.srcSubresource.baseArrayLayer = src_box->z;
1286          region.srcSubresource.layerCount = src_box->depth;
1287          region.extent.depth = 1;
1288       } else {
1289          region.srcOffset.z = src_box->z;
1290          region.srcSubresource.layerCount = 1;
1291          region.extent.depth = src_box->depth;
1292       }
1293
1294       region.srcOffset.x = src_box->x;
1295       region.srcOffset.y = src_box->y;
1296
1297       region.dstSubresource.aspectMask = dst->aspect;
1298       region.dstSubresource.mipLevel = dst_level;
1299       if (dst->base.array_size > 1) {
1300          region.dstSubresource.baseArrayLayer = dstz;
1301          region.dstSubresource.layerCount = src_box->depth;
1302       } else {
1303          region.dstOffset.z = dstz;
1304          region.dstSubresource.layerCount = 1;
1305       }
1306
1307       region.dstOffset.x = dstx;
1308       region.dstOffset.y = dsty;
1309       region.extent.width = src_box->width;
1310       region.extent.height = src_box->height;
1311
1312       struct zink_batch *batch = zink_batch_no_rp(ctx);
1313       zink_batch_reference_resoure(batch, src);
1314       zink_batch_reference_resoure(batch, dst);
1315
1316       vkCmdCopyImage(batch->cmdbuf, src->image, src->layout,
1317                      dst->image, dst->layout,
1318                      1, &region);
1319    } else
1320       debug_printf("zink: TODO resource copy\n");
1321 }
1322
1323 struct pipe_context *
1324 zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
1325 {
1326    struct zink_screen *screen = zink_screen(pscreen);
1327    struct zink_context *ctx = CALLOC_STRUCT(zink_context);
1328
1329    ctx->base.screen = pscreen;
1330    ctx->base.priv = priv;
1331
1332    ctx->base.destroy = zink_context_destroy;
1333
1334    zink_context_state_init(&ctx->base);
1335
1336    ctx->base.create_sampler_state = zink_create_sampler_state;
1337    ctx->base.bind_sampler_states = zink_bind_sampler_states;
1338    ctx->base.delete_sampler_state = zink_delete_sampler_state;
1339
1340    ctx->base.create_sampler_view = zink_create_sampler_view;
1341    ctx->base.set_sampler_views = zink_set_sampler_views;
1342    ctx->base.sampler_view_destroy = zink_sampler_view_destroy;
1343
1344    ctx->base.create_vs_state = zink_create_vs_state;
1345    ctx->base.bind_vs_state = zink_bind_vs_state;
1346    ctx->base.delete_vs_state = zink_delete_vs_state;
1347
1348    ctx->base.create_fs_state = zink_create_fs_state;
1349    ctx->base.bind_fs_state = zink_bind_fs_state;
1350    ctx->base.delete_fs_state = zink_delete_fs_state;
1351
1352    ctx->base.set_polygon_stipple = zink_set_polygon_stipple;
1353    ctx->base.set_vertex_buffers = zink_set_vertex_buffers;
1354    ctx->base.set_viewport_states = zink_set_viewport_states;
1355    ctx->base.set_scissor_states = zink_set_scissor_states;
1356    ctx->base.set_constant_buffer = zink_set_constant_buffer;
1357    ctx->base.set_framebuffer_state = zink_set_framebuffer_state;
1358    ctx->base.set_stencil_ref = zink_set_stencil_ref;
1359    ctx->base.set_clip_state = zink_set_clip_state;
1360    ctx->base.set_active_query_state = zink_set_active_query_state;
1361    ctx->base.set_blend_color = zink_set_blend_color;
1362
1363    ctx->base.set_sample_mask = zink_set_sample_mask;
1364
1365    ctx->base.clear = zink_clear;
1366    ctx->base.draw_vbo = zink_draw_vbo;
1367    ctx->base.flush = zink_flush;
1368
1369    ctx->base.resource_copy_region = zink_resource_copy_region;
1370    ctx->base.blit = zink_blit;
1371
1372    ctx->base.flush_resource = zink_flush_resource;
1373    zink_context_surface_init(&ctx->base);
1374    zink_context_resource_init(&ctx->base);
1375    zink_context_query_init(&ctx->base);
1376
1377    slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
1378
1379    ctx->base.stream_uploader = u_upload_create_default(&ctx->base);
1380    ctx->base.const_uploader = ctx->base.stream_uploader;
1381
1382    int prim_hwsupport = 1 << PIPE_PRIM_POINTS |
1383                         1 << PIPE_PRIM_LINES |
1384                         1 << PIPE_PRIM_LINE_STRIP |
1385                         1 << PIPE_PRIM_TRIANGLES |
1386                         1 << PIPE_PRIM_TRIANGLE_STRIP |
1387                         1 << PIPE_PRIM_TRIANGLE_FAN;
1388
1389    ctx->primconvert = util_primconvert_create(&ctx->base, prim_hwsupport);
1390    if (!ctx->primconvert)
1391       goto fail;
1392
1393    ctx->blitter = util_blitter_create(&ctx->base);
1394    if (!ctx->blitter)
1395       goto fail;
1396
1397    VkCommandPoolCreateInfo cpci = {};
1398    cpci.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO;
1399    cpci.queueFamilyIndex = screen->gfx_queue;
1400    cpci.flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT;
1401    if (vkCreateCommandPool(screen->dev, &cpci, NULL, &ctx->cmdpool) != VK_SUCCESS)
1402       goto fail;
1403
1404    VkCommandBufferAllocateInfo cbai = {};
1405    cbai.sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO;
1406    cbai.commandPool = ctx->cmdpool;
1407    cbai.level = VK_COMMAND_BUFFER_LEVEL_PRIMARY;
1408    cbai.commandBufferCount = 1;
1409
1410    VkDescriptorPoolSize sizes[] = {
1411       {VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER, ZINK_BATCH_DESC_SIZE}
1412    };
1413    VkDescriptorPoolCreateInfo dpci = {};
1414    dpci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO;
1415    dpci.pPoolSizes = sizes;
1416    dpci.poolSizeCount = ARRAY_SIZE(sizes);
1417    dpci.flags = VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT;
1418    dpci.maxSets = ZINK_BATCH_DESC_SIZE;
1419
1420    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i) {
1421       if (vkAllocateCommandBuffers(screen->dev, &cbai, &ctx->batches[i].cmdbuf) != VK_SUCCESS)
1422          goto fail;
1423
1424       ctx->batches[i].resources = _mesa_set_create(NULL, _mesa_hash_pointer,
1425                                                    _mesa_key_pointer_equal);
1426       ctx->batches[i].sampler_views = _mesa_set_create(NULL,
1427                                                        _mesa_hash_pointer,
1428                                                        _mesa_key_pointer_equal);
1429
1430       if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views)
1431          goto fail;
1432
1433       util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL);
1434
1435       if (vkCreateDescriptorPool(screen->dev, &dpci, 0,
1436                                  &ctx->batches[i].descpool) != VK_SUCCESS)
1437          goto fail;
1438    }
1439
1440    vkGetDeviceQueue(screen->dev, screen->gfx_queue, 0, &ctx->queue);
1441
1442    ctx->program_cache = _mesa_hash_table_create(NULL,
1443                                                 hash_gfx_program,
1444                                                 equals_gfx_program);
1445    ctx->render_pass_cache = _mesa_hash_table_create(NULL,
1446                                                     hash_render_pass_state,
1447                                                     equals_render_pass_state);
1448    ctx->framebuffer_cache = _mesa_hash_table_create(NULL,
1449                                                     hash_framebuffer_state,
1450                                                     equals_framebuffer_state);
1451
1452    if (!ctx->program_cache || !ctx->render_pass_cache ||
1453        !ctx->framebuffer_cache)
1454       goto fail;
1455
1456    ctx->dirty = ZINK_DIRTY_PROGRAM;
1457
1458    /* start the first batch */
1459    zink_start_batch(ctx, zink_curr_batch(ctx));
1460
1461    return &ctx->base;
1462
1463 fail:
1464    if (ctx) {
1465       vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
1466       FREE(ctx);
1467    }
1468    return NULL;
1469 }