src/gallium/drivers/zink/zink_context.c

   1 /*
   2  * Copyright 2018 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "zink_context.h"
  25
  26 #include "zink_batch.h"
  27 #include "zink_compiler.h"
  28 #include "zink_fence.h"
  29 #include "zink_framebuffer.h"
  30 #include "zink_pipeline.h"
  31 #include "zink_program.h"
  32 #include "zink_render_pass.h"
  33 #include "zink_resource.h"
  34 #include "zink_screen.h"
  35 #include "zink_state.h"
  36 #include "zink_surface.h"
  37
  38 #include "indices/u_primconvert.h"
  39 #include "util/u_blitter.h"
  40 #include "util/u_debug.h"
  41 #include "util/u_format.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45
  46 #include "nir.h"
  47
  48 #include "util/u_memory.h"
  49 #include "util/u_prim.h"
  50 #include "util/u_upload_mgr.h"
  51
  52 static void
  53 zink_context_destroy(struct pipe_context *pctx)
  54 {
  55    struct zink_context *ctx = zink_context(pctx);
  56    struct zink_screen *screen = zink_screen(pctx->screen);
  57
  58    if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS)
  59       debug_printf("vkQueueWaitIdle failed\n");
  60
  61    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i)
  62       vkFreeCommandBuffers(screen->dev, ctx->cmdpool, 1, &ctx->batches[i].cmdbuf);
  63    vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
  64
  65    util_primconvert_destroy(ctx->primconvert);
  66    u_upload_destroy(pctx->stream_uploader);
  67    slab_destroy_child(&ctx->transfer_pool);
  68    util_blitter_destroy(ctx->blitter);
  69    FREE(ctx);
  70 }
  71
  72 static VkFilter
  73 filter(enum pipe_tex_filter filter)
  74 {
  75    switch (filter) {
  76    case PIPE_TEX_FILTER_NEAREST: return VK_FILTER_NEAREST;
  77    case PIPE_TEX_FILTER_LINEAR: return VK_FILTER_LINEAR;
  78    }
  79    unreachable("unexpected filter");
  80 }
  81
  82 static VkSamplerMipmapMode
  83 sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
  84 {
  85    switch (filter) {
  86    case PIPE_TEX_MIPFILTER_NEAREST: return VK_SAMPLER_MIPMAP_MODE_NEAREST;
  87    case PIPE_TEX_MIPFILTER_LINEAR: return VK_SAMPLER_MIPMAP_MODE_LINEAR;
  88    case PIPE_TEX_MIPFILTER_NONE:
  89       unreachable("PIPE_TEX_MIPFILTER_NONE should be dealt with earlier");
  90    }
  91    unreachable("unexpected filter");
  92 }
  93
  94 static VkSamplerAddressMode
  95 sampler_address_mode(enum pipe_tex_wrap filter)
  96 {
  97    switch (filter) {
  98    case PIPE_TEX_WRAP_REPEAT: return VK_SAMPLER_ADDRESS_MODE_REPEAT;
  99    case PIPE_TEX_WRAP_CLAMP: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 100    case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE;
 101    case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
 102    case PIPE_TEX_WRAP_MIRROR_REPEAT: return VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT;
 103    case PIPE_TEX_WRAP_MIRROR_CLAMP: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 104    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE;
 105    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 106    }
 107    unreachable("unexpected wrap");
 108 }
 109
 110 static void *
 111 zink_create_sampler_state(struct pipe_context *pctx,
 112                           const struct pipe_sampler_state *state)
 113 {
 114    struct zink_screen *screen = zink_screen(pctx->screen);
 115
 116    VkSamplerCreateInfo sci = {};
 117    sci.sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO;
 118    sci.magFilter = filter(state->mag_img_filter);
 119    sci.minFilter = filter(state->min_img_filter);
 120
 121    if (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 122       sci.mipmapMode = sampler_mipmap_mode(state->min_mip_filter);
 123       sci.minLod = state->min_lod;
 124       sci.maxLod = state->max_lod;
 125    } else {
 126       sci.mipmapMode = VK_SAMPLER_MIPMAP_MODE_NEAREST;
 127       sci.minLod = 0;
 128       sci.maxLod = 0;
 129    }
 130
 131    sci.addressModeU = sampler_address_mode(state->wrap_s);
 132    sci.addressModeV = sampler_address_mode(state->wrap_t);
 133    sci.addressModeW = sampler_address_mode(state->wrap_r);
 134    sci.mipLodBias = state->lod_bias;
 135    sci.compareOp = VK_COMPARE_OP_NEVER; // TODO
 136    sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO
 137    sci.unnormalizedCoordinates = !state->normalized_coords;
 138
 139    if (state->max_anisotropy > 1) {
 140       sci.maxAnisotropy = state->max_anisotropy;
 141       sci.anisotropyEnable = VK_TRUE;
 142    }
 143
 144    VkSampler sampler;
 145    VkResult err = vkCreateSampler(screen->dev, &sci, NULL, &sampler);
 146    if (err != VK_SUCCESS)
 147       return NULL;
 148
 149    return sampler;
 150 }
 151
 152 static void
 153 zink_bind_sampler_states(struct pipe_context *pctx,
 154                          enum pipe_shader_type shader,
 155                          unsigned start_slot,
 156                          unsigned num_samplers,
 157                          void **samplers)
 158 {
 159    struct zink_context *ctx = zink_context(pctx);
 160    for (unsigned i = 0; i < num_samplers; ++i)
 161       ctx->samplers[shader][start_slot + i] = (VkSampler)samplers[i];
 162 }
 163
 164 static void
 165 zink_delete_sampler_state(struct pipe_context *pctx,
 166                           void *sampler_state)
 167 {
 168    struct zink_batch *batch = zink_context_curr_batch(zink_context(pctx));
 169    util_dynarray_append(&batch->zombie_samplers,
 170                         VkSampler, sampler_state);
 171 }
 172
 173
 174 static VkImageViewType
 175 image_view_type(enum pipe_texture_target target)
 176 {
 177    switch (target) {
 178    case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
 179    case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
 180    case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
 181    case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
 182    case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
 183    case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
 184    case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
 185    case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D; /* not sure */
 186    default:
 187       unreachable("unexpected target");
 188    }
 189 }
 190
 191 static VkComponentSwizzle
 192 component_mapping(enum pipe_swizzle swizzle)
 193 {
 194    switch (swizzle) {
 195    case PIPE_SWIZZLE_X: return VK_COMPONENT_SWIZZLE_R;
 196    case PIPE_SWIZZLE_Y: return VK_COMPONENT_SWIZZLE_G;
 197    case PIPE_SWIZZLE_Z: return VK_COMPONENT_SWIZZLE_B;
 198    case PIPE_SWIZZLE_W: return VK_COMPONENT_SWIZZLE_A;
 199    case PIPE_SWIZZLE_0: return VK_COMPONENT_SWIZZLE_ZERO;
 200    case PIPE_SWIZZLE_1: return VK_COMPONENT_SWIZZLE_ONE;
 201    case PIPE_SWIZZLE_NONE: return VK_COMPONENT_SWIZZLE_IDENTITY; // ???
 202    default:
 203       unreachable("unexpected swizzle");
 204    }
 205 }
 206
 207 static struct pipe_sampler_view *
 208 zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
 209                          const struct pipe_sampler_view *state)
 210 {
 211    struct zink_screen *screen = zink_screen(pctx->screen);
 212    struct zink_resource *res = zink_resource(pres);
 213    struct zink_sampler_view *sampler_view = CALLOC_STRUCT(zink_sampler_view);
 214
 215    sampler_view->base = *state;
 216    sampler_view->base.texture = NULL;
 217    pipe_resource_reference(&sampler_view->base.texture, pres);
 218    sampler_view->base.reference.count = 1;
 219    sampler_view->base.context = pctx;
 220
 221    VkImageViewCreateInfo ivci = {};
 222    ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
 223    ivci.image = res->image;
 224    ivci.viewType = image_view_type(state->target);
 225    ivci.format = zink_get_format(state->format);
 226    ivci.components.r = component_mapping(state->swizzle_r);
 227    ivci.components.g = component_mapping(state->swizzle_g);
 228    ivci.components.b = component_mapping(state->swizzle_b);
 229    ivci.components.a = component_mapping(state->swizzle_a);
 230    ivci.subresourceRange.aspectMask = zink_aspect_from_format(state->format);
 231    ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
 232    ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
 233    ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
 234    ivci.subresourceRange.layerCount = state->u.tex.last_layer - state->u.tex.first_layer + 1;
 235
 236    VkResult err = vkCreateImageView(screen->dev, &ivci, NULL, &sampler_view->image_view);
 237    if (err != VK_SUCCESS) {
 238       FREE(sampler_view);
 239       return NULL;
 240    }
 241
 242    return &sampler_view->base;
 243 }
 244
 245 static void
 246 zink_destroy_sampler_view(struct pipe_context *pctx,
 247                           struct pipe_sampler_view *pview)
 248 {
 249    struct zink_sampler_view *view = zink_sampler_view(pview);
 250    vkDestroyImageView(zink_screen(pctx->screen)->dev, view->image_view, NULL);
 251    FREE(view);
 252 }
 253
 254 static void *
 255 zink_create_vs_state(struct pipe_context *pctx,
 256                      const struct pipe_shader_state *shader)
 257 {
 258    struct nir_shader *nir;
 259    if (shader->type != PIPE_SHADER_IR_NIR)
 260       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 261    else
 262       nir = (struct nir_shader *)shader->ir.nir;
 263
 264    return zink_compile_nir(zink_screen(pctx->screen), nir);
 265 }
 266
 267 static void
 268 bind_stage(struct zink_context *ctx, enum pipe_shader_type stage,
 269            struct zink_shader *shader)
 270 {
 271    assert(stage < PIPE_SHADER_COMPUTE);
 272    ctx->gfx_stages[stage] = shader;
 273    ctx->dirty |= ZINK_DIRTY_PROGRAM;
 274 }
 275
 276 static void
 277 zink_bind_vs_state(struct pipe_context *pctx,
 278                    void *cso)
 279 {
 280    bind_stage(zink_context(pctx), PIPE_SHADER_VERTEX, cso);
 281 }
 282
 283 static void
 284 zink_delete_vs_state(struct pipe_context *pctx,
 285                      void *cso)
 286 {
 287    zink_shader_free(zink_screen(pctx->screen), cso);
 288 }
 289
 290 static void *
 291 zink_create_fs_state(struct pipe_context *pctx,
 292                      const struct pipe_shader_state *shader)
 293 {
 294    struct nir_shader *nir;
 295    if (shader->type != PIPE_SHADER_IR_NIR)
 296       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 297    else
 298       nir = (struct nir_shader *)shader->ir.nir;
 299
 300    return zink_compile_nir(zink_screen(pctx->screen), nir);
 301 }
 302
 303 static void
 304 zink_bind_fs_state(struct pipe_context *pctx,
 305                    void *cso)
 306 {
 307    bind_stage(zink_context(pctx), PIPE_SHADER_FRAGMENT, cso);
 308 }
 309
 310 static void
 311 zink_delete_fs_state(struct pipe_context *pctx,
 312                      void *cso)
 313 {
 314    zink_shader_free(zink_screen(pctx->screen), cso);
 315 }
 316
 317 static void
 318 zink_set_polygon_stipple(struct pipe_context *pctx,
 319                          const struct pipe_poly_stipple *ps)
 320 {
 321 }
 322
 323 static void
 324 zink_set_vertex_buffers(struct pipe_context *pctx,
 325                         unsigned start_slot,
 326                         unsigned num_buffers,
 327                         const struct pipe_vertex_buffer *buffers)
 328 {
 329    struct zink_context *ctx = zink_context(pctx);
 330
 331    if (buffers) {
 332       for (int i = 0; i < num_buffers; ++i) {
 333          const struct pipe_vertex_buffer *vb = buffers + i;
 334          ctx->gfx_pipeline_state.bindings[start_slot + i].stride = vb->stride;
 335       }
 336    }
 337
 338    util_set_vertex_buffers_mask(ctx->buffers, &ctx->buffers_enabled_mask,
 339                                 buffers, start_slot, num_buffers);
 340 }
 341
 342 static void
 343 zink_set_viewport_states(struct pipe_context *pctx,
 344                          unsigned start_slot,
 345                          unsigned num_viewports,
 346                          const struct pipe_viewport_state *state)
 347 {
 348    struct zink_context *ctx = zink_context(pctx);
 349
 350    for (unsigned i = 0; i < num_viewports; ++i) {
 351       VkViewport viewport = {
 352          state[i].translate[0] - state[i].scale[0],
 353          state[i].translate[1] - state[i].scale[1],
 354          state[i].scale[0] * 2,
 355          state[i].scale[1] * 2,
 356          state[i].translate[2] - state[i].scale[2],
 357          state[i].translate[2] + state[i].scale[2]
 358       };
 359       ctx->viewports[start_slot + i] = viewport;
 360    }
 361    ctx->num_viewports = start_slot + num_viewports;
 362 }
 363
 364 static void
 365 zink_set_scissor_states(struct pipe_context *pctx,
 366                         unsigned start_slot, unsigned num_scissors,
 367                         const struct pipe_scissor_state *states)
 368 {
 369    struct zink_context *ctx = zink_context(pctx);
 370
 371    for (unsigned i = 0; i < num_scissors; i++) {
 372       VkRect2D scissor;
 373
 374       scissor.offset.x = states[i].minx;
 375       scissor.offset.y = states[i].miny;
 376       scissor.extent.width = states[i].maxx - states[i].minx;
 377       scissor.extent.height = states[i].maxy - states[i].miny;
 378       ctx->scissors[start_slot + i] = scissor;
 379    }
 380    ctx->num_scissors = start_slot + num_scissors;
 381 }
 382
 383 static void
 384 zink_set_constant_buffer(struct pipe_context *pctx,
 385                          enum pipe_shader_type shader, uint index,
 386                          const struct pipe_constant_buffer *cb)
 387 {
 388    struct zink_context *ctx = zink_context(pctx);
 389
 390    if (cb) {
 391       struct pipe_resource *buffer = cb->buffer;
 392       unsigned offset = cb->buffer_offset;
 393       if (cb->user_buffer)
 394          u_upload_data(ctx->base.const_uploader, 0, cb->buffer_size, 64,
 395                        cb->user_buffer, &offset, &buffer);
 396
 397       pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
 398       ctx->ubos[shader][index].buffer_offset = offset;
 399       ctx->ubos[shader][index].buffer_size = cb->buffer_size;
 400       ctx->ubos[shader][index].user_buffer = NULL;
 401
 402       if (cb->user_buffer)
 403          pipe_resource_reference(&buffer, NULL);
 404    } else {
 405       pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
 406       ctx->ubos[shader][index].buffer_offset = 0;
 407       ctx->ubos[shader][index].buffer_size = 0;
 408       ctx->ubos[shader][index].user_buffer = NULL;
 409    }
 410 }
 411
 412 static void
 413 zink_set_sampler_views(struct pipe_context *pctx,
 414                        enum pipe_shader_type shader_type,
 415                        unsigned start_slot,
 416                        unsigned num_views,
 417                        struct pipe_sampler_view **views)
 418 {
 419    struct zink_context *ctx = zink_context(pctx);
 420    assert(views);
 421    for (unsigned i = 0; i < num_views; ++i) {
 422       pipe_sampler_view_reference(
 423          &ctx->image_views[shader_type][start_slot + i],
 424          views[i]);
 425    }
 426 }
 427
 428 static void
 429 zink_set_stencil_ref(struct pipe_context *pctx,
 430                      const struct pipe_stencil_ref *ref)
 431 {
 432    struct zink_context *ctx = zink_context(pctx);
 433    ctx->stencil_ref[0] = ref->ref_value[0];
 434    ctx->stencil_ref[1] = ref->ref_value[1];
 435 }
 436
 437 static void
 438 zink_set_clip_state(struct pipe_context *pctx,
 439                     const struct pipe_clip_state *pcs)
 440 {
 441 }
 442
 443 static struct zink_render_pass *
 444 get_render_pass(struct zink_context *ctx)
 445 {
 446    struct zink_screen *screen = zink_screen(ctx->base.screen);
 447    const struct pipe_framebuffer_state *fb = &ctx->fb_state;
 448    struct zink_render_pass_state state;
 449
 450    for (int i = 0; i < fb->nr_cbufs; i++) {
 451       struct zink_resource *cbuf = zink_resource(fb->cbufs[i]->texture);
 452       state.rts[i].format = cbuf->format;
 453    }
 454    state.num_cbufs = fb->nr_cbufs;
 455
 456    if (fb->zsbuf) {
 457       struct zink_resource *zsbuf = zink_resource(fb->zsbuf->texture);
 458       state.rts[fb->nr_cbufs].format = zsbuf->format;
 459    }
 460    state.have_zsbuf = fb->zsbuf != NULL;
 461
 462    struct hash_entry *entry = _mesa_hash_table_search(ctx->render_pass_cache,
 463                                                       &state);
 464    if (!entry) {
 465       struct zink_render_pass *rp;
 466       rp = zink_create_render_pass(screen, &state);
 467       entry = _mesa_hash_table_insert(ctx->render_pass_cache, &state, rp);
 468       if (!entry)
 469          return NULL;
 470    }
 471
 472    return entry->data;
 473 }
 474
 475 static struct zink_framebuffer *
 476 get_framebuffer(struct zink_context *ctx)
 477 {
 478    struct zink_screen *screen = zink_screen(ctx->base.screen);
 479
 480    struct zink_framebuffer_state state = {};
 481    state.rp = get_render_pass(ctx);
 482    for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
 483       struct pipe_surface *psurf = ctx->fb_state.cbufs[i];
 484       state.attachments[i] = zink_surface(psurf);
 485    }
 486
 487    state.num_attachments = ctx->fb_state.nr_cbufs;
 488    if (ctx->fb_state.zsbuf) {
 489       struct pipe_surface *psurf = ctx->fb_state.zsbuf;
 490       state.attachments[state.num_attachments++] = zink_surface(psurf);
 491    }
 492
 493    state.width = ctx->fb_state.width;
 494    state.height = ctx->fb_state.height;
 495    state.layers = MAX2(ctx->fb_state.layers, 1);
 496
 497    struct hash_entry *entry = _mesa_hash_table_search(ctx->framebuffer_cache,
 498                                                       &state);
 499    if (!entry) {
 500       struct zink_framebuffer *fb = zink_create_framebuffer(screen, &state);
 501       entry = _mesa_hash_table_insert(ctx->framebuffer_cache, &state, fb);
 502       if (!entry)
 503          return NULL;
 504    }
 505
 506    return entry->data;
 507 }
 508
 509 void
 510 zink_begin_render_pass(struct zink_context *ctx, struct zink_batch *batch)
 511 {
 512    struct zink_screen *screen = zink_screen(ctx->base.screen);
 513    assert(batch == zink_context_curr_batch(ctx));
 514    assert(ctx->gfx_pipeline_state.render_pass);
 515
 516    VkRenderPassBeginInfo rpbi = {};
 517    rpbi.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO;
 518    rpbi.renderPass = ctx->gfx_pipeline_state.render_pass->render_pass;
 519    rpbi.renderArea.offset.x = 0;
 520    rpbi.renderArea.offset.y = 0;
 521    rpbi.renderArea.extent.width = ctx->fb_state.width;
 522    rpbi.renderArea.extent.height = ctx->fb_state.height;
 523    rpbi.clearValueCount = 0;
 524    rpbi.pClearValues = NULL;
 525    rpbi.framebuffer = ctx->framebuffer->fb;
 526
 527    assert(ctx->gfx_pipeline_state.render_pass && ctx->framebuffer);
 528    assert(!batch->rp || batch->rp == ctx->gfx_pipeline_state.render_pass);
 529    assert(!batch->fb || batch->fb == ctx->framebuffer);
 530
 531    zink_render_pass_reference(screen, &batch->rp, ctx->gfx_pipeline_state.render_pass);
 532    zink_framebuffer_reference(screen, &batch->fb, ctx->framebuffer);
 533
 534    vkCmdBeginRenderPass(batch->cmdbuf, &rpbi, VK_SUBPASS_CONTENTS_INLINE);
 535 }
 536
 537 static void
 538 flush_batch(struct zink_context *ctx)
 539 {
 540    struct zink_batch *batch = zink_context_curr_batch(ctx);
 541    if (batch->rp)
 542       vkCmdEndRenderPass(batch->cmdbuf);
 543
 544    zink_end_batch(ctx, batch);
 545
 546    ctx->curr_batch++;
 547    if (ctx->curr_batch == ARRAY_SIZE(ctx->batches))
 548       ctx->curr_batch = 0;
 549
 550    batch = zink_context_curr_batch(ctx);
 551    zink_start_batch(ctx, batch);
 552 }
 553
 554 static void
 555 zink_set_framebuffer_state(struct pipe_context *pctx,
 556                            const struct pipe_framebuffer_state *state)
 557 {
 558    struct zink_context *ctx = zink_context(pctx);
 559    struct zink_screen *screen = zink_screen(pctx->screen);
 560
 561    util_copy_framebuffer_state(&ctx->fb_state, state);
 562
 563    struct zink_framebuffer *fb = get_framebuffer(ctx);
 564    zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
 565    zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
 566
 567    ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
 568
 569    flush_batch(ctx);
 570    struct zink_batch *batch = zink_context_curr_batch(ctx);
 571
 572    for (int i = 0; i < state->nr_cbufs; i++) {
 573       struct zink_resource *res = zink_resource(state->cbufs[i]->texture);
 574       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 575           res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
 576          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 577                                VK_IMAGE_LAYOUT_GENERAL);
 578    }
 579
 580    if (state->zsbuf) {
 581       struct zink_resource *res = zink_resource(state->zsbuf->texture);
 582       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 583           res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
 584          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 585                                VK_IMAGE_LAYOUT_GENERAL);
 586    }
 587 }
 588
 589 static void
 590 zink_set_active_query_state(struct pipe_context *pctx, bool enable)
 591 {
 592 }
 593
 594 static void
 595 zink_set_blend_color(struct pipe_context *pctx,
 596                      const struct pipe_blend_color *color)
 597 {
 598    struct zink_context *ctx = zink_context(pctx);
 599    memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
 600 }
 601
 602 static VkAccessFlags
 603 access_flags(VkImageLayout layout)
 604 {
 605    switch (layout) {
 606    case VK_IMAGE_LAYOUT_UNDEFINED:
 607    case VK_IMAGE_LAYOUT_GENERAL:
 608       return 0;
 609
 610    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 611       return VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
 612    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 613       return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
 614
 615    case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
 616       return VK_ACCESS_SHADER_READ_BIT;
 617
 618    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 619       return VK_ACCESS_TRANSFER_READ_BIT;
 620
 621    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 622       return VK_ACCESS_TRANSFER_WRITE_BIT;
 623
 624    case VK_IMAGE_LAYOUT_PREINITIALIZED:
 625       return VK_ACCESS_HOST_WRITE_BIT;
 626
 627    default:
 628       unreachable("unexpected layout");
 629    }
 630 }
 631
 632 void
 633 zink_resource_barrier(VkCommandBuffer cmdbuf, struct zink_resource *res,
 634                       VkImageAspectFlags aspect, VkImageLayout new_layout)
 635 {
 636    VkImageSubresourceRange isr = {
 637       aspect,
 638       0, VK_REMAINING_MIP_LEVELS,
 639       0, VK_REMAINING_ARRAY_LAYERS
 640    };
 641
 642    VkImageMemoryBarrier imb = {
 643       VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
 644       NULL,
 645       access_flags(res->layout),
 646       access_flags(new_layout),
 647       res->layout,
 648       new_layout,
 649       VK_QUEUE_FAMILY_IGNORED,
 650       VK_QUEUE_FAMILY_IGNORED,
 651       res->image,
 652       isr
 653    };
 654    vkCmdPipelineBarrier(
 655       cmdbuf,
 656       VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
 657       VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
 658       0,
 659       0, NULL,
 660       0, NULL,
 661       1, &imb
 662    );
 663
 664    res->layout = new_layout;
 665 }
 666
 667 static void
 668 zink_clear(struct pipe_context *pctx,
 669            unsigned buffers,
 670            const union pipe_color_union *pcolor,
 671            double depth, unsigned stencil)
 672 {
 673    struct zink_context *ctx = zink_context(pctx);
 674    struct pipe_framebuffer_state *fb = &ctx->fb_state;
 675
 676    struct zink_batch *batch = zink_context_curr_batch(ctx);
 677
 678    VkClearAttachment attachments[1 + PIPE_MAX_COLOR_BUFS];
 679    int num_attachments = 0;
 680
 681    if (buffers & PIPE_CLEAR_COLOR) {
 682       VkClearColorValue color;
 683       color.float32[0] = pcolor->f[0];
 684       color.float32[1] = pcolor->f[1];
 685       color.float32[2] = pcolor->f[2];
 686       color.float32[3] = pcolor->f[3];
 687
 688       for (unsigned i = 0; i < fb->nr_cbufs; i++) {
 689          if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
 690             continue;
 691
 692          attachments[num_attachments].aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
 693          attachments[num_attachments].colorAttachment = i;
 694          attachments[num_attachments].clearValue.color = color;
 695          ++num_attachments;
 696       }
 697    }
 698
 699    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && fb->zsbuf) {
 700       VkImageAspectFlags aspect = 0;
 701       if (buffers & PIPE_CLEAR_DEPTH)
 702          aspect |= VK_IMAGE_ASPECT_DEPTH_BIT;
 703       if (buffers & PIPE_CLEAR_STENCIL)
 704          aspect |= VK_IMAGE_ASPECT_STENCIL_BIT;
 705
 706       attachments[num_attachments].aspectMask = aspect;
 707       attachments[num_attachments].clearValue.depthStencil.depth = depth;
 708       attachments[num_attachments].clearValue.depthStencil.stencil = stencil;
 709       ++num_attachments;
 710    }
 711
 712    unsigned num_layers = util_framebuffer_get_num_layers(fb);
 713    VkClearRect rects[PIPE_MAX_VIEWPORTS];
 714    uint32_t num_rects;
 715    if (ctx->num_scissors) {
 716       for (unsigned i = 0 ; i < ctx->num_scissors; ++i) {
 717          rects[i].rect = ctx->scissors[i];
 718          rects[i].baseArrayLayer = 0;
 719          rects[i].layerCount = num_layers;
 720       }
 721       num_rects = ctx->num_scissors;
 722    } else {
 723       rects[0].rect.offset.x = 0;
 724       rects[0].rect.offset.y = 0;
 725       rects[0].rect.extent.width = fb->width;
 726       rects[0].rect.extent.height = fb->height;
 727       rects[0].baseArrayLayer = 0;
 728       rects[0].layerCount = num_layers;
 729       num_rects = 1;
 730    }
 731
 732    if (!batch->rp)
 733       zink_begin_render_pass(ctx, batch);
 734
 735    vkCmdClearAttachments(batch->cmdbuf,
 736                          num_attachments, attachments,
 737                          num_rects, rects);
 738 }
 739
 740 VkShaderStageFlagBits
 741 zink_shader_stage(enum pipe_shader_type type)
 742 {
 743    VkShaderStageFlagBits stages[] = {
 744       [PIPE_SHADER_VERTEX] = VK_SHADER_STAGE_VERTEX_BIT,
 745       [PIPE_SHADER_FRAGMENT] = VK_SHADER_STAGE_FRAGMENT_BIT,
 746       [PIPE_SHADER_GEOMETRY] = VK_SHADER_STAGE_GEOMETRY_BIT,
 747       [PIPE_SHADER_TESS_CTRL] = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
 748       [PIPE_SHADER_TESS_EVAL] = VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
 749       [PIPE_SHADER_COMPUTE] = VK_SHADER_STAGE_COMPUTE_BIT,
 750    };
 751    return stages[type];
 752 }
 753
 754 static VkDescriptorSet
 755 allocate_descriptor_set(struct zink_context *ctx, VkDescriptorSetLayout dsl)
 756 {
 757    struct zink_screen *screen = zink_screen(ctx->base.screen);
 758    VkDescriptorSetAllocateInfo dsai;
 759    memset((void *)&dsai, 0, sizeof(dsai));
 760    dsai.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO;
 761    dsai.pNext = NULL;
 762    dsai.descriptorPool = ctx->descpool;
 763    dsai.descriptorSetCount = 1;
 764    dsai.pSetLayouts = &dsl;
 765
 766    VkDescriptorSet desc_set;
 767    if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
 768
 769       /* if we run out of descriptor sets we either need to create a bunch
 770        * more... or flush and wait. For simplicity, let's flush for now.
 771        */
 772       struct pipe_fence_handle *fence = NULL;
 773       ctx->base.flush(&ctx->base, &fence, 0);
 774       ctx->base.screen->fence_finish(ctx->base.screen, &ctx->base, fence,
 775                                      PIPE_TIMEOUT_INFINITE);
 776
 777       if (vkResetDescriptorPool(screen->dev, ctx->descpool, 0) != VK_SUCCESS) {
 778          fprintf(stderr, "vkResetDescriptorPool failed\n");
 779          return VK_NULL_HANDLE;
 780       }
 781       if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
 782          fprintf(stderr, "vkAllocateDescriptorSets failed\n");
 783          return VK_NULL_HANDLE;
 784       }
 785    }
 786
 787    return desc_set;
 788 }
 789
 790 static void
 791 zink_bind_vertex_buffers(struct zink_batch *batch, struct zink_context *ctx)
 792 {
 793    VkBuffer buffers[PIPE_MAX_ATTRIBS];
 794    VkDeviceSize buffer_offsets[PIPE_MAX_ATTRIBS];
 795    const struct zink_vertex_elements_state *elems = ctx->element_state;
 796    for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) {
 797       struct pipe_vertex_buffer *vb = ctx->buffers + ctx->element_state->binding_map[i];
 798       assert(vb && vb->buffer.resource);
 799       struct zink_resource *res = zink_resource(vb->buffer.resource);
 800       buffers[i] = res->buffer;
 801       buffer_offsets[i] = vb->buffer_offset;
 802       zink_batch_reference_resoure(batch, res);
 803    }
 804
 805    if (elems->hw_state.num_bindings > 0)
 806       vkCmdBindVertexBuffers(batch->cmdbuf, 0,
 807                              elems->hw_state.num_bindings,
 808                              buffers, buffer_offsets);
 809 }
 810
 811 static uint32_t
 812 hash_gfx_program(const void *key)
 813 {
 814    return _mesa_hash_data(key, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1));
 815 }
 816
 817 static bool
 818 equals_gfx_program(const void *a, const void *b)
 819 {
 820    return memcmp(a, b, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1)) == 0;
 821 }
 822
 823 static uint32_t
 824 hash_render_pass_state(const void *key)
 825 {
 826    return _mesa_hash_data(key, sizeof(struct zink_render_pass_state));
 827 }
 828
 829 static bool
 830 equals_render_pass_state(const void *a, const void *b)
 831 {
 832    return memcmp(a, b, sizeof(struct zink_render_pass_state)) == 0;
 833 }
 834
 835 static uint32_t
 836 hash_framebuffer_state(const void *key)
 837 {
 838    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)key;
 839    return _mesa_hash_data(key, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments);
 840 }
 841
 842 static bool
 843 equals_framebuffer_state(const void *a, const void *b)
 844 {
 845    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)a;
 846    return memcmp(a, b, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments) == 0;
 847 }
 848
 849 static struct zink_gfx_program *
 850 get_gfx_program(struct zink_context *ctx)
 851 {
 852    if (ctx->dirty & ZINK_DIRTY_PROGRAM) {
 853       struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
 854                                                          ctx->gfx_stages);
 855       if (!entry) {
 856          struct zink_gfx_program *prog;
 857          prog = zink_create_gfx_program(zink_screen(ctx->base.screen)->dev,
 858                                                      ctx->gfx_stages);
 859          entry = _mesa_hash_table_insert(ctx->program_cache, prog->stages, prog);
 860          if (!entry)
 861             return NULL;
 862       }
 863       ctx->curr_program = entry->data;
 864       ctx->dirty &= ~ZINK_DIRTY_PROGRAM;
 865    }
 866
 867    assert(ctx->curr_program);
 868    return ctx->curr_program;
 869 }
 870
 871 static void
 872 zink_draw_vbo(struct pipe_context *pctx,
 873               const struct pipe_draw_info *dinfo)
 874 {
 875    struct zink_context *ctx = zink_context(pctx);
 876    struct zink_screen *screen = zink_screen(pctx->screen);
 877    struct zink_rasterizer_state *rast_state = ctx->rast_state;
 878
 879    if (dinfo->mode >= PIPE_PRIM_QUADS ||
 880        dinfo->mode == PIPE_PRIM_LINE_LOOP) {
 881       if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&dinfo->count))
 882          return;
 883
 884       util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
 885       util_primconvert_draw_vbo(ctx->primconvert, dinfo);
 886       return;
 887    }
 888
 889    struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
 890    if (!gfx_program)
 891       return;
 892
 893    VkPipeline pipeline = zink_get_gfx_pipeline(screen->dev, gfx_program,
 894                                                &ctx->gfx_pipeline_state,
 895                                                dinfo->mode);
 896
 897    bool depth_bias = false;
 898    switch (u_reduced_prim(dinfo->mode)) {
 899    case PIPE_PRIM_POINTS:
 900       depth_bias = rast_state->offset_point;
 901       break;
 902
 903    case PIPE_PRIM_LINES:
 904       depth_bias = rast_state->offset_line;
 905       break;
 906
 907    case PIPE_PRIM_TRIANGLES:
 908       depth_bias = rast_state->offset_tri;
 909       break;
 910
 911    default:
 912       unreachable("unexpected reduced prim");
 913    }
 914
 915    unsigned index_offset = 0;
 916    struct pipe_resource *index_buffer = NULL;
 917    if (dinfo->index_size > 0) {
 918       if (dinfo->has_user_indices) {
 919          if (!util_upload_index_buffer(pctx, dinfo, &index_buffer, &index_offset)) {
 920             debug_printf("util_upload_index_buffer() failed\n");
 921             return;
 922          }
 923       } else
 924          index_buffer = dinfo->index.resource;
 925    }
 926
 927    VkDescriptorSet desc_set = allocate_descriptor_set(ctx, gfx_program->dsl);
 928
 929    struct zink_batch *batch = zink_context_curr_batch(ctx);
 930
 931    VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS + PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 932    VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS];
 933    VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 934    int num_wds = 0, num_buffer_info = 0, num_image_info = 0;
 935
 936    struct zink_resource *transitions[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 937    int num_transitions = 0;
 938
 939    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
 940       struct zink_shader *shader = ctx->gfx_stages[i];
 941       if (!shader)
 942          continue;
 943
 944       for (int j = 0; j < shader->num_bindings; j++) {
 945          int index = shader->bindings[j].index;
 946          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
 947             assert(ctx->ubos[i][index].buffer_size > 0);
 948             assert(ctx->ubos[i][index].buffer);
 949             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
 950             buffer_infos[num_buffer_info].buffer = res->buffer;
 951             buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset;
 952             buffer_infos[num_buffer_info].range  = VK_WHOLE_SIZE;
 953             wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info;
 954             ++num_buffer_info;
 955             zink_batch_reference_resoure(batch, res);
 956          } else {
 957             struct pipe_sampler_view *psampler_view = ctx->image_views[i][index];
 958             assert(psampler_view);
 959             struct zink_sampler_view *sampler_view = zink_sampler_view(psampler_view);
 960
 961             struct zink_resource *res = zink_resource(psampler_view->texture);
 962             VkImageLayout layout = res->layout;
 963             if (layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL &&
 964                 layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL &&
 965                 layout != VK_IMAGE_LAYOUT_GENERAL) {
 966                transitions[num_transitions++] = res;
 967                layout = VK_IMAGE_LAYOUT_GENERAL;
 968             }
 969             image_infos[num_image_info].imageLayout = layout;
 970             image_infos[num_image_info].imageView = sampler_view->image_view;
 971             image_infos[num_image_info].sampler = ctx->samplers[i][index];
 972             wds[num_wds].pImageInfo = image_infos + num_image_info;
 973             ++num_image_info;
 974             zink_batch_reference_sampler_view(batch, sampler_view);
 975          }
 976
 977          wds[num_wds].sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET;
 978          wds[num_wds].pNext = NULL;
 979          wds[num_wds].dstBinding = shader->bindings[j].binding;
 980          wds[num_wds].dstArrayElement = 0;
 981          wds[num_wds].descriptorCount = 1;
 982          wds[num_wds].descriptorType = shader->bindings[j].type;
 983          ++num_wds;
 984       }
 985    }
 986
 987    if (num_transitions > 0) {
 988       if (batch->rp)
 989          vkCmdEndRenderPass(batch->cmdbuf);
 990
 991       for (int i = 0; i < num_transitions; ++i)
 992          zink_resource_barrier(batch->cmdbuf, transitions[i],
 993                                transitions[i]->aspect,
 994                                VK_IMAGE_LAYOUT_GENERAL);
 995
 996       zink_begin_render_pass(ctx, batch);
 997    } else if (!batch->rp)
 998       zink_begin_render_pass(ctx, batch);
 999
1000
1001    vkCmdSetViewport(batch->cmdbuf, 0, ctx->num_viewports, ctx->viewports);
1002
1003    if (ctx->num_scissors)
1004       vkCmdSetScissor(batch->cmdbuf, 0, ctx->num_scissors, ctx->scissors);
1005    else if (ctx->fb_state.width && ctx->fb_state.height) {
1006       VkRect2D fb_scissor = {};
1007       fb_scissor.extent.width = ctx->fb_state.width;
1008       fb_scissor.extent.height = ctx->fb_state.height;
1009       vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
1010    }
1011
1012    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref[0]);
1013    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref[1]);
1014
1015    if (depth_bias)
1016       vkCmdSetDepthBias(batch->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
1017    else
1018       vkCmdSetDepthBias(batch->cmdbuf, 0.0f, 0.0f, 0.0f);
1019
1020    if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
1021       vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
1022
1023    for (int i = 0; i < num_wds; ++i)
1024       wds[i].dstSet = desc_set;
1025
1026    vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
1027
1028    vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
1029    vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
1030                            gfx_program->layout, 0, 1, &desc_set, 0, NULL);
1031    zink_bind_vertex_buffers(batch, ctx);
1032
1033    if (dinfo->index_size > 0) {
1034       assert(dinfo->index_size != 1);
1035       VkIndexType index_type = dinfo->index_size == 2 ? VK_INDEX_TYPE_UINT16 : VK_INDEX_TYPE_UINT32;
1036       struct zink_resource *res = zink_resource(index_buffer);
1037       vkCmdBindIndexBuffer(batch->cmdbuf, res->buffer, index_offset, index_type);
1038       zink_batch_reference_resoure(batch, res);
1039       vkCmdDrawIndexed(batch->cmdbuf,
1040          dinfo->count, dinfo->instance_count,
1041          dinfo->start, dinfo->index_bias, dinfo->start_instance);
1042    } else
1043       vkCmdDraw(batch->cmdbuf, dinfo->count, dinfo->instance_count, dinfo->start, dinfo->start_instance);
1044
1045    if (dinfo->index_size > 0 && dinfo->has_user_indices)
1046       pipe_resource_reference(&index_buffer, NULL);
1047 }
1048
1049 static void
1050 zink_flush(struct pipe_context *pctx,
1051            struct pipe_fence_handle **pfence,
1052            enum pipe_flush_flags flags)
1053 {
1054    struct zink_context *ctx = zink_context(pctx);
1055
1056    struct zink_batch *batch = zink_context_curr_batch(ctx);
1057    flush_batch(ctx);
1058
1059    if (pfence)
1060       zink_fence_reference(zink_screen(pctx->screen),
1061                            (struct zink_fence **)pfence,
1062                            batch->fence);
1063
1064    if (flags & PIPE_FLUSH_END_OF_FRAME)
1065       pctx->screen->fence_finish(pctx->screen, pctx,
1066                                  (struct pipe_fence_handle *)batch->fence,
1067                                  PIPE_TIMEOUT_INFINITE);
1068 }
1069
1070 static void
1071 zink_blit(struct pipe_context *pctx,
1072           const struct pipe_blit_info *info)
1073 {
1074    struct zink_context *ctx = zink_context(pctx);
1075    bool is_resolve = false;
1076    if (info->mask != PIPE_MASK_RGBA ||
1077        info->scissor_enable ||
1078        info->alpha_blend) {
1079       if (!util_blitter_is_blit_supported(ctx->blitter, info)) {
1080          debug_printf("blit unsupported %s -> %s\n",
1081                  util_format_short_name(info->src.resource->format),
1082                  util_format_short_name(info->dst.resource->format));
1083          return;
1084       }
1085
1086       util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[PIPE_SHADER_FRAGMENT]);
1087       util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->buffers);
1088       util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
1089       util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
1090       util_blitter_save_rasterizer(ctx->blitter, ctx->gfx_pipeline_state.rast_state);
1091
1092       util_blitter_blit(ctx->blitter, info);
1093       return;
1094    }
1095
1096    struct zink_resource *src = zink_resource(info->src.resource);
1097    struct zink_resource *dst = zink_resource(info->dst.resource);
1098
1099    if (src->base.nr_samples > 1 && dst->base.nr_samples <= 1)
1100       is_resolve = true;
1101
1102    struct zink_batch *batch = zink_context_curr_batch(ctx);
1103    if (batch->rp)
1104       vkCmdEndRenderPass(batch->cmdbuf);
1105
1106    zink_batch_reference_resoure(batch, src);
1107    zink_batch_reference_resoure(batch, dst);
1108
1109    if (is_resolve) {
1110       VkImageResolve region = {};
1111
1112       region.srcSubresource.aspectMask = src->aspect;
1113       region.srcSubresource.mipLevel = info->src.level;
1114       region.srcSubresource.baseArrayLayer = 0; // no clue
1115       region.srcSubresource.layerCount = 1; // no clue
1116       region.srcOffset.x = info->src.box.x;
1117       region.srcOffset.y = info->src.box.y;
1118       region.srcOffset.z = info->src.box.z;
1119
1120       region.dstSubresource.aspectMask = dst->aspect;
1121       region.dstSubresource.mipLevel = info->dst.level;
1122       region.dstSubresource.baseArrayLayer = 0; // no clue
1123       region.dstSubresource.layerCount = 1; // no clue
1124       region.dstOffset.x = info->dst.box.x;
1125       region.dstOffset.y = info->dst.box.y;
1126       region.dstOffset.z = info->dst.box.z;
1127
1128       region.extent.width = info->dst.box.width;
1129       region.extent.height = info->dst.box.height;
1130       region.extent.depth = info->dst.box.depth;
1131       vkCmdResolveImage(batch->cmdbuf, src->image, src->layout,
1132                         dst->image, dst->layout,
1133                         1, &region);
1134
1135    } else {
1136       if (dst->layout != VK_IMAGE_LAYOUT_GENERAL &&
1137           dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL)
1138          zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1139                                VK_IMAGE_LAYOUT_GENERAL);
1140
1141       VkImageBlit region = {};
1142       region.srcSubresource.aspectMask = src->aspect;
1143       region.srcSubresource.mipLevel = info->src.level;
1144       region.srcOffsets[0].x = info->src.box.x;
1145       region.srcOffsets[0].y = info->src.box.y;
1146       region.srcOffsets[1].x = info->src.box.x + info->src.box.width;
1147       region.srcOffsets[1].y = info->src.box.y + info->src.box.height;
1148
1149       if (src->base.array_size > 1) {
1150          region.srcOffsets[0].z = 0;
1151          region.srcOffsets[1].z = 1;
1152          region.srcSubresource.baseArrayLayer = info->src.box.z;
1153          region.srcSubresource.layerCount = info->src.box.depth;
1154       } else {
1155          region.srcOffsets[0].z = info->src.box.z;
1156          region.srcOffsets[1].z = info->src.box.z + info->src.box.depth;
1157          region.srcSubresource.baseArrayLayer = 0;
1158          region.srcSubresource.layerCount = 1;
1159       }
1160
1161       region.dstSubresource.aspectMask = dst->aspect;
1162       region.dstSubresource.mipLevel = info->dst.level;
1163       region.dstOffsets[0].x = info->dst.box.x;
1164       region.dstOffsets[0].y = info->dst.box.y;
1165       region.dstOffsets[1].x = info->dst.box.x + info->dst.box.width;
1166       region.dstOffsets[1].y = info->dst.box.y + info->dst.box.height;
1167
1168       if (dst->base.array_size > 1) {
1169          region.dstOffsets[0].z = 0;
1170          region.dstOffsets[1].z = 1;
1171          region.dstSubresource.baseArrayLayer = info->dst.box.z;
1172          region.dstSubresource.layerCount = info->dst.box.depth;
1173       } else {
1174          region.dstOffsets[0].z = info->dst.box.z;
1175          region.dstOffsets[1].z = info->dst.box.z + info->dst.box.depth;
1176          region.dstSubresource.baseArrayLayer = 0;
1177          region.dstSubresource.layerCount = 1;
1178       }
1179
1180       vkCmdBlitImage(batch->cmdbuf, src->image, src->layout,
1181                      dst->image, dst->layout,
1182                      1, &region,
1183                      filter(info->filter));
1184    }
1185
1186    if (batch->rp)
1187       zink_begin_render_pass(ctx, batch);
1188
1189    /* HACK: I have no idea why this is needed, but without it ioquake3
1190     * randomly keeps fading to black.
1191     */
1192    flush_batch(ctx);
1193 }
1194
1195 static void
1196 zink_flush_resource(struct pipe_context *pipe,
1197                     struct pipe_resource *resource)
1198 {
1199 }
1200
1201 static void
1202 zink_resource_copy_region(struct pipe_context *pctx,
1203                           struct pipe_resource *pdst,
1204                           unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1205                           struct pipe_resource *psrc,
1206                           unsigned src_level, const struct pipe_box *src_box)
1207 {
1208    struct zink_resource *dst = zink_resource(pdst);
1209    struct zink_resource *src = zink_resource(psrc);
1210    struct zink_context *ctx = zink_context(pctx);
1211    if (dst->base.target != PIPE_BUFFER && src->base.target != PIPE_BUFFER) {
1212       VkImageCopy region = {};
1213
1214       region.srcSubresource.aspectMask = src->aspect;
1215       region.srcSubresource.mipLevel = src_level;
1216       region.srcSubresource.layerCount = 1;
1217       if (src->base.array_size > 1) {
1218          region.srcSubresource.baseArrayLayer = src_box->z;
1219          region.srcSubresource.layerCount = src_box->depth;
1220          region.extent.depth = 1;
1221       } else {
1222          region.srcOffset.z = src_box->z;
1223          region.srcSubresource.layerCount = 1;
1224          region.extent.depth = src_box->depth;
1225       }
1226
1227       region.srcOffset.x = src_box->x;
1228       region.srcOffset.y = src_box->y;
1229
1230       region.dstSubresource.aspectMask = dst->aspect;
1231       region.dstSubresource.mipLevel = dst_level;
1232       if (dst->base.array_size > 1) {
1233          region.dstSubresource.baseArrayLayer = dstz;
1234          region.dstSubresource.layerCount = src_box->depth;
1235       } else {
1236          region.dstOffset.z = dstz;
1237          region.dstSubresource.layerCount = 1;
1238       }
1239
1240       region.dstOffset.x = dstx;
1241       region.dstOffset.y = dsty;
1242       region.extent.width = src_box->width;
1243       region.extent.height = src_box->height;
1244
1245       struct zink_batch *batch = zink_context_curr_batch(ctx);
1246       zink_batch_reference_resoure(batch, src);
1247       zink_batch_reference_resoure(batch, dst);
1248
1249       vkCmdCopyImage(batch->cmdbuf, src->image, src->layout,
1250                      dst->image, dst->layout,
1251                      1, &region);
1252    } else
1253       debug_printf("zink: TODO resource copy\n");
1254 }
1255
1256 struct pipe_context *
1257 zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
1258 {
1259    struct zink_screen *screen = zink_screen(pscreen);
1260    struct zink_context *ctx = CALLOC_STRUCT(zink_context);
1261
1262    ctx->base.screen = pscreen;
1263    ctx->base.priv = priv;
1264
1265    ctx->base.destroy = zink_context_destroy;
1266
1267    zink_context_state_init(&ctx->base);
1268
1269    ctx->base.create_sampler_state = zink_create_sampler_state;
1270    ctx->base.bind_sampler_states = zink_bind_sampler_states;
1271    ctx->base.delete_sampler_state = zink_delete_sampler_state;
1272
1273    ctx->base.create_sampler_view = zink_create_sampler_view;
1274    ctx->base.set_sampler_views = zink_set_sampler_views;
1275    ctx->base.sampler_view_destroy = zink_destroy_sampler_view;
1276
1277    ctx->base.create_vs_state = zink_create_vs_state;
1278    ctx->base.bind_vs_state = zink_bind_vs_state;
1279    ctx->base.delete_vs_state = zink_delete_vs_state;
1280
1281    ctx->base.create_fs_state = zink_create_fs_state;
1282    ctx->base.bind_fs_state = zink_bind_fs_state;
1283    ctx->base.delete_fs_state = zink_delete_fs_state;
1284
1285    ctx->base.set_polygon_stipple = zink_set_polygon_stipple;
1286    ctx->base.set_vertex_buffers = zink_set_vertex_buffers;
1287    ctx->base.set_viewport_states = zink_set_viewport_states;
1288    ctx->base.set_scissor_states = zink_set_scissor_states;
1289    ctx->base.set_constant_buffer = zink_set_constant_buffer;
1290    ctx->base.set_framebuffer_state = zink_set_framebuffer_state;
1291    ctx->base.set_stencil_ref = zink_set_stencil_ref;
1292    ctx->base.set_clip_state = zink_set_clip_state;
1293    ctx->base.set_active_query_state = zink_set_active_query_state;
1294    ctx->base.set_blend_color = zink_set_blend_color;
1295
1296    ctx->base.clear = zink_clear;
1297    ctx->base.draw_vbo = zink_draw_vbo;
1298    ctx->base.flush = zink_flush;
1299
1300    ctx->base.resource_copy_region = zink_resource_copy_region;
1301    ctx->base.blit = zink_blit;
1302
1303    ctx->base.flush_resource = zink_flush_resource;
1304    zink_context_surface_init(&ctx->base);
1305    zink_context_resource_init(&ctx->base);
1306    zink_context_query_init(&ctx->base);
1307
1308    slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
1309
1310    ctx->base.stream_uploader = u_upload_create_default(&ctx->base);
1311    ctx->base.const_uploader = ctx->base.stream_uploader;
1312
1313    int prim_hwsupport = 1 << PIPE_PRIM_POINTS |
1314                         1 << PIPE_PRIM_LINES |
1315                         1 << PIPE_PRIM_LINE_STRIP |
1316                         1 << PIPE_PRIM_TRIANGLES |
1317                         1 << PIPE_PRIM_TRIANGLE_STRIP |
1318                         1 << PIPE_PRIM_TRIANGLE_FAN;
1319
1320    ctx->primconvert = util_primconvert_create(&ctx->base, prim_hwsupport);
1321    if (!ctx->primconvert)
1322       goto fail;
1323
1324    ctx->blitter = util_blitter_create(&ctx->base);
1325    if (!ctx->blitter)
1326       goto fail;
1327
1328    VkCommandPoolCreateInfo cpci = {};
1329    cpci.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO;
1330    cpci.queueFamilyIndex = screen->gfx_queue;
1331    cpci.flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT;
1332    if (vkCreateCommandPool(screen->dev, &cpci, NULL, &ctx->cmdpool) != VK_SUCCESS)
1333       goto fail;
1334
1335    VkCommandBufferAllocateInfo cbai = {};
1336    cbai.sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO;
1337    cbai.commandPool = ctx->cmdpool;
1338    cbai.level = VK_COMMAND_BUFFER_LEVEL_PRIMARY;
1339    cbai.commandBufferCount = 1;
1340    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i) {
1341       if (vkAllocateCommandBuffers(screen->dev, &cbai, &ctx->batches[i].cmdbuf) != VK_SUCCESS)
1342          goto fail;
1343
1344       ctx->batches[i].resources = _mesa_set_create(NULL, _mesa_hash_pointer,
1345                                                    _mesa_key_pointer_equal);
1346       ctx->batches[i].sampler_views = _mesa_set_create(NULL,
1347                                                        _mesa_hash_pointer,
1348                                                        _mesa_key_pointer_equal);
1349
1350       if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views)
1351          goto fail;
1352
1353       util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL);
1354    }
1355
1356    VkDescriptorPoolSize sizes[] = {
1357       {VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER, 1000}
1358    };
1359    VkDescriptorPoolCreateInfo dpci = {};
1360    dpci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO;
1361    dpci.pPoolSizes = sizes;
1362    dpci.poolSizeCount = ARRAY_SIZE(sizes);
1363    dpci.flags = VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT;
1364    dpci.maxSets = 1000;
1365
1366    if(vkCreateDescriptorPool(screen->dev, &dpci, 0, &ctx->descpool) != VK_SUCCESS)
1367       goto fail;
1368
1369    vkGetDeviceQueue(screen->dev, screen->gfx_queue, 0, &ctx->queue);
1370
1371    ctx->program_cache = _mesa_hash_table_create(NULL,
1372                                                 hash_gfx_program,
1373                                                 equals_gfx_program);
1374    ctx->render_pass_cache = _mesa_hash_table_create(NULL,
1375                                                     hash_render_pass_state,
1376                                                     equals_render_pass_state);
1377    ctx->framebuffer_cache = _mesa_hash_table_create(NULL,
1378                                                     hash_framebuffer_state,
1379                                                     equals_framebuffer_state);
1380
1381    if (!ctx->program_cache || !ctx->render_pass_cache ||
1382        !ctx->framebuffer_cache)
1383       goto fail;
1384
1385    ctx->dirty = ZINK_DIRTY_PROGRAM;
1386
1387    /* start the first batch */
1388    zink_start_batch(ctx, zink_context_curr_batch(ctx));
1389
1390    return &ctx->base;
1391
1392 fail:
1393    if (ctx) {
1394       vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
1395       FREE(ctx);
1396    }
1397    return NULL;
1398 }