src/gallium/drivers/zink/zink_context.c

   1 /*
   2  * Copyright 2018 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "zink_context.h"
  25
  26 #include "zink_batch.h"
  27 #include "zink_compiler.h"
  28 #include "zink_fence.h"
  29 #include "zink_framebuffer.h"
  30 #include "zink_pipeline.h"
  31 #include "zink_program.h"
  32 #include "zink_render_pass.h"
  33 #include "zink_resource.h"
  34 #include "zink_screen.h"
  35 #include "zink_state.h"
  36 #include "zink_surface.h"
  37
  38 #include "indices/u_primconvert.h"
  39 #include "util/u_blitter.h"
  40 #include "util/u_debug.h"
  41 #include "util/u_format.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45
  46 #include "nir.h"
  47
  48 #include "util/u_memory.h"
  49 #include "util/u_prim.h"
  50 #include "util/u_upload_mgr.h"
  51
  52 static void
  53 zink_context_destroy(struct pipe_context *pctx)
  54 {
  55    struct zink_context *ctx = zink_context(pctx);
  56    struct zink_screen *screen = zink_screen(pctx->screen);
  57
  58    if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS)
  59       debug_printf("vkQueueWaitIdle failed\n");
  60
  61    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i)
  62       vkFreeCommandBuffers(screen->dev, ctx->cmdpool, 1, &ctx->batches[i].cmdbuf);
  63    vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
  64
  65    util_primconvert_destroy(ctx->primconvert);
  66    u_upload_destroy(pctx->stream_uploader);
  67    slab_destroy_child(&ctx->transfer_pool);
  68    util_blitter_destroy(ctx->blitter);
  69    FREE(ctx);
  70 }
  71
  72 static VkFilter
  73 filter(enum pipe_tex_filter filter)
  74 {
  75    switch (filter) {
  76    case PIPE_TEX_FILTER_NEAREST: return VK_FILTER_NEAREST;
  77    case PIPE_TEX_FILTER_LINEAR: return VK_FILTER_LINEAR;
  78    }
  79    unreachable("unexpected filter");
  80 }
  81
  82 static VkSamplerMipmapMode
  83 sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
  84 {
  85    switch (filter) {
  86    case PIPE_TEX_MIPFILTER_NEAREST: return VK_SAMPLER_MIPMAP_MODE_NEAREST;
  87    case PIPE_TEX_MIPFILTER_LINEAR: return VK_SAMPLER_MIPMAP_MODE_LINEAR;
  88    case PIPE_TEX_MIPFILTER_NONE:
  89       unreachable("PIPE_TEX_MIPFILTER_NONE should be dealt with earlier");
  90    }
  91    unreachable("unexpected filter");
  92 }
  93
  94 static VkSamplerAddressMode
  95 sampler_address_mode(enum pipe_tex_wrap filter)
  96 {
  97    switch (filter) {
  98    case PIPE_TEX_WRAP_REPEAT: return VK_SAMPLER_ADDRESS_MODE_REPEAT;
  99    case PIPE_TEX_WRAP_CLAMP: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 100    case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE;
 101    case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
 102    case PIPE_TEX_WRAP_MIRROR_REPEAT: return VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT;
 103    case PIPE_TEX_WRAP_MIRROR_CLAMP: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 104    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE;
 105    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 106    }
 107    unreachable("unexpected wrap");
 108 }
 109
 110 static VkCompareOp
 111 compare_op(enum pipe_compare_func op)
 112 {
 113    switch (op) {
 114       case PIPE_FUNC_NEVER: return VK_COMPARE_OP_NEVER;
 115       case PIPE_FUNC_LESS: return VK_COMPARE_OP_LESS;
 116       case PIPE_FUNC_EQUAL: return VK_COMPARE_OP_EQUAL;
 117       case PIPE_FUNC_LEQUAL: return VK_COMPARE_OP_LESS_OR_EQUAL;
 118       case PIPE_FUNC_GREATER: return VK_COMPARE_OP_GREATER;
 119       case PIPE_FUNC_NOTEQUAL: return VK_COMPARE_OP_NOT_EQUAL;
 120       case PIPE_FUNC_GEQUAL: return VK_COMPARE_OP_GREATER_OR_EQUAL;
 121       case PIPE_FUNC_ALWAYS: return VK_COMPARE_OP_ALWAYS;
 122    }
 123    unreachable("unexpected compare");
 124 }
 125
 126 static void *
 127 zink_create_sampler_state(struct pipe_context *pctx,
 128                           const struct pipe_sampler_state *state)
 129 {
 130    struct zink_screen *screen = zink_screen(pctx->screen);
 131
 132    VkSamplerCreateInfo sci = {};
 133    sci.sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO;
 134    sci.magFilter = filter(state->mag_img_filter);
 135    sci.minFilter = filter(state->min_img_filter);
 136
 137    if (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 138       sci.mipmapMode = sampler_mipmap_mode(state->min_mip_filter);
 139       sci.minLod = state->min_lod;
 140       sci.maxLod = state->max_lod;
 141    } else {
 142       sci.mipmapMode = VK_SAMPLER_MIPMAP_MODE_NEAREST;
 143       sci.minLod = 0;
 144       sci.maxLod = 0;
 145    }
 146
 147    sci.addressModeU = sampler_address_mode(state->wrap_s);
 148    sci.addressModeV = sampler_address_mode(state->wrap_t);
 149    sci.addressModeW = sampler_address_mode(state->wrap_r);
 150    sci.mipLodBias = state->lod_bias;
 151
 152    if (state->compare_mode == PIPE_TEX_COMPARE_NONE)
 153       sci.compareOp = VK_COMPARE_OP_NEVER;
 154    else
 155       sci.compareOp = compare_op(state->compare_func);
 156
 157    sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO
 158    sci.unnormalizedCoordinates = !state->normalized_coords;
 159
 160    if (state->max_anisotropy > 1) {
 161       sci.maxAnisotropy = state->max_anisotropy;
 162       sci.anisotropyEnable = VK_TRUE;
 163    }
 164
 165    VkSampler sampler;
 166    VkResult err = vkCreateSampler(screen->dev, &sci, NULL, &sampler);
 167    if (err != VK_SUCCESS)
 168       return NULL;
 169
 170    return sampler;
 171 }
 172
 173 static void
 174 zink_bind_sampler_states(struct pipe_context *pctx,
 175                          enum pipe_shader_type shader,
 176                          unsigned start_slot,
 177                          unsigned num_samplers,
 178                          void **samplers)
 179 {
 180    struct zink_context *ctx = zink_context(pctx);
 181    for (unsigned i = 0; i < num_samplers; ++i)
 182       ctx->samplers[shader][start_slot + i] = (VkSampler)samplers[i];
 183    ctx->num_samplers[shader] = start_slot + num_samplers;
 184 }
 185
 186 static void
 187 zink_delete_sampler_state(struct pipe_context *pctx,
 188                           void *sampler_state)
 189 {
 190    struct zink_batch *batch = zink_curr_batch(zink_context(pctx));
 191    util_dynarray_append(&batch->zombie_samplers,
 192                         VkSampler, sampler_state);
 193 }
 194
 195
 196 static VkImageViewType
 197 image_view_type(enum pipe_texture_target target)
 198 {
 199    switch (target) {
 200    case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
 201    case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
 202    case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
 203    case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
 204    case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
 205    case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
 206    case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
 207    case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D; /* not sure */
 208    default:
 209       unreachable("unexpected target");
 210    }
 211 }
 212
 213 static VkComponentSwizzle
 214 component_mapping(enum pipe_swizzle swizzle)
 215 {
 216    switch (swizzle) {
 217    case PIPE_SWIZZLE_X: return VK_COMPONENT_SWIZZLE_R;
 218    case PIPE_SWIZZLE_Y: return VK_COMPONENT_SWIZZLE_G;
 219    case PIPE_SWIZZLE_Z: return VK_COMPONENT_SWIZZLE_B;
 220    case PIPE_SWIZZLE_W: return VK_COMPONENT_SWIZZLE_A;
 221    case PIPE_SWIZZLE_0: return VK_COMPONENT_SWIZZLE_ZERO;
 222    case PIPE_SWIZZLE_1: return VK_COMPONENT_SWIZZLE_ONE;
 223    case PIPE_SWIZZLE_NONE: return VK_COMPONENT_SWIZZLE_IDENTITY; // ???
 224    default:
 225       unreachable("unexpected swizzle");
 226    }
 227 }
 228
 229 static VkImageAspectFlags
 230 sampler_aspect_from_format(enum pipe_format fmt)
 231 {
 232    if (util_format_is_depth_or_stencil(fmt)) {
 233       const struct util_format_description *desc = util_format_description(fmt);
 234       if (util_format_has_depth(desc))
 235          return VK_IMAGE_ASPECT_DEPTH_BIT;
 236       assert(util_format_has_stencil(desc));
 237       return VK_IMAGE_ASPECT_STENCIL_BIT;
 238    } else
 239      return VK_IMAGE_ASPECT_COLOR_BIT;
 240 }
 241
 242 static struct pipe_sampler_view *
 243 zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
 244                          const struct pipe_sampler_view *state)
 245 {
 246    struct zink_screen *screen = zink_screen(pctx->screen);
 247    struct zink_resource *res = zink_resource(pres);
 248    struct zink_sampler_view *sampler_view = CALLOC_STRUCT(zink_sampler_view);
 249
 250    sampler_view->base = *state;
 251    sampler_view->base.texture = NULL;
 252    pipe_resource_reference(&sampler_view->base.texture, pres);
 253    sampler_view->base.reference.count = 1;
 254    sampler_view->base.context = pctx;
 255
 256    VkImageViewCreateInfo ivci = {};
 257    ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
 258    ivci.image = res->image;
 259    ivci.viewType = image_view_type(state->target);
 260    ivci.format = zink_get_format(state->format);
 261    ivci.components.r = component_mapping(state->swizzle_r);
 262    ivci.components.g = component_mapping(state->swizzle_g);
 263    ivci.components.b = component_mapping(state->swizzle_b);
 264    ivci.components.a = component_mapping(state->swizzle_a);
 265
 266    ivci.subresourceRange.aspectMask = sampler_aspect_from_format(state->format);
 267    ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
 268    ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
 269    ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
 270    ivci.subresourceRange.layerCount = state->u.tex.last_layer - state->u.tex.first_layer + 1;
 271
 272    VkResult err = vkCreateImageView(screen->dev, &ivci, NULL, &sampler_view->image_view);
 273    if (err != VK_SUCCESS) {
 274       FREE(sampler_view);
 275       return NULL;
 276    }
 277
 278    return &sampler_view->base;
 279 }
 280
 281 static void
 282 zink_sampler_view_destroy(struct pipe_context *pctx,
 283                           struct pipe_sampler_view *pview)
 284 {
 285    struct zink_sampler_view *view = zink_sampler_view(pview);
 286    vkDestroyImageView(zink_screen(pctx->screen)->dev, view->image_view, NULL);
 287    FREE(view);
 288 }
 289
 290 static void *
 291 zink_create_vs_state(struct pipe_context *pctx,
 292                      const struct pipe_shader_state *shader)
 293 {
 294    struct nir_shader *nir;
 295    if (shader->type != PIPE_SHADER_IR_NIR)
 296       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 297    else
 298       nir = (struct nir_shader *)shader->ir.nir;
 299
 300    return zink_compile_nir(zink_screen(pctx->screen), nir);
 301 }
 302
 303 static void
 304 bind_stage(struct zink_context *ctx, enum pipe_shader_type stage,
 305            struct zink_shader *shader)
 306 {
 307    assert(stage < PIPE_SHADER_COMPUTE);
 308    ctx->gfx_stages[stage] = shader;
 309    ctx->dirty |= ZINK_DIRTY_PROGRAM;
 310 }
 311
 312 static void
 313 zink_bind_vs_state(struct pipe_context *pctx,
 314                    void *cso)
 315 {
 316    bind_stage(zink_context(pctx), PIPE_SHADER_VERTEX, cso);
 317 }
 318
 319 static void
 320 zink_delete_vs_state(struct pipe_context *pctx,
 321                      void *cso)
 322 {
 323    zink_shader_free(zink_screen(pctx->screen), cso);
 324 }
 325
 326 static void *
 327 zink_create_fs_state(struct pipe_context *pctx,
 328                      const struct pipe_shader_state *shader)
 329 {
 330    struct nir_shader *nir;
 331    if (shader->type != PIPE_SHADER_IR_NIR)
 332       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 333    else
 334       nir = (struct nir_shader *)shader->ir.nir;
 335
 336    return zink_compile_nir(zink_screen(pctx->screen), nir);
 337 }
 338
 339 static void
 340 zink_bind_fs_state(struct pipe_context *pctx,
 341                    void *cso)
 342 {
 343    bind_stage(zink_context(pctx), PIPE_SHADER_FRAGMENT, cso);
 344 }
 345
 346 static void
 347 zink_delete_fs_state(struct pipe_context *pctx,
 348                      void *cso)
 349 {
 350    zink_shader_free(zink_screen(pctx->screen), cso);
 351 }
 352
 353 static void
 354 zink_set_polygon_stipple(struct pipe_context *pctx,
 355                          const struct pipe_poly_stipple *ps)
 356 {
 357 }
 358
 359 static void
 360 zink_set_vertex_buffers(struct pipe_context *pctx,
 361                         unsigned start_slot,
 362                         unsigned num_buffers,
 363                         const struct pipe_vertex_buffer *buffers)
 364 {
 365    struct zink_context *ctx = zink_context(pctx);
 366
 367    if (buffers) {
 368       for (int i = 0; i < num_buffers; ++i) {
 369          const struct pipe_vertex_buffer *vb = buffers + i;
 370          ctx->gfx_pipeline_state.bindings[start_slot + i].stride = vb->stride;
 371       }
 372    }
 373
 374    util_set_vertex_buffers_mask(ctx->buffers, &ctx->buffers_enabled_mask,
 375                                 buffers, start_slot, num_buffers);
 376 }
 377
 378 static void
 379 zink_set_viewport_states(struct pipe_context *pctx,
 380                          unsigned start_slot,
 381                          unsigned num_viewports,
 382                          const struct pipe_viewport_state *state)
 383 {
 384    struct zink_context *ctx = zink_context(pctx);
 385
 386    for (unsigned i = 0; i < num_viewports; ++i) {
 387       VkViewport viewport = {
 388          state[i].translate[0] - state[i].scale[0],
 389          state[i].translate[1] - state[i].scale[1],
 390          state[i].scale[0] * 2,
 391          state[i].scale[1] * 2,
 392          state[i].translate[2] - state[i].scale[2],
 393          state[i].translate[2] + state[i].scale[2]
 394       };
 395       ctx->viewport_states[start_slot + i] = state[i];
 396       ctx->viewports[start_slot + i] = viewport;
 397    }
 398    ctx->num_viewports = start_slot + num_viewports;
 399 }
 400
 401 static void
 402 zink_set_scissor_states(struct pipe_context *pctx,
 403                         unsigned start_slot, unsigned num_scissors,
 404                         const struct pipe_scissor_state *states)
 405 {
 406    struct zink_context *ctx = zink_context(pctx);
 407
 408    for (unsigned i = 0; i < num_scissors; i++) {
 409       VkRect2D scissor;
 410
 411       scissor.offset.x = states[i].minx;
 412       scissor.offset.y = states[i].miny;
 413       scissor.extent.width = states[i].maxx - states[i].minx;
 414       scissor.extent.height = states[i].maxy - states[i].miny;
 415       ctx->scissor_states[start_slot + i] = states[i];
 416       ctx->scissors[start_slot + i] = scissor;
 417    }
 418    ctx->num_scissors = start_slot + num_scissors;
 419 }
 420
 421 static void
 422 zink_set_constant_buffer(struct pipe_context *pctx,
 423                          enum pipe_shader_type shader, uint index,
 424                          const struct pipe_constant_buffer *cb)
 425 {
 426    struct zink_context *ctx = zink_context(pctx);
 427
 428    if (cb) {
 429       struct pipe_resource *buffer = cb->buffer;
 430       unsigned offset = cb->buffer_offset;
 431       if (cb->user_buffer)
 432          u_upload_data(ctx->base.const_uploader, 0, cb->buffer_size, 64,
 433                        cb->user_buffer, &offset, &buffer);
 434
 435       pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
 436       ctx->ubos[shader][index].buffer_offset = offset;
 437       ctx->ubos[shader][index].buffer_size = cb->buffer_size;
 438       ctx->ubos[shader][index].user_buffer = NULL;
 439
 440       if (cb->user_buffer)
 441          pipe_resource_reference(&buffer, NULL);
 442    } else {
 443       pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
 444       ctx->ubos[shader][index].buffer_offset = 0;
 445       ctx->ubos[shader][index].buffer_size = 0;
 446       ctx->ubos[shader][index].user_buffer = NULL;
 447    }
 448 }
 449
 450 static void
 451 zink_set_sampler_views(struct pipe_context *pctx,
 452                        enum pipe_shader_type shader_type,
 453                        unsigned start_slot,
 454                        unsigned num_views,
 455                        struct pipe_sampler_view **views)
 456 {
 457    struct zink_context *ctx = zink_context(pctx);
 458    assert(views);
 459    for (unsigned i = 0; i < num_views; ++i) {
 460       pipe_sampler_view_reference(
 461          &ctx->image_views[shader_type][start_slot + i],
 462          views[i]);
 463    }
 464    ctx->num_image_views[shader_type] = start_slot + num_views;
 465 }
 466
 467 static void
 468 zink_set_stencil_ref(struct pipe_context *pctx,
 469                      const struct pipe_stencil_ref *ref)
 470 {
 471    struct zink_context *ctx = zink_context(pctx);
 472    ctx->stencil_ref = *ref;
 473 }
 474
 475 static void
 476 zink_set_clip_state(struct pipe_context *pctx,
 477                     const struct pipe_clip_state *pcs)
 478 {
 479 }
 480
 481 static struct zink_render_pass *
 482 get_render_pass(struct zink_context *ctx)
 483 {
 484    struct zink_screen *screen = zink_screen(ctx->base.screen);
 485    const struct pipe_framebuffer_state *fb = &ctx->fb_state;
 486    struct zink_render_pass_state state;
 487
 488    for (int i = 0; i < fb->nr_cbufs; i++) {
 489       struct zink_resource *cbuf = zink_resource(fb->cbufs[i]->texture);
 490       state.rts[i].format = cbuf->format;
 491       state.rts[i].samples = cbuf->base.nr_samples > 0 ? cbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 492    }
 493    state.num_cbufs = fb->nr_cbufs;
 494
 495    if (fb->zsbuf) {
 496       struct zink_resource *zsbuf = zink_resource(fb->zsbuf->texture);
 497       state.rts[fb->nr_cbufs].format = zsbuf->format;
 498       state.rts[fb->nr_cbufs].samples = zsbuf->base.nr_samples > 0 ? zsbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 499    }
 500    state.have_zsbuf = fb->zsbuf != NULL;
 501
 502    struct hash_entry *entry = _mesa_hash_table_search(ctx->render_pass_cache,
 503                                                       &state);
 504    if (!entry) {
 505       struct zink_render_pass *rp;
 506       rp = zink_create_render_pass(screen, &state);
 507       entry = _mesa_hash_table_insert(ctx->render_pass_cache, &state, rp);
 508       if (!entry)
 509          return NULL;
 510    }
 511
 512    return entry->data;
 513 }
 514
 515 static struct zink_framebuffer *
 516 get_framebuffer(struct zink_context *ctx)
 517 {
 518    struct zink_screen *screen = zink_screen(ctx->base.screen);
 519
 520    struct zink_framebuffer_state state = {};
 521    state.rp = get_render_pass(ctx);
 522    for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
 523       struct pipe_surface *psurf = ctx->fb_state.cbufs[i];
 524       state.attachments[i] = zink_surface(psurf);
 525    }
 526
 527    state.num_attachments = ctx->fb_state.nr_cbufs;
 528    if (ctx->fb_state.zsbuf) {
 529       struct pipe_surface *psurf = ctx->fb_state.zsbuf;
 530       state.attachments[state.num_attachments++] = zink_surface(psurf);
 531    }
 532
 533    state.width = ctx->fb_state.width;
 534    state.height = ctx->fb_state.height;
 535    state.layers = MAX2(ctx->fb_state.layers, 1);
 536
 537    struct hash_entry *entry = _mesa_hash_table_search(ctx->framebuffer_cache,
 538                                                       &state);
 539    if (!entry) {
 540       struct zink_framebuffer *fb = zink_create_framebuffer(screen, &state);
 541       entry = _mesa_hash_table_insert(ctx->framebuffer_cache, &state, fb);
 542       if (!entry)
 543          return NULL;
 544    }
 545
 546    return entry->data;
 547 }
 548
 549 void
 550 zink_begin_render_pass(struct zink_context *ctx, struct zink_batch *batch)
 551 {
 552    struct zink_screen *screen = zink_screen(ctx->base.screen);
 553    assert(batch == zink_curr_batch(ctx));
 554    assert(ctx->gfx_pipeline_state.render_pass);
 555
 556    VkRenderPassBeginInfo rpbi = {};
 557    rpbi.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO;
 558    rpbi.renderPass = ctx->gfx_pipeline_state.render_pass->render_pass;
 559    rpbi.renderArea.offset.x = 0;
 560    rpbi.renderArea.offset.y = 0;
 561    rpbi.renderArea.extent.width = ctx->fb_state.width;
 562    rpbi.renderArea.extent.height = ctx->fb_state.height;
 563    rpbi.clearValueCount = 0;
 564    rpbi.pClearValues = NULL;
 565    rpbi.framebuffer = ctx->framebuffer->fb;
 566
 567    assert(ctx->gfx_pipeline_state.render_pass && ctx->framebuffer);
 568    assert(!batch->rp || batch->rp == ctx->gfx_pipeline_state.render_pass);
 569    assert(!batch->fb || batch->fb == ctx->framebuffer);
 570
 571    zink_render_pass_reference(screen, &batch->rp, ctx->gfx_pipeline_state.render_pass);
 572    zink_framebuffer_reference(screen, &batch->fb, ctx->framebuffer);
 573
 574    vkCmdBeginRenderPass(batch->cmdbuf, &rpbi, VK_SUBPASS_CONTENTS_INLINE);
 575 }
 576
 577 static void
 578 flush_batch(struct zink_context *ctx)
 579 {
 580    struct zink_batch *batch = zink_curr_batch(ctx);
 581    if (batch->rp)
 582       vkCmdEndRenderPass(batch->cmdbuf);
 583
 584    zink_end_batch(ctx, batch);
 585
 586    ctx->curr_batch++;
 587    if (ctx->curr_batch == ARRAY_SIZE(ctx->batches))
 588       ctx->curr_batch = 0;
 589
 590    zink_start_batch(ctx, zink_curr_batch(ctx));
 591 }
 592
 593 struct zink_batch *
 594 zink_batch_rp(struct zink_context *ctx)
 595 {
 596    struct zink_batch *batch = zink_curr_batch(ctx);
 597    if (!batch->rp) {
 598       zink_begin_render_pass(ctx, batch);
 599       assert(batch->rp);
 600    }
 601    return batch;
 602 }
 603
 604 struct zink_batch *
 605 zink_batch_no_rp(struct zink_context *ctx)
 606 {
 607    struct zink_batch *batch = zink_curr_batch(ctx);
 608    if (batch->rp) {
 609       /* flush batch and get a new one */
 610       flush_batch(ctx);
 611       batch = zink_curr_batch(ctx);
 612       assert(!batch->rp);
 613    }
 614    return batch;
 615 }
 616
 617 static void
 618 zink_set_framebuffer_state(struct pipe_context *pctx,
 619                            const struct pipe_framebuffer_state *state)
 620 {
 621    struct zink_context *ctx = zink_context(pctx);
 622    struct zink_screen *screen = zink_screen(pctx->screen);
 623
 624    VkSampleCountFlagBits rast_samples = VK_SAMPLE_COUNT_1_BIT;
 625    for (int i = 0; i < state->nr_cbufs; i++)
 626       rast_samples = MAX2(rast_samples, state->cbufs[i]->texture->nr_samples);
 627    if (state->zsbuf && state->zsbuf->texture->nr_samples)
 628       rast_samples = MAX2(rast_samples, state->zsbuf->texture->nr_samples);
 629
 630    util_copy_framebuffer_state(&ctx->fb_state, state);
 631
 632    struct zink_framebuffer *fb = get_framebuffer(ctx);
 633    zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
 634    zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
 635
 636    ctx->gfx_pipeline_state.rast_samples = rast_samples;
 637    ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
 638
 639    struct zink_batch *batch = zink_batch_no_rp(ctx);
 640
 641    for (int i = 0; i < state->nr_cbufs; i++) {
 642       struct zink_resource *res = zink_resource(state->cbufs[i]->texture);
 643       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 644           res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
 645          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 646                                VK_IMAGE_LAYOUT_GENERAL);
 647    }
 648
 649    if (state->zsbuf) {
 650       struct zink_resource *res = zink_resource(state->zsbuf->texture);
 651       if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
 652           res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
 653          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 654                                VK_IMAGE_LAYOUT_GENERAL);
 655    }
 656 }
 657
 658 static void
 659 zink_set_blend_color(struct pipe_context *pctx,
 660                      const struct pipe_blend_color *color)
 661 {
 662    struct zink_context *ctx = zink_context(pctx);
 663    memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
 664 }
 665
 666 static void
 667 zink_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
 668 {
 669    struct zink_context *ctx = zink_context(pctx);
 670    ctx->gfx_pipeline_state.sample_mask = sample_mask;
 671 }
 672
 673 static VkAccessFlags
 674 access_flags(VkImageLayout layout)
 675 {
 676    switch (layout) {
 677    case VK_IMAGE_LAYOUT_UNDEFINED:
 678    case VK_IMAGE_LAYOUT_GENERAL:
 679       return 0;
 680
 681    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 682       return VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
 683    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 684       return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
 685
 686    case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
 687       return VK_ACCESS_SHADER_READ_BIT;
 688
 689    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 690       return VK_ACCESS_TRANSFER_READ_BIT;
 691
 692    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 693       return VK_ACCESS_TRANSFER_WRITE_BIT;
 694
 695    case VK_IMAGE_LAYOUT_PREINITIALIZED:
 696       return VK_ACCESS_HOST_WRITE_BIT;
 697
 698    default:
 699       unreachable("unexpected layout");
 700    }
 701 }
 702
 703 void
 704 zink_resource_barrier(VkCommandBuffer cmdbuf, struct zink_resource *res,
 705                       VkImageAspectFlags aspect, VkImageLayout new_layout)
 706 {
 707    VkImageSubresourceRange isr = {
 708       aspect,
 709       0, VK_REMAINING_MIP_LEVELS,
 710       0, VK_REMAINING_ARRAY_LAYERS
 711    };
 712
 713    VkImageMemoryBarrier imb = {
 714       VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
 715       NULL,
 716       access_flags(res->layout),
 717       access_flags(new_layout),
 718       res->layout,
 719       new_layout,
 720       VK_QUEUE_FAMILY_IGNORED,
 721       VK_QUEUE_FAMILY_IGNORED,
 722       res->image,
 723       isr
 724    };
 725    vkCmdPipelineBarrier(
 726       cmdbuf,
 727       VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
 728       VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
 729       0,
 730       0, NULL,
 731       0, NULL,
 732       1, &imb
 733    );
 734
 735    res->layout = new_layout;
 736 }
 737
 738 static void
 739 zink_clear(struct pipe_context *pctx,
 740            unsigned buffers,
 741            const union pipe_color_union *pcolor,
 742            double depth, unsigned stencil)
 743 {
 744    struct zink_context *ctx = zink_context(pctx);
 745    struct pipe_framebuffer_state *fb = &ctx->fb_state;
 746
 747    /* FIXME: this is very inefficient; if no renderpass has been started yet,
 748     * we should record the clear if it's full-screen, and apply it as we
 749     * start the render-pass. Otherwise we can do a partial out-of-renderpass
 750     * clear.
 751     */
 752    struct zink_batch *batch = zink_batch_rp(ctx);
 753
 754    VkClearAttachment attachments[1 + PIPE_MAX_COLOR_BUFS];
 755    int num_attachments = 0;
 756
 757    if (buffers & PIPE_CLEAR_COLOR) {
 758       VkClearColorValue color;
 759       color.float32[0] = pcolor->f[0];
 760       color.float32[1] = pcolor->f[1];
 761       color.float32[2] = pcolor->f[2];
 762       color.float32[3] = pcolor->f[3];
 763
 764       for (unsigned i = 0; i < fb->nr_cbufs; i++) {
 765          if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
 766             continue;
 767
 768          attachments[num_attachments].aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
 769          attachments[num_attachments].colorAttachment = i;
 770          attachments[num_attachments].clearValue.color = color;
 771          ++num_attachments;
 772       }
 773    }
 774
 775    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && fb->zsbuf) {
 776       VkImageAspectFlags aspect = 0;
 777       if (buffers & PIPE_CLEAR_DEPTH)
 778          aspect |= VK_IMAGE_ASPECT_DEPTH_BIT;
 779       if (buffers & PIPE_CLEAR_STENCIL)
 780          aspect |= VK_IMAGE_ASPECT_STENCIL_BIT;
 781
 782       attachments[num_attachments].aspectMask = aspect;
 783       attachments[num_attachments].clearValue.depthStencil.depth = depth;
 784       attachments[num_attachments].clearValue.depthStencil.stencil = stencil;
 785       ++num_attachments;
 786    }
 787
 788    unsigned num_layers = util_framebuffer_get_num_layers(fb);
 789    VkClearRect rects[PIPE_MAX_VIEWPORTS];
 790    uint32_t num_rects;
 791    if (ctx->num_scissors) {
 792       for (unsigned i = 0 ; i < ctx->num_scissors; ++i) {
 793          rects[i].rect = ctx->scissors[i];
 794          rects[i].rect.extent.width = MIN2(rects[i].rect.extent.width,
 795                                            fb->width);
 796          rects[i].rect.extent.height = MIN2(rects[i].rect.extent.height,
 797                                             fb->height);
 798          rects[i].baseArrayLayer = 0;
 799          rects[i].layerCount = num_layers;
 800       }
 801       num_rects = ctx->num_scissors;
 802    } else {
 803       rects[0].rect.offset.x = 0;
 804       rects[0].rect.offset.y = 0;
 805       rects[0].rect.extent.width = fb->width;
 806       rects[0].rect.extent.height = fb->height;
 807       rects[0].baseArrayLayer = 0;
 808       rects[0].layerCount = num_layers;
 809       num_rects = 1;
 810    }
 811
 812    vkCmdClearAttachments(batch->cmdbuf,
 813                          num_attachments, attachments,
 814                          num_rects, rects);
 815 }
 816
 817 VkShaderStageFlagBits
 818 zink_shader_stage(enum pipe_shader_type type)
 819 {
 820    VkShaderStageFlagBits stages[] = {
 821       [PIPE_SHADER_VERTEX] = VK_SHADER_STAGE_VERTEX_BIT,
 822       [PIPE_SHADER_FRAGMENT] = VK_SHADER_STAGE_FRAGMENT_BIT,
 823       [PIPE_SHADER_GEOMETRY] = VK_SHADER_STAGE_GEOMETRY_BIT,
 824       [PIPE_SHADER_TESS_CTRL] = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
 825       [PIPE_SHADER_TESS_EVAL] = VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
 826       [PIPE_SHADER_COMPUTE] = VK_SHADER_STAGE_COMPUTE_BIT,
 827    };
 828    return stages[type];
 829 }
 830
 831 static VkDescriptorSet
 832 allocate_descriptor_set(struct zink_screen *screen,
 833                         struct zink_batch *batch,
 834                         struct zink_gfx_program *prog)
 835 {
 836    assert(batch->descs_left >= prog->num_descriptors);
 837    VkDescriptorSetAllocateInfo dsai;
 838    memset((void *)&dsai, 0, sizeof(dsai));
 839    dsai.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO;
 840    dsai.pNext = NULL;
 841    dsai.descriptorPool = batch->descpool;
 842    dsai.descriptorSetCount = 1;
 843    dsai.pSetLayouts = &prog->dsl;
 844
 845    VkDescriptorSet desc_set;
 846    if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
 847       debug_printf("ZINK: failed to allocate descriptor set :/");
 848       return VK_NULL_HANDLE;
 849    }
 850
 851    batch->descs_left -= prog->num_descriptors;
 852    return desc_set;
 853 }
 854
 855 static void
 856 zink_bind_vertex_buffers(struct zink_batch *batch, struct zink_context *ctx)
 857 {
 858    VkBuffer buffers[PIPE_MAX_ATTRIBS];
 859    VkDeviceSize buffer_offsets[PIPE_MAX_ATTRIBS];
 860    const struct zink_vertex_elements_state *elems = ctx->element_state;
 861    for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) {
 862       struct pipe_vertex_buffer *vb = ctx->buffers + ctx->element_state->binding_map[i];
 863       assert(vb && vb->buffer.resource);
 864       struct zink_resource *res = zink_resource(vb->buffer.resource);
 865       buffers[i] = res->buffer;
 866       buffer_offsets[i] = vb->buffer_offset;
 867       zink_batch_reference_resoure(batch, res);
 868    }
 869
 870    if (elems->hw_state.num_bindings > 0)
 871       vkCmdBindVertexBuffers(batch->cmdbuf, 0,
 872                              elems->hw_state.num_bindings,
 873                              buffers, buffer_offsets);
 874 }
 875
 876 static uint32_t
 877 hash_gfx_program(const void *key)
 878 {
 879    return _mesa_hash_data(key, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1));
 880 }
 881
 882 static bool
 883 equals_gfx_program(const void *a, const void *b)
 884 {
 885    return memcmp(a, b, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1)) == 0;
 886 }
 887
 888 static uint32_t
 889 hash_render_pass_state(const void *key)
 890 {
 891    return _mesa_hash_data(key, sizeof(struct zink_render_pass_state));
 892 }
 893
 894 static bool
 895 equals_render_pass_state(const void *a, const void *b)
 896 {
 897    return memcmp(a, b, sizeof(struct zink_render_pass_state)) == 0;
 898 }
 899
 900 static uint32_t
 901 hash_framebuffer_state(const void *key)
 902 {
 903    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)key;
 904    return _mesa_hash_data(key, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments);
 905 }
 906
 907 static bool
 908 equals_framebuffer_state(const void *a, const void *b)
 909 {
 910    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)a;
 911    return memcmp(a, b, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments) == 0;
 912 }
 913
 914 static struct zink_gfx_program *
 915 get_gfx_program(struct zink_context *ctx)
 916 {
 917    if (ctx->dirty & ZINK_DIRTY_PROGRAM) {
 918       struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
 919                                                          ctx->gfx_stages);
 920       if (!entry) {
 921          struct zink_gfx_program *prog;
 922          prog = zink_create_gfx_program(zink_screen(ctx->base.screen),
 923                                                      ctx->gfx_stages);
 924          entry = _mesa_hash_table_insert(ctx->program_cache, prog->stages, prog);
 925          if (!entry)
 926             return NULL;
 927       }
 928       ctx->curr_program = entry->data;
 929       ctx->dirty &= ~ZINK_DIRTY_PROGRAM;
 930    }
 931
 932    assert(ctx->curr_program);
 933    return ctx->curr_program;
 934 }
 935
 936 static void
 937 zink_draw_vbo(struct pipe_context *pctx,
 938               const struct pipe_draw_info *dinfo)
 939 {
 940    struct zink_context *ctx = zink_context(pctx);
 941    struct zink_screen *screen = zink_screen(pctx->screen);
 942    struct zink_rasterizer_state *rast_state = ctx->rast_state;
 943
 944    if (dinfo->mode >= PIPE_PRIM_QUADS ||
 945        dinfo->mode == PIPE_PRIM_LINE_LOOP ||
 946        dinfo->index_size == 1) {
 947       if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&dinfo->count))
 948          return;
 949
 950       util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
 951       util_primconvert_draw_vbo(ctx->primconvert, dinfo);
 952       return;
 953    }
 954
 955    struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
 956    if (!gfx_program)
 957       return;
 958
 959    VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
 960                                                &ctx->gfx_pipeline_state,
 961                                                dinfo->mode);
 962
 963    bool depth_bias = false;
 964    switch (u_reduced_prim(dinfo->mode)) {
 965    case PIPE_PRIM_POINTS:
 966       depth_bias = rast_state->offset_point;
 967       break;
 968
 969    case PIPE_PRIM_LINES:
 970       depth_bias = rast_state->offset_line;
 971       break;
 972
 973    case PIPE_PRIM_TRIANGLES:
 974       depth_bias = rast_state->offset_tri;
 975       break;
 976
 977    default:
 978       unreachable("unexpected reduced prim");
 979    }
 980
 981    unsigned index_offset = 0;
 982    struct pipe_resource *index_buffer = NULL;
 983    if (dinfo->index_size > 0) {
 984       if (dinfo->has_user_indices) {
 985          if (!util_upload_index_buffer(pctx, dinfo, &index_buffer, &index_offset)) {
 986             debug_printf("util_upload_index_buffer() failed\n");
 987             return;
 988          }
 989       } else
 990          index_buffer = dinfo->index.resource;
 991    }
 992
 993    VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS + PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 994    VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS];
 995    VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 996    int num_wds = 0, num_buffer_info = 0, num_image_info = 0;
 997
 998    struct zink_resource *transitions[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
 999    int num_transitions = 0;
1000
1001    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1002       struct zink_shader *shader = ctx->gfx_stages[i];
1003       if (!shader)
1004          continue;
1005
1006       for (int j = 0; j < shader->num_bindings; j++) {
1007          int index = shader->bindings[j].index;
1008          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1009             assert(ctx->ubos[i][index].buffer_size > 0);
1010             assert(ctx->ubos[i][index].buffer);
1011             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1012             buffer_infos[num_buffer_info].buffer = res->buffer;
1013             buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset;
1014             buffer_infos[num_buffer_info].range  = VK_WHOLE_SIZE;
1015             wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info;
1016             ++num_buffer_info;
1017          } else {
1018             struct pipe_sampler_view *psampler_view = ctx->image_views[i][index];
1019             assert(psampler_view);
1020             struct zink_sampler_view *sampler_view = zink_sampler_view(psampler_view);
1021
1022             struct zink_resource *res = zink_resource(psampler_view->texture);
1023             VkImageLayout layout = res->layout;
1024             if (layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL &&
1025                 layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL &&
1026                 layout != VK_IMAGE_LAYOUT_GENERAL) {
1027                transitions[num_transitions++] = res;
1028                layout = VK_IMAGE_LAYOUT_GENERAL;
1029             }
1030             image_infos[num_image_info].imageLayout = layout;
1031             image_infos[num_image_info].imageView = sampler_view->image_view;
1032             image_infos[num_image_info].sampler = ctx->samplers[i][index];
1033             wds[num_wds].pImageInfo = image_infos + num_image_info;
1034             ++num_image_info;
1035          }
1036
1037          wds[num_wds].sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET;
1038          wds[num_wds].pNext = NULL;
1039          wds[num_wds].dstBinding = shader->bindings[j].binding;
1040          wds[num_wds].dstArrayElement = 0;
1041          wds[num_wds].descriptorCount = 1;
1042          wds[num_wds].descriptorType = shader->bindings[j].type;
1043          ++num_wds;
1044       }
1045    }
1046
1047    struct zink_batch *batch;
1048    if (num_transitions > 0) {
1049       batch = zink_batch_no_rp(ctx);
1050
1051       for (int i = 0; i < num_transitions; ++i)
1052          zink_resource_barrier(batch->cmdbuf, transitions[i],
1053                                transitions[i]->aspect,
1054                                VK_IMAGE_LAYOUT_GENERAL);
1055    }
1056
1057    batch = zink_batch_rp(ctx);
1058
1059    if (batch->descs_left < gfx_program->num_descriptors) {
1060       flush_batch(ctx);
1061       batch = zink_batch_rp(ctx);
1062       assert(batch->descs_left >= gfx_program->num_descriptors);
1063    }
1064
1065    VkDescriptorSet desc_set = allocate_descriptor_set(screen, batch,
1066                                                       gfx_program);
1067    assert(desc_set != VK_NULL_HANDLE);
1068
1069    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1070       struct zink_shader *shader = ctx->gfx_stages[i];
1071       if (!shader)
1072          continue;
1073
1074       for (int j = 0; j < shader->num_bindings; j++) {
1075          int index = shader->bindings[j].index;
1076          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1077             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1078             zink_batch_reference_resoure(batch, res);
1079          } else {
1080             struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->image_views[i][index]);
1081             zink_batch_reference_sampler_view(batch, sampler_view);
1082          }
1083       }
1084    }
1085
1086    vkCmdSetViewport(batch->cmdbuf, 0, ctx->num_viewports, ctx->viewports);
1087
1088    if (ctx->num_scissors)
1089       vkCmdSetScissor(batch->cmdbuf, 0, ctx->num_scissors, ctx->scissors);
1090    else if (ctx->fb_state.width && ctx->fb_state.height) {
1091       VkRect2D fb_scissor = {};
1092       fb_scissor.extent.width = ctx->fb_state.width;
1093       fb_scissor.extent.height = ctx->fb_state.height;
1094       vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
1095    }
1096
1097    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref.ref_value[0]);
1098    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref.ref_value[1]);
1099
1100    if (depth_bias)
1101       vkCmdSetDepthBias(batch->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
1102    else
1103       vkCmdSetDepthBias(batch->cmdbuf, 0.0f, 0.0f, 0.0f);
1104
1105    if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
1106       vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
1107
1108    for (int i = 0; i < num_wds; ++i)
1109       wds[i].dstSet = desc_set;
1110
1111    vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
1112
1113    vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
1114    vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
1115                            gfx_program->layout, 0, 1, &desc_set, 0, NULL);
1116    zink_bind_vertex_buffers(batch, ctx);
1117
1118    if (dinfo->index_size > 0) {
1119       assert(dinfo->index_size != 1);
1120       VkIndexType index_type = dinfo->index_size == 2 ? VK_INDEX_TYPE_UINT16 : VK_INDEX_TYPE_UINT32;
1121       struct zink_resource *res = zink_resource(index_buffer);
1122       vkCmdBindIndexBuffer(batch->cmdbuf, res->buffer, index_offset, index_type);
1123       zink_batch_reference_resoure(batch, res);
1124       vkCmdDrawIndexed(batch->cmdbuf,
1125          dinfo->count, dinfo->instance_count,
1126          dinfo->start, dinfo->index_bias, dinfo->start_instance);
1127    } else
1128       vkCmdDraw(batch->cmdbuf, dinfo->count, dinfo->instance_count, dinfo->start, dinfo->start_instance);
1129
1130    if (dinfo->index_size > 0 && dinfo->has_user_indices)
1131       pipe_resource_reference(&index_buffer, NULL);
1132 }
1133
1134 static void
1135 zink_flush(struct pipe_context *pctx,
1136            struct pipe_fence_handle **pfence,
1137            enum pipe_flush_flags flags)
1138 {
1139    struct zink_context *ctx = zink_context(pctx);
1140
1141    struct zink_batch *batch = zink_curr_batch(ctx);
1142    flush_batch(ctx);
1143
1144    if (pfence)
1145       zink_fence_reference(zink_screen(pctx->screen),
1146                            (struct zink_fence **)pfence,
1147                            batch->fence);
1148
1149    /* HACK:
1150     * For some strange reason, we need to finish before presenting, or else
1151     * we start rendering on top of the back-buffer for the next frame. This
1152     * seems like a bug in the DRI-driver to me, because we really should
1153     * be properly protected by fences here, and the back-buffer should
1154     * either be swapped with the front-buffer, or blitted from. But for
1155     * some strange reason, neither of these things happen.
1156     */
1157    if (flags & PIPE_FLUSH_END_OF_FRAME)
1158       pctx->screen->fence_finish(pctx->screen, pctx,
1159                                  (struct pipe_fence_handle *)batch->fence,
1160                                  PIPE_TIMEOUT_INFINITE);
1161 }
1162
1163 static bool
1164 blit_resolve(struct zink_context *ctx, const struct pipe_blit_info *info)
1165 {
1166    if (info->mask != PIPE_MASK_RGBA ||
1167        info->scissor_enable ||
1168        info->alpha_blend)
1169       return false;
1170
1171    struct zink_resource *src = zink_resource(info->src.resource);
1172    struct zink_resource *dst = zink_resource(info->dst.resource);
1173
1174    struct zink_batch *batch = zink_batch_no_rp(ctx);
1175
1176    zink_batch_reference_resoure(batch, src);
1177    zink_batch_reference_resoure(batch, dst);
1178
1179    VkImageResolve region = {};
1180
1181    region.srcSubresource.aspectMask = src->aspect;
1182    region.srcSubresource.mipLevel = info->src.level;
1183    region.srcSubresource.baseArrayLayer = 0; // no clue
1184    region.srcSubresource.layerCount = 1; // no clue
1185    region.srcOffset.x = info->src.box.x;
1186    region.srcOffset.y = info->src.box.y;
1187    region.srcOffset.z = info->src.box.z;
1188
1189    region.dstSubresource.aspectMask = dst->aspect;
1190    region.dstSubresource.mipLevel = info->dst.level;
1191    region.dstSubresource.baseArrayLayer = 0; // no clue
1192    region.dstSubresource.layerCount = 1; // no clue
1193    region.dstOffset.x = info->dst.box.x;
1194    region.dstOffset.y = info->dst.box.y;
1195    region.dstOffset.z = info->dst.box.z;
1196
1197    region.extent.width = info->dst.box.width;
1198    region.extent.height = info->dst.box.height;
1199    region.extent.depth = info->dst.box.depth;
1200    vkCmdResolveImage(batch->cmdbuf, src->image, src->layout,
1201                      dst->image, dst->layout,
1202                      1, &region);
1203
1204    /* HACK: I have no idea why this is needed, but without it ioquake3
1205     * randomly keeps fading to black.
1206     */
1207    flush_batch(ctx);
1208
1209    return true;
1210 }
1211
1212 static bool
1213 blit_native(struct zink_context *ctx, const struct pipe_blit_info *info)
1214 {
1215    if (info->mask != PIPE_MASK_RGBA ||
1216        info->scissor_enable ||
1217        info->alpha_blend)
1218       return false;
1219
1220    struct zink_resource *src = zink_resource(info->src.resource);
1221    struct zink_resource *dst = zink_resource(info->dst.resource);
1222
1223    struct zink_batch *batch = zink_batch_no_rp(ctx);
1224    zink_batch_reference_resoure(batch, src);
1225    zink_batch_reference_resoure(batch, dst);
1226
1227    if (dst->layout != VK_IMAGE_LAYOUT_GENERAL &&
1228        dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL)
1229       zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1230                             VK_IMAGE_LAYOUT_GENERAL);
1231
1232    VkImageBlit region = {};
1233    region.srcSubresource.aspectMask = src->aspect;
1234    region.srcSubresource.mipLevel = info->src.level;
1235    region.srcOffsets[0].x = info->src.box.x;
1236    region.srcOffsets[0].y = info->src.box.y;
1237    region.srcOffsets[1].x = info->src.box.x + info->src.box.width;
1238    region.srcOffsets[1].y = info->src.box.y + info->src.box.height;
1239
1240    if (src->base.array_size > 1) {
1241       region.srcOffsets[0].z = 0;
1242       region.srcOffsets[1].z = 1;
1243       region.srcSubresource.baseArrayLayer = info->src.box.z;
1244       region.srcSubresource.layerCount = info->src.box.depth;
1245    } else {
1246       region.srcOffsets[0].z = info->src.box.z;
1247       region.srcOffsets[1].z = info->src.box.z + info->src.box.depth;
1248       region.srcSubresource.baseArrayLayer = 0;
1249       region.srcSubresource.layerCount = 1;
1250    }
1251
1252    region.dstSubresource.aspectMask = dst->aspect;
1253    region.dstSubresource.mipLevel = info->dst.level;
1254    region.dstOffsets[0].x = info->dst.box.x;
1255    region.dstOffsets[0].y = info->dst.box.y;
1256    region.dstOffsets[1].x = info->dst.box.x + info->dst.box.width;
1257    region.dstOffsets[1].y = info->dst.box.y + info->dst.box.height;
1258
1259    if (dst->base.array_size > 1) {
1260       region.dstOffsets[0].z = 0;
1261       region.dstOffsets[1].z = 1;
1262       region.dstSubresource.baseArrayLayer = info->dst.box.z;
1263       region.dstSubresource.layerCount = info->dst.box.depth;
1264    } else {
1265       region.dstOffsets[0].z = info->dst.box.z;
1266       region.dstOffsets[1].z = info->dst.box.z + info->dst.box.depth;
1267       region.dstSubresource.baseArrayLayer = 0;
1268       region.dstSubresource.layerCount = 1;
1269    }
1270
1271    vkCmdBlitImage(batch->cmdbuf, src->image, src->layout,
1272                   dst->image, dst->layout,
1273                   1, &region,
1274                   filter(info->filter));
1275
1276    /* HACK: I have no idea why this is needed, but without it ioquake3
1277     * randomly keeps fading to black.
1278     */
1279    flush_batch(ctx);
1280
1281    return true;
1282 }
1283
1284 static void
1285 zink_blit(struct pipe_context *pctx,
1286           const struct pipe_blit_info *info)
1287 {
1288    struct zink_context *ctx = zink_context(pctx);
1289    if (info->src.resource->nr_samples > 1 &&
1290        info->dst.resource->nr_samples <= 1) {
1291       if (blit_resolve(ctx, info))
1292          return;
1293    } else {
1294       if (blit_native(ctx, info))
1295          return;
1296    }
1297
1298    if (!util_blitter_is_blit_supported(ctx->blitter, info)) {
1299       debug_printf("blit unsupported %s -> %s\n",
1300               util_format_short_name(info->src.resource->format),
1301               util_format_short_name(info->dst.resource->format));
1302       return;
1303    }
1304
1305    util_blitter_save_blend(ctx->blitter, ctx->gfx_pipeline_state.blend_state);
1306    util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->gfx_pipeline_state.depth_stencil_alpha_state);
1307    util_blitter_save_vertex_elements(ctx->blitter, ctx->element_state);
1308    util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
1309    util_blitter_save_rasterizer(ctx->blitter, ctx->rast_state);
1310    util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
1311    util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
1312    util_blitter_save_framebuffer(ctx->blitter, &ctx->fb_state);
1313    util_blitter_save_viewport(ctx->blitter, ctx->viewport_states);
1314    util_blitter_save_scissor(ctx->blitter, ctx->scissor_states);
1315    util_blitter_save_fragment_sampler_states(ctx->blitter,
1316                                              ctx->num_samplers[PIPE_SHADER_FRAGMENT],
1317                                              (void **)ctx->samplers[PIPE_SHADER_FRAGMENT]);
1318    util_blitter_save_fragment_sampler_views(ctx->blitter,
1319                                             ctx->num_image_views[PIPE_SHADER_FRAGMENT],
1320                                             ctx->image_views[PIPE_SHADER_FRAGMENT]);
1321    util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[PIPE_SHADER_FRAGMENT]);
1322    util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->buffers);
1323    util_blitter_save_sample_mask(ctx->blitter, ctx->gfx_pipeline_state.sample_mask);
1324
1325    util_blitter_blit(ctx->blitter, info);
1326 }
1327
1328 static void
1329 zink_flush_resource(struct pipe_context *pipe,
1330                     struct pipe_resource *resource)
1331 {
1332 }
1333
1334 static void
1335 zink_resource_copy_region(struct pipe_context *pctx,
1336                           struct pipe_resource *pdst,
1337                           unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1338                           struct pipe_resource *psrc,
1339                           unsigned src_level, const struct pipe_box *src_box)
1340 {
1341    struct zink_resource *dst = zink_resource(pdst);
1342    struct zink_resource *src = zink_resource(psrc);
1343    struct zink_context *ctx = zink_context(pctx);
1344    if (dst->base.target != PIPE_BUFFER && src->base.target != PIPE_BUFFER) {
1345       VkImageCopy region = {};
1346
1347       region.srcSubresource.aspectMask = src->aspect;
1348       region.srcSubresource.mipLevel = src_level;
1349       region.srcSubresource.layerCount = 1;
1350       if (src->base.array_size > 1) {
1351          region.srcSubresource.baseArrayLayer = src_box->z;
1352          region.srcSubresource.layerCount = src_box->depth;
1353          region.extent.depth = 1;
1354       } else {
1355          region.srcOffset.z = src_box->z;
1356          region.srcSubresource.layerCount = 1;
1357          region.extent.depth = src_box->depth;
1358       }
1359
1360       region.srcOffset.x = src_box->x;
1361       region.srcOffset.y = src_box->y;
1362
1363       region.dstSubresource.aspectMask = dst->aspect;
1364       region.dstSubresource.mipLevel = dst_level;
1365       if (dst->base.array_size > 1) {
1366          region.dstSubresource.baseArrayLayer = dstz;
1367          region.dstSubresource.layerCount = src_box->depth;
1368       } else {
1369          region.dstOffset.z = dstz;
1370          region.dstSubresource.layerCount = 1;
1371       }
1372
1373       region.dstOffset.x = dstx;
1374       region.dstOffset.y = dsty;
1375       region.extent.width = src_box->width;
1376       region.extent.height = src_box->height;
1377
1378       struct zink_batch *batch = zink_batch_no_rp(ctx);
1379       zink_batch_reference_resoure(batch, src);
1380       zink_batch_reference_resoure(batch, dst);
1381
1382       if (src->layout != VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL &&
1383           src->layout != VK_IMAGE_LAYOUT_GENERAL) {
1384          zink_resource_barrier(batch->cmdbuf, src, src->aspect,
1385                                VK_IMAGE_LAYOUT_GENERAL);
1386          src->layout = VK_IMAGE_LAYOUT_GENERAL;
1387       }
1388
1389       if (dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1390           dst->layout != VK_IMAGE_LAYOUT_GENERAL) {
1391          zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1392                                VK_IMAGE_LAYOUT_GENERAL);
1393          dst->layout = VK_IMAGE_LAYOUT_GENERAL;
1394       }
1395
1396       vkCmdCopyImage(batch->cmdbuf, src->image, src->layout,
1397                      dst->image, dst->layout,
1398                      1, &region);
1399    } else
1400       debug_printf("zink: TODO resource copy\n");
1401 }
1402
1403 struct pipe_context *
1404 zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
1405 {
1406    struct zink_screen *screen = zink_screen(pscreen);
1407    struct zink_context *ctx = CALLOC_STRUCT(zink_context);
1408
1409    ctx->base.screen = pscreen;
1410    ctx->base.priv = priv;
1411
1412    ctx->base.destroy = zink_context_destroy;
1413
1414    zink_context_state_init(&ctx->base);
1415
1416    ctx->base.create_sampler_state = zink_create_sampler_state;
1417    ctx->base.bind_sampler_states = zink_bind_sampler_states;
1418    ctx->base.delete_sampler_state = zink_delete_sampler_state;
1419
1420    ctx->base.create_sampler_view = zink_create_sampler_view;
1421    ctx->base.set_sampler_views = zink_set_sampler_views;
1422    ctx->base.sampler_view_destroy = zink_sampler_view_destroy;
1423
1424    ctx->base.create_vs_state = zink_create_vs_state;
1425    ctx->base.bind_vs_state = zink_bind_vs_state;
1426    ctx->base.delete_vs_state = zink_delete_vs_state;
1427
1428    ctx->base.create_fs_state = zink_create_fs_state;
1429    ctx->base.bind_fs_state = zink_bind_fs_state;
1430    ctx->base.delete_fs_state = zink_delete_fs_state;
1431
1432    ctx->base.set_polygon_stipple = zink_set_polygon_stipple;
1433    ctx->base.set_vertex_buffers = zink_set_vertex_buffers;
1434    ctx->base.set_viewport_states = zink_set_viewport_states;
1435    ctx->base.set_scissor_states = zink_set_scissor_states;
1436    ctx->base.set_constant_buffer = zink_set_constant_buffer;
1437    ctx->base.set_framebuffer_state = zink_set_framebuffer_state;
1438    ctx->base.set_stencil_ref = zink_set_stencil_ref;
1439    ctx->base.set_clip_state = zink_set_clip_state;
1440    ctx->base.set_blend_color = zink_set_blend_color;
1441
1442    ctx->base.set_sample_mask = zink_set_sample_mask;
1443
1444    ctx->base.clear = zink_clear;
1445    ctx->base.draw_vbo = zink_draw_vbo;
1446    ctx->base.flush = zink_flush;
1447
1448    ctx->base.resource_copy_region = zink_resource_copy_region;
1449    ctx->base.blit = zink_blit;
1450
1451    ctx->base.flush_resource = zink_flush_resource;
1452    zink_context_surface_init(&ctx->base);
1453    zink_context_resource_init(&ctx->base);
1454    zink_context_query_init(&ctx->base);
1455
1456    slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
1457
1458    ctx->base.stream_uploader = u_upload_create_default(&ctx->base);
1459    ctx->base.const_uploader = ctx->base.stream_uploader;
1460
1461    int prim_hwsupport = 1 << PIPE_PRIM_POINTS |
1462                         1 << PIPE_PRIM_LINES |
1463                         1 << PIPE_PRIM_LINE_STRIP |
1464                         1 << PIPE_PRIM_TRIANGLES |
1465                         1 << PIPE_PRIM_TRIANGLE_STRIP |
1466                         1 << PIPE_PRIM_TRIANGLE_FAN;
1467
1468    ctx->primconvert = util_primconvert_create(&ctx->base, prim_hwsupport);
1469    if (!ctx->primconvert)
1470       goto fail;
1471
1472    ctx->blitter = util_blitter_create(&ctx->base);
1473    if (!ctx->blitter)
1474       goto fail;
1475
1476    VkCommandPoolCreateInfo cpci = {};
1477    cpci.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO;
1478    cpci.queueFamilyIndex = screen->gfx_queue;
1479    cpci.flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT;
1480    if (vkCreateCommandPool(screen->dev, &cpci, NULL, &ctx->cmdpool) != VK_SUCCESS)
1481       goto fail;
1482
1483    VkCommandBufferAllocateInfo cbai = {};
1484    cbai.sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO;
1485    cbai.commandPool = ctx->cmdpool;
1486    cbai.level = VK_COMMAND_BUFFER_LEVEL_PRIMARY;
1487    cbai.commandBufferCount = 1;
1488
1489    VkDescriptorPoolSize sizes[] = {
1490       {VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER, ZINK_BATCH_DESC_SIZE}
1491    };
1492    VkDescriptorPoolCreateInfo dpci = {};
1493    dpci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO;
1494    dpci.pPoolSizes = sizes;
1495    dpci.poolSizeCount = ARRAY_SIZE(sizes);
1496    dpci.flags = VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT;
1497    dpci.maxSets = ZINK_BATCH_DESC_SIZE;
1498
1499    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i) {
1500       if (vkAllocateCommandBuffers(screen->dev, &cbai, &ctx->batches[i].cmdbuf) != VK_SUCCESS)
1501          goto fail;
1502
1503       ctx->batches[i].resources = _mesa_set_create(NULL, _mesa_hash_pointer,
1504                                                    _mesa_key_pointer_equal);
1505       ctx->batches[i].sampler_views = _mesa_set_create(NULL,
1506                                                        _mesa_hash_pointer,
1507                                                        _mesa_key_pointer_equal);
1508
1509       if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views)
1510          goto fail;
1511
1512       util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL);
1513
1514       if (vkCreateDescriptorPool(screen->dev, &dpci, 0,
1515                                  &ctx->batches[i].descpool) != VK_SUCCESS)
1516          goto fail;
1517    }
1518
1519    vkGetDeviceQueue(screen->dev, screen->gfx_queue, 0, &ctx->queue);
1520
1521    ctx->program_cache = _mesa_hash_table_create(NULL,
1522                                                 hash_gfx_program,
1523                                                 equals_gfx_program);
1524    ctx->render_pass_cache = _mesa_hash_table_create(NULL,
1525                                                     hash_render_pass_state,
1526                                                     equals_render_pass_state);
1527    ctx->framebuffer_cache = _mesa_hash_table_create(NULL,
1528                                                     hash_framebuffer_state,
1529                                                     equals_framebuffer_state);
1530
1531    if (!ctx->program_cache || !ctx->render_pass_cache ||
1532        !ctx->framebuffer_cache)
1533       goto fail;
1534
1535    ctx->dirty = ZINK_DIRTY_PROGRAM;
1536
1537    /* start the first batch */
1538    zink_start_batch(ctx, zink_curr_batch(ctx));
1539
1540    return &ctx->base;
1541
1542 fail:
1543    if (ctx) {
1544       vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
1545       FREE(ctx);
1546    }
1547    return NULL;
1548 }