projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
zink: fixup scissoring
[mesa.git] / src / gallium / drivers / zink / zink_context.c
1 /*
2 * Copyright 2018 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "zink_context.h"
25
26 #include "zink_batch.h"
27 #include "zink_compiler.h"
28 #include "zink_fence.h"
29 #include "zink_framebuffer.h"
30 #include "zink_pipeline.h"
31 #include "zink_program.h"
32 #include "zink_render_pass.h"
33 #include "zink_resource.h"
34 #include "zink_screen.h"
35 #include "zink_state.h"
36 #include "zink_surface.h"
37
38 #include "indices/u_primconvert.h"
39 #include "util/u_blitter.h"
40 #include "util/u_debug.h"
41 #include "util/u_format.h"
42 #include "util/u_framebuffer.h"
43 #include "util/u_helpers.h"
44 #include "util/u_inlines.h"
45
46 #include "nir.h"
47
48 #include "util/u_memory.h"
49 #include "util/u_prim.h"
50 #include "util/u_upload_mgr.h"
51
52 static void
53 zink_context_destroy(struct pipe_context *pctx)
54 {
55 struct zink_context *ctx = zink_context(pctx);
56 struct zink_screen *screen = zink_screen(pctx->screen);
57
58 if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS)
59 debug_printf("vkQueueWaitIdle failed\n");
60
61 for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i)
62 vkFreeCommandBuffers(screen->dev, ctx->cmdpool, 1, &ctx->batches[i].cmdbuf);
63 vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
64
65 util_primconvert_destroy(ctx->primconvert);
66 u_upload_destroy(pctx->stream_uploader);
67 slab_destroy_child(&ctx->transfer_pool);
68 util_blitter_destroy(ctx->blitter);
69 FREE(ctx);
70 }
71
72 static VkFilter
73 filter(enum pipe_tex_filter filter)
74 {
75 switch (filter) {
76 case PIPE_TEX_FILTER_NEAREST: return VK_FILTER_NEAREST;
77 case PIPE_TEX_FILTER_LINEAR: return VK_FILTER_LINEAR;
78 }
79 unreachable("unexpected filter");
80 }
81
82 static VkSamplerMipmapMode
83 sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
84 {
85 switch (filter) {
86 case PIPE_TEX_MIPFILTER_NEAREST: return VK_SAMPLER_MIPMAP_MODE_NEAREST;
87 case PIPE_TEX_MIPFILTER_LINEAR: return VK_SAMPLER_MIPMAP_MODE_LINEAR;
88 case PIPE_TEX_MIPFILTER_NONE:
89 unreachable("PIPE_TEX_MIPFILTER_NONE should be dealt with earlier");
90 }
91 unreachable("unexpected filter");
92 }
93
94 static VkSamplerAddressMode
95 sampler_address_mode(enum pipe_tex_wrap filter)
96 {
97 switch (filter) {
98 case PIPE_TEX_WRAP_REPEAT: return VK_SAMPLER_ADDRESS_MODE_REPEAT;
99 case PIPE_TEX_WRAP_CLAMP: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
100 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE;
101 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
102 case PIPE_TEX_WRAP_MIRROR_REPEAT: return VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT;
103 case PIPE_TEX_WRAP_MIRROR_CLAMP: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
104 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE;
105 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
106 }
107 unreachable("unexpected wrap");
108 }
109
110 static VkCompareOp
111 compare_op(enum pipe_compare_func op)
112 {
113 switch (op) {
114 case PIPE_FUNC_NEVER: return VK_COMPARE_OP_NEVER;
115 case PIPE_FUNC_LESS: return VK_COMPARE_OP_LESS;
116 case PIPE_FUNC_EQUAL: return VK_COMPARE_OP_EQUAL;
117 case PIPE_FUNC_LEQUAL: return VK_COMPARE_OP_LESS_OR_EQUAL;
118 case PIPE_FUNC_GREATER: return VK_COMPARE_OP_GREATER;
119 case PIPE_FUNC_NOTEQUAL: return VK_COMPARE_OP_NOT_EQUAL;
120 case PIPE_FUNC_GEQUAL: return VK_COMPARE_OP_GREATER_OR_EQUAL;
121 case PIPE_FUNC_ALWAYS: return VK_COMPARE_OP_ALWAYS;
122 }
123 unreachable("unexpected compare");
124 }
125
126 static void *
127 zink_create_sampler_state(struct pipe_context *pctx,
128 const struct pipe_sampler_state *state)
129 {
130 struct zink_screen *screen = zink_screen(pctx->screen);
131
132 VkSamplerCreateInfo sci = {};
133 sci.sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO;
134 sci.magFilter = filter(state->mag_img_filter);
135 sci.minFilter = filter(state->min_img_filter);
136
137 if (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
138 sci.mipmapMode = sampler_mipmap_mode(state->min_mip_filter);
139 sci.minLod = state->min_lod;
140 sci.maxLod = state->max_lod;
141 } else {
142 sci.mipmapMode = VK_SAMPLER_MIPMAP_MODE_NEAREST;
143 sci.minLod = 0;
144 sci.maxLod = 0;
145 }
146
147 sci.addressModeU = sampler_address_mode(state->wrap_s);
148 sci.addressModeV = sampler_address_mode(state->wrap_t);
149 sci.addressModeW = sampler_address_mode(state->wrap_r);
150 sci.mipLodBias = state->lod_bias;
151
152 if (state->compare_mode == PIPE_TEX_COMPARE_NONE)
153 sci.compareOp = VK_COMPARE_OP_NEVER;
154 else
155 sci.compareOp = compare_op(state->compare_func);
156
157 sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO
158 sci.unnormalizedCoordinates = !state->normalized_coords;
159
160 if (state->max_anisotropy > 1) {
161 sci.maxAnisotropy = state->max_anisotropy;
162 sci.anisotropyEnable = VK_TRUE;
163 }
164
165 VkSampler sampler;
166 VkResult err = vkCreateSampler(screen->dev, &sci, NULL, &sampler);
167 if (err != VK_SUCCESS)
168 return NULL;
169
170 return sampler;
171 }
172
173 static void
174 zink_bind_sampler_states(struct pipe_context *pctx,
175 enum pipe_shader_type shader,
176 unsigned start_slot,
177 unsigned num_samplers,
178 void **samplers)
179 {
180 struct zink_context *ctx = zink_context(pctx);
181 for (unsigned i = 0; i < num_samplers; ++i)
182 ctx->samplers[shader][start_slot + i] = (VkSampler)samplers[i];
183 ctx->num_samplers[shader] = start_slot + num_samplers;
184 }
185
186 static void
187 zink_delete_sampler_state(struct pipe_context *pctx,
188 void *sampler_state)
189 {
190 struct zink_batch *batch = zink_curr_batch(zink_context(pctx));
191 util_dynarray_append(&batch->zombie_samplers,
192 VkSampler, sampler_state);
193 }
194
195
196 static VkImageViewType
197 image_view_type(enum pipe_texture_target target)
198 {
199 switch (target) {
200 case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
201 case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
202 case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
203 case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
204 case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
205 case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
206 case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
207 case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D; /* not sure */
208 default:
209 unreachable("unexpected target");
210 }
211 }
212
213 static VkComponentSwizzle
214 component_mapping(enum pipe_swizzle swizzle)
215 {
216 switch (swizzle) {
217 case PIPE_SWIZZLE_X: return VK_COMPONENT_SWIZZLE_R;
218 case PIPE_SWIZZLE_Y: return VK_COMPONENT_SWIZZLE_G;
219 case PIPE_SWIZZLE_Z: return VK_COMPONENT_SWIZZLE_B;
220 case PIPE_SWIZZLE_W: return VK_COMPONENT_SWIZZLE_A;
221 case PIPE_SWIZZLE_0: return VK_COMPONENT_SWIZZLE_ZERO;
222 case PIPE_SWIZZLE_1: return VK_COMPONENT_SWIZZLE_ONE;
223 case PIPE_SWIZZLE_NONE: return VK_COMPONENT_SWIZZLE_IDENTITY; // ???
224 default:
225 unreachable("unexpected swizzle");
226 }
227 }
228
229 static VkImageAspectFlags
230 sampler_aspect_from_format(enum pipe_format fmt)
231 {
232 if (util_format_is_depth_or_stencil(fmt)) {
233 const struct util_format_description *desc = util_format_description(fmt);
234 if (util_format_has_depth(desc))
235 return VK_IMAGE_ASPECT_DEPTH_BIT;
236 assert(util_format_has_stencil(desc));
237 return VK_IMAGE_ASPECT_STENCIL_BIT;
238 } else
239 return VK_IMAGE_ASPECT_COLOR_BIT;
240 }
241
242 static struct pipe_sampler_view *
243 zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
244 const struct pipe_sampler_view *state)
245 {
246 struct zink_screen *screen = zink_screen(pctx->screen);
247 struct zink_resource *res = zink_resource(pres);
248 struct zink_sampler_view *sampler_view = CALLOC_STRUCT(zink_sampler_view);
249
250 sampler_view->base = *state;
251 sampler_view->base.texture = NULL;
252 pipe_resource_reference(&sampler_view->base.texture, pres);
253 sampler_view->base.reference.count = 1;
254 sampler_view->base.context = pctx;
255
256 VkImageViewCreateInfo ivci = {};
257 ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
258 ivci.image = res->image;
259 ivci.viewType = image_view_type(state->target);
260 ivci.format = zink_get_format(state->format);
261 ivci.components.r = component_mapping(state->swizzle_r);
262 ivci.components.g = component_mapping(state->swizzle_g);
263 ivci.components.b = component_mapping(state->swizzle_b);
264 ivci.components.a = component_mapping(state->swizzle_a);
265
266 ivci.subresourceRange.aspectMask = sampler_aspect_from_format(state->format);
267 ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
268 ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
269 ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
270 ivci.subresourceRange.layerCount = state->u.tex.last_layer - state->u.tex.first_layer + 1;
271
272 VkResult err = vkCreateImageView(screen->dev, &ivci, NULL, &sampler_view->image_view);
273 if (err != VK_SUCCESS) {
274 FREE(sampler_view);
275 return NULL;
276 }
277
278 return &sampler_view->base;
279 }
280
281 static void
282 zink_sampler_view_destroy(struct pipe_context *pctx,
283 struct pipe_sampler_view *pview)
284 {
285 struct zink_sampler_view *view = zink_sampler_view(pview);
286 vkDestroyImageView(zink_screen(pctx->screen)->dev, view->image_view, NULL);
287 FREE(view);
288 }
289
290 static void *
291 zink_create_vs_state(struct pipe_context *pctx,
292 const struct pipe_shader_state *shader)
293 {
294 struct nir_shader *nir;
295 if (shader->type != PIPE_SHADER_IR_NIR)
296 nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
297 else
298 nir = (struct nir_shader *)shader->ir.nir;
299
300 return zink_compile_nir(zink_screen(pctx->screen), nir);
301 }
302
303 static void
304 bind_stage(struct zink_context *ctx, enum pipe_shader_type stage,
305 struct zink_shader *shader)
306 {
307 assert(stage < PIPE_SHADER_COMPUTE);
308 ctx->gfx_stages[stage] = shader;
309 ctx->dirty |= ZINK_DIRTY_PROGRAM;
310 }
311
312 static void
313 zink_bind_vs_state(struct pipe_context *pctx,
314 void *cso)
315 {
316 bind_stage(zink_context(pctx), PIPE_SHADER_VERTEX, cso);
317 }
318
319 static void
320 zink_delete_vs_state(struct pipe_context *pctx,
321 void *cso)
322 {
323 zink_shader_free(zink_screen(pctx->screen), cso);
324 }
325
326 static void *
327 zink_create_fs_state(struct pipe_context *pctx,
328 const struct pipe_shader_state *shader)
329 {
330 struct nir_shader *nir;
331 if (shader->type != PIPE_SHADER_IR_NIR)
332 nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
333 else
334 nir = (struct nir_shader *)shader->ir.nir;
335
336 return zink_compile_nir(zink_screen(pctx->screen), nir);
337 }
338
339 static void
340 zink_bind_fs_state(struct pipe_context *pctx,
341 void *cso)
342 {
343 bind_stage(zink_context(pctx), PIPE_SHADER_FRAGMENT, cso);
344 }
345
346 static void
347 zink_delete_fs_state(struct pipe_context *pctx,
348 void *cso)
349 {
350 zink_shader_free(zink_screen(pctx->screen), cso);
351 }
352
353 static void
354 zink_set_polygon_stipple(struct pipe_context *pctx,
355 const struct pipe_poly_stipple *ps)
356 {
357 }
358
359 static void
360 zink_set_vertex_buffers(struct pipe_context *pctx,
361 unsigned start_slot,
362 unsigned num_buffers,
363 const struct pipe_vertex_buffer *buffers)
364 {
365 struct zink_context *ctx = zink_context(pctx);
366
367 if (buffers) {
368 for (int i = 0; i < num_buffers; ++i) {
369 const struct pipe_vertex_buffer *vb = buffers + i;
370 ctx->gfx_pipeline_state.bindings[start_slot + i].stride = vb->stride;
371 }
372 }
373
374 util_set_vertex_buffers_mask(ctx->buffers, &ctx->buffers_enabled_mask,
375 buffers, start_slot, num_buffers);
376 }
377
378 static void
379 zink_set_viewport_states(struct pipe_context *pctx,
380 unsigned start_slot,
381 unsigned num_viewports,
382 const struct pipe_viewport_state *state)
383 {
384 struct zink_context *ctx = zink_context(pctx);
385
386 for (unsigned i = 0; i < num_viewports; ++i) {
387 VkViewport viewport = {
388 state[i].translate[0] - state[i].scale[0],
389 state[i].translate[1] - state[i].scale[1],
390 state[i].scale[0] * 2,
391 state[i].scale[1] * 2,
392 state[i].translate[2] - state[i].scale[2],
393 state[i].translate[2] + state[i].scale[2]
394 };
395 ctx->viewport_states[start_slot + i] = state[i];
396 ctx->viewports[start_slot + i] = viewport;
397 }
398 ctx->num_viewports = start_slot + num_viewports;
399 }
400
401 static void
402 zink_set_scissor_states(struct pipe_context *pctx,
403 unsigned start_slot, unsigned num_scissors,
404 const struct pipe_scissor_state *states)
405 {
406 struct zink_context *ctx = zink_context(pctx);
407
408 for (unsigned i = 0; i < num_scissors; i++) {
409 VkRect2D scissor;
410
411 scissor.offset.x = states[i].minx;
412 scissor.offset.y = states[i].miny;
413 scissor.extent.width = states[i].maxx - states[i].minx;
414 scissor.extent.height = states[i].maxy - states[i].miny;
415 ctx->scissor_states[start_slot + i] = states[i];
416 ctx->scissors[start_slot + i] = scissor;
417 }
418 }
419
420 static void
421 zink_set_constant_buffer(struct pipe_context *pctx,
422 enum pipe_shader_type shader, uint index,
423 const struct pipe_constant_buffer *cb)
424 {
425 struct zink_context *ctx = zink_context(pctx);
426
427 if (cb) {
428 struct pipe_resource *buffer = cb->buffer;
429 unsigned offset = cb->buffer_offset;
430 if (cb->user_buffer) {
431 struct zink_screen *screen = zink_screen(pctx->screen);
432 u_upload_data(ctx->base.const_uploader, 0, cb->buffer_size,
433 screen->props.limits.minUniformBufferOffsetAlignment,
434 cb->user_buffer, &offset, &buffer);
435 }
436
437 pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
438 ctx->ubos[shader][index].buffer_offset = offset;
439 ctx->ubos[shader][index].buffer_size = cb->buffer_size;
440 ctx->ubos[shader][index].user_buffer = NULL;
441
442 if (cb->user_buffer)
443 pipe_resource_reference(&buffer, NULL);
444 } else {
445 pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
446 ctx->ubos[shader][index].buffer_offset = 0;
447 ctx->ubos[shader][index].buffer_size = 0;
448 ctx->ubos[shader][index].user_buffer = NULL;
449 }
450 }
451
452 static void
453 zink_set_sampler_views(struct pipe_context *pctx,
454 enum pipe_shader_type shader_type,
455 unsigned start_slot,
456 unsigned num_views,
457 struct pipe_sampler_view **views)
458 {
459 struct zink_context *ctx = zink_context(pctx);
460 assert(views);
461 for (unsigned i = 0; i < num_views; ++i) {
462 pipe_sampler_view_reference(
463 &ctx->image_views[shader_type][start_slot + i],
464 views[i]);
465 }
466 ctx->num_image_views[shader_type] = start_slot + num_views;
467 }
468
469 static void
470 zink_set_stencil_ref(struct pipe_context *pctx,
471 const struct pipe_stencil_ref *ref)
472 {
473 struct zink_context *ctx = zink_context(pctx);
474 ctx->stencil_ref = *ref;
475 }
476
477 static void
478 zink_set_clip_state(struct pipe_context *pctx,
479 const struct pipe_clip_state *pcs)
480 {
481 }
482
483 static struct zink_render_pass *
484 get_render_pass(struct zink_context *ctx)
485 {
486 struct zink_screen *screen = zink_screen(ctx->base.screen);
487 const struct pipe_framebuffer_state *fb = &ctx->fb_state;
488 struct zink_render_pass_state state;
489
490 for (int i = 0; i < fb->nr_cbufs; i++) {
491 struct zink_resource *cbuf = zink_resource(fb->cbufs[i]->texture);
492 state.rts[i].format = cbuf->format;
493 state.rts[i].samples = cbuf->base.nr_samples > 0 ? cbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
494 }
495 state.num_cbufs = fb->nr_cbufs;
496
497 if (fb->zsbuf) {
498 struct zink_resource *zsbuf = zink_resource(fb->zsbuf->texture);
499 state.rts[fb->nr_cbufs].format = zsbuf->format;
500 state.rts[fb->nr_cbufs].samples = zsbuf->base.nr_samples > 0 ? zsbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
501 }
502 state.have_zsbuf = fb->zsbuf != NULL;
503
504 struct hash_entry *entry = _mesa_hash_table_search(ctx->render_pass_cache,
505 &state);
506 if (!entry) {
507 struct zink_render_pass *rp;
508 rp = zink_create_render_pass(screen, &state);
509 entry = _mesa_hash_table_insert(ctx->render_pass_cache, &state, rp);
510 if (!entry)
511 return NULL;
512 }
513
514 return entry->data;
515 }
516
517 static struct zink_framebuffer *
518 get_framebuffer(struct zink_context *ctx)
519 {
520 struct zink_screen *screen = zink_screen(ctx->base.screen);
521
522 struct zink_framebuffer_state state = {};
523 state.rp = get_render_pass(ctx);
524 for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
525 struct pipe_surface *psurf = ctx->fb_state.cbufs[i];
526 state.attachments[i] = zink_surface(psurf);
527 }
528
529 state.num_attachments = ctx->fb_state.nr_cbufs;
530 if (ctx->fb_state.zsbuf) {
531 struct pipe_surface *psurf = ctx->fb_state.zsbuf;
532 state.attachments[state.num_attachments++] = zink_surface(psurf);
533 }
534
535 state.width = ctx->fb_state.width;
536 state.height = ctx->fb_state.height;
537 state.layers = MAX2(ctx->fb_state.layers, 1);
538
539 struct hash_entry *entry = _mesa_hash_table_search(ctx->framebuffer_cache,
540 &state);
541 if (!entry) {
542 struct zink_framebuffer *fb = zink_create_framebuffer(screen, &state);
543 entry = _mesa_hash_table_insert(ctx->framebuffer_cache, &state, fb);
544 if (!entry)
545 return NULL;
546 }
547
548 return entry->data;
549 }
550
551 void
552 zink_begin_render_pass(struct zink_context *ctx, struct zink_batch *batch)
553 {
554 struct zink_screen *screen = zink_screen(ctx->base.screen);
555 assert(batch == zink_curr_batch(ctx));
556 assert(ctx->gfx_pipeline_state.render_pass);
557
558 VkRenderPassBeginInfo rpbi = {};
559 rpbi.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO;
560 rpbi.renderPass = ctx->gfx_pipeline_state.render_pass->render_pass;
561 rpbi.renderArea.offset.x = 0;
562 rpbi.renderArea.offset.y = 0;
563 rpbi.renderArea.extent.width = ctx->fb_state.width;
564 rpbi.renderArea.extent.height = ctx->fb_state.height;
565 rpbi.clearValueCount = 0;
566 rpbi.pClearValues = NULL;
567 rpbi.framebuffer = ctx->framebuffer->fb;
568
569 assert(ctx->gfx_pipeline_state.render_pass && ctx->framebuffer);
570 assert(!batch->rp || batch->rp == ctx->gfx_pipeline_state.render_pass);
571 assert(!batch->fb || batch->fb == ctx->framebuffer);
572
573 zink_render_pass_reference(screen, &batch->rp, ctx->gfx_pipeline_state.render_pass);
574 zink_framebuffer_reference(screen, &batch->fb, ctx->framebuffer);
575
576 vkCmdBeginRenderPass(batch->cmdbuf, &rpbi, VK_SUBPASS_CONTENTS_INLINE);
577 }
578
579 static void
580 flush_batch(struct zink_context *ctx)
581 {
582 struct zink_batch *batch = zink_curr_batch(ctx);
583 if (batch->rp)
584 vkCmdEndRenderPass(batch->cmdbuf);
585
586 zink_end_batch(ctx, batch);
587
588 ctx->curr_batch++;
589 if (ctx->curr_batch == ARRAY_SIZE(ctx->batches))
590 ctx->curr_batch = 0;
591
592 zink_start_batch(ctx, zink_curr_batch(ctx));
593 }
594
595 struct zink_batch *
596 zink_batch_rp(struct zink_context *ctx)
597 {
598 struct zink_batch *batch = zink_curr_batch(ctx);
599 if (!batch->rp) {
600 zink_begin_render_pass(ctx, batch);
601 assert(batch->rp);
602 }
603 return batch;
604 }
605
606 struct zink_batch *
607 zink_batch_no_rp(struct zink_context *ctx)
608 {
609 struct zink_batch *batch = zink_curr_batch(ctx);
610 if (batch->rp) {
611 /* flush batch and get a new one */
612 flush_batch(ctx);
613 batch = zink_curr_batch(ctx);
614 assert(!batch->rp);
615 }
616 return batch;
617 }
618
619 static void
620 zink_set_framebuffer_state(struct pipe_context *pctx,
621 const struct pipe_framebuffer_state *state)
622 {
623 struct zink_context *ctx = zink_context(pctx);
624 struct zink_screen *screen = zink_screen(pctx->screen);
625
626 VkSampleCountFlagBits rast_samples = VK_SAMPLE_COUNT_1_BIT;
627 for (int i = 0; i < state->nr_cbufs; i++)
628 rast_samples = MAX2(rast_samples, state->cbufs[i]->texture->nr_samples);
629 if (state->zsbuf && state->zsbuf->texture->nr_samples)
630 rast_samples = MAX2(rast_samples, state->zsbuf->texture->nr_samples);
631
632 util_copy_framebuffer_state(&ctx->fb_state, state);
633
634 struct zink_framebuffer *fb = get_framebuffer(ctx);
635 zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
636 zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
637
638 ctx->gfx_pipeline_state.rast_samples = rast_samples;
639 ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
640
641 struct zink_batch *batch = zink_batch_no_rp(ctx);
642
643 for (int i = 0; i < state->nr_cbufs; i++) {
644 struct zink_resource *res = zink_resource(state->cbufs[i]->texture);
645 if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
646 res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
647 zink_resource_barrier(batch->cmdbuf, res, res->aspect,
648 VK_IMAGE_LAYOUT_GENERAL);
649 }
650
651 if (state->zsbuf) {
652 struct zink_resource *res = zink_resource(state->zsbuf->texture);
653 if (res->layout != VK_IMAGE_LAYOUT_GENERAL &&
654 res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
655 zink_resource_barrier(batch->cmdbuf, res, res->aspect,
656 VK_IMAGE_LAYOUT_GENERAL);
657 }
658 }
659
660 static void
661 zink_set_blend_color(struct pipe_context *pctx,
662 const struct pipe_blend_color *color)
663 {
664 struct zink_context *ctx = zink_context(pctx);
665 memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
666 }
667
668 static void
669 zink_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
670 {
671 struct zink_context *ctx = zink_context(pctx);
672 ctx->gfx_pipeline_state.sample_mask = sample_mask;
673 }
674
675 static VkAccessFlags
676 access_flags(VkImageLayout layout)
677 {
678 switch (layout) {
679 case VK_IMAGE_LAYOUT_UNDEFINED:
680 case VK_IMAGE_LAYOUT_GENERAL:
681 return 0;
682
683 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
684 return VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
685 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
686 return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
687
688 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
689 return VK_ACCESS_SHADER_READ_BIT;
690
691 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
692 return VK_ACCESS_TRANSFER_READ_BIT;
693
694 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
695 return VK_ACCESS_TRANSFER_WRITE_BIT;
696
697 case VK_IMAGE_LAYOUT_PREINITIALIZED:
698 return VK_ACCESS_HOST_WRITE_BIT;
699
700 default:
701 unreachable("unexpected layout");
702 }
703 }
704
705 void
706 zink_resource_barrier(VkCommandBuffer cmdbuf, struct zink_resource *res,
707 VkImageAspectFlags aspect, VkImageLayout new_layout)
708 {
709 VkImageSubresourceRange isr = {
710 aspect,
711 0, VK_REMAINING_MIP_LEVELS,
712 0, VK_REMAINING_ARRAY_LAYERS
713 };
714
715 VkImageMemoryBarrier imb = {
716 VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
717 NULL,
718 access_flags(res->layout),
719 access_flags(new_layout),
720 res->layout,
721 new_layout,
722 VK_QUEUE_FAMILY_IGNORED,
723 VK_QUEUE_FAMILY_IGNORED,
724 res->image,
725 isr
726 };
727 vkCmdPipelineBarrier(
728 cmdbuf,
729 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
730 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
731 0,
732 0, NULL,
733 0, NULL,
734 1, &imb
735 );
736
737 res->layout = new_layout;
738 }
739
740 static void
741 zink_clear(struct pipe_context *pctx,
742 unsigned buffers,
743 const union pipe_color_union *pcolor,
744 double depth, unsigned stencil)
745 {
746 struct zink_context *ctx = zink_context(pctx);
747 struct pipe_framebuffer_state *fb = &ctx->fb_state;
748
749 /* FIXME: this is very inefficient; if no renderpass has been started yet,
750 * we should record the clear if it's full-screen, and apply it as we
751 * start the render-pass. Otherwise we can do a partial out-of-renderpass
752 * clear.
753 */
754 struct zink_batch *batch = zink_batch_rp(ctx);
755
756 VkClearAttachment attachments[1 + PIPE_MAX_COLOR_BUFS];
757 int num_attachments = 0;
758
759 if (buffers & PIPE_CLEAR_COLOR) {
760 VkClearColorValue color;
761 color.float32[0] = pcolor->f[0];
762 color.float32[1] = pcolor->f[1];
763 color.float32[2] = pcolor->f[2];
764 color.float32[3] = pcolor->f[3];
765
766 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
767 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
768 continue;
769
770 attachments[num_attachments].aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
771 attachments[num_attachments].colorAttachment = i;
772 attachments[num_attachments].clearValue.color = color;
773 ++num_attachments;
774 }
775 }
776
777 if (buffers & PIPE_CLEAR_DEPTHSTENCIL && fb->zsbuf) {
778 VkImageAspectFlags aspect = 0;
779 if (buffers & PIPE_CLEAR_DEPTH)
780 aspect |= VK_IMAGE_ASPECT_DEPTH_BIT;
781 if (buffers & PIPE_CLEAR_STENCIL)
782 aspect |= VK_IMAGE_ASPECT_STENCIL_BIT;
783
784 attachments[num_attachments].aspectMask = aspect;
785 attachments[num_attachments].clearValue.depthStencil.depth = depth;
786 attachments[num_attachments].clearValue.depthStencil.stencil = stencil;
787 ++num_attachments;
788 }
789
790 VkClearRect cr;
791 cr.rect.offset.x = 0;
792 cr.rect.offset.y = 0;
793 cr.rect.extent.width = fb->width;
794 cr.rect.extent.height = fb->height;
795 cr.baseArrayLayer = 0;
796 cr.layerCount = util_framebuffer_get_num_layers(fb);
797 vkCmdClearAttachments(batch->cmdbuf, num_attachments, attachments, 1, &cr);
798 }
799
800 VkShaderStageFlagBits
801 zink_shader_stage(enum pipe_shader_type type)
802 {
803 VkShaderStageFlagBits stages[] = {
804 [PIPE_SHADER_VERTEX] = VK_SHADER_STAGE_VERTEX_BIT,
805 [PIPE_SHADER_FRAGMENT] = VK_SHADER_STAGE_FRAGMENT_BIT,
806 [PIPE_SHADER_GEOMETRY] = VK_SHADER_STAGE_GEOMETRY_BIT,
807 [PIPE_SHADER_TESS_CTRL] = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
808 [PIPE_SHADER_TESS_EVAL] = VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
809 [PIPE_SHADER_COMPUTE] = VK_SHADER_STAGE_COMPUTE_BIT,
810 };
811 return stages[type];
812 }
813
814 static VkDescriptorSet
815 allocate_descriptor_set(struct zink_screen *screen,
816 struct zink_batch *batch,
817 struct zink_gfx_program *prog)
818 {
819 assert(batch->descs_left >= prog->num_descriptors);
820 VkDescriptorSetAllocateInfo dsai;
821 memset((void *)&dsai, 0, sizeof(dsai));
822 dsai.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO;
823 dsai.pNext = NULL;
824 dsai.descriptorPool = batch->descpool;
825 dsai.descriptorSetCount = 1;
826 dsai.pSetLayouts = &prog->dsl;
827
828 VkDescriptorSet desc_set;
829 if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
830 debug_printf("ZINK: failed to allocate descriptor set :/");
831 return VK_NULL_HANDLE;
832 }
833
834 batch->descs_left -= prog->num_descriptors;
835 return desc_set;
836 }
837
838 static void
839 zink_bind_vertex_buffers(struct zink_batch *batch, struct zink_context *ctx)
840 {
841 VkBuffer buffers[PIPE_MAX_ATTRIBS];
842 VkDeviceSize buffer_offsets[PIPE_MAX_ATTRIBS];
843 const struct zink_vertex_elements_state *elems = ctx->element_state;
844 for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) {
845 struct pipe_vertex_buffer *vb = ctx->buffers + ctx->element_state->binding_map[i];
846 assert(vb && vb->buffer.resource);
847 struct zink_resource *res = zink_resource(vb->buffer.resource);
848 buffers[i] = res->buffer;
849 buffer_offsets[i] = vb->buffer_offset;
850 zink_batch_reference_resoure(batch, res);
851 }
852
853 if (elems->hw_state.num_bindings > 0)
854 vkCmdBindVertexBuffers(batch->cmdbuf, 0,
855 elems->hw_state.num_bindings,
856 buffers, buffer_offsets);
857 }
858
859 static uint32_t
860 hash_gfx_program(const void *key)
861 {
862 return _mesa_hash_data(key, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1));
863 }
864
865 static bool
866 equals_gfx_program(const void *a, const void *b)
867 {
868 return memcmp(a, b, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1)) == 0;
869 }
870
871 static uint32_t
872 hash_render_pass_state(const void *key)
873 {
874 return _mesa_hash_data(key, sizeof(struct zink_render_pass_state));
875 }
876
877 static bool
878 equals_render_pass_state(const void *a, const void *b)
879 {
880 return memcmp(a, b, sizeof(struct zink_render_pass_state)) == 0;
881 }
882
883 static uint32_t
884 hash_framebuffer_state(const void *key)
885 {
886 struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)key;
887 return _mesa_hash_data(key, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments);
888 }
889
890 static bool
891 equals_framebuffer_state(const void *a, const void *b)
892 {
893 struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)a;
894 return memcmp(a, b, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments) == 0;
895 }
896
897 static struct zink_gfx_program *
898 get_gfx_program(struct zink_context *ctx)
899 {
900 if (ctx->dirty & ZINK_DIRTY_PROGRAM) {
901 struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
902 ctx->gfx_stages);
903 if (!entry) {
904 struct zink_gfx_program *prog;
905 prog = zink_create_gfx_program(zink_screen(ctx->base.screen),
906 ctx->gfx_stages);
907 entry = _mesa_hash_table_insert(ctx->program_cache, prog->stages, prog);
908 if (!entry)
909 return NULL;
910 }
911 ctx->curr_program = entry->data;
912 ctx->dirty &= ~ZINK_DIRTY_PROGRAM;
913 }
914
915 assert(ctx->curr_program);
916 return ctx->curr_program;
917 }
918
919 static void
920 zink_draw_vbo(struct pipe_context *pctx,
921 const struct pipe_draw_info *dinfo)
922 {
923 struct zink_context *ctx = zink_context(pctx);
924 struct zink_screen *screen = zink_screen(pctx->screen);
925 struct zink_rasterizer_state *rast_state = ctx->rast_state;
926
927 if (dinfo->mode >= PIPE_PRIM_QUADS ||
928 dinfo->mode == PIPE_PRIM_LINE_LOOP ||
929 dinfo->index_size == 1) {
930 if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&dinfo->count))
931 return;
932
933 util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
934 util_primconvert_draw_vbo(ctx->primconvert, dinfo);
935 return;
936 }
937
938 struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
939 if (!gfx_program)
940 return;
941
942 VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
943 &ctx->gfx_pipeline_state,
944 dinfo->mode);
945
946 bool depth_bias = false;
947 switch (u_reduced_prim(dinfo->mode)) {
948 case PIPE_PRIM_POINTS:
949 depth_bias = rast_state->offset_point;
950 break;
951
952 case PIPE_PRIM_LINES:
953 depth_bias = rast_state->offset_line;
954 break;
955
956 case PIPE_PRIM_TRIANGLES:
957 depth_bias = rast_state->offset_tri;
958 break;
959
960 default:
961 unreachable("unexpected reduced prim");
962 }
963
964 unsigned index_offset = 0;
965 struct pipe_resource *index_buffer = NULL;
966 if (dinfo->index_size > 0) {
967 if (dinfo->has_user_indices) {
968 if (!util_upload_index_buffer(pctx, dinfo, &index_buffer, &index_offset)) {
969 debug_printf("util_upload_index_buffer() failed\n");
970 return;
971 }
972 } else
973 index_buffer = dinfo->index.resource;
974 }
975
976 VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS + PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
977 VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS];
978 VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
979 int num_wds = 0, num_buffer_info = 0, num_image_info = 0;
980
981 struct zink_resource *transitions[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
982 int num_transitions = 0;
983
984 for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
985 struct zink_shader *shader = ctx->gfx_stages[i];
986 if (!shader)
987 continue;
988
989 for (int j = 0; j < shader->num_bindings; j++) {
990 int index = shader->bindings[j].index;
991 if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
992 assert(ctx->ubos[i][index].buffer_size > 0);
993 assert(ctx->ubos[i][index].buffer_size <= screen->props.limits.maxUniformBufferRange);
994 assert(ctx->ubos[i][index].buffer);
995 struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
996 buffer_infos[num_buffer_info].buffer = res->buffer;
997 buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset;
998 buffer_infos[num_buffer_info].range = ctx->ubos[i][index].buffer_size;
999 wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info;
1000 ++num_buffer_info;
1001 } else {
1002 struct pipe_sampler_view *psampler_view = ctx->image_views[i][index];
1003 assert(psampler_view);
1004 struct zink_sampler_view *sampler_view = zink_sampler_view(psampler_view);
1005
1006 struct zink_resource *res = zink_resource(psampler_view->texture);
1007 VkImageLayout layout = res->layout;
1008 if (layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL &&
1009 layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL &&
1010 layout != VK_IMAGE_LAYOUT_GENERAL) {
1011 transitions[num_transitions++] = res;
1012 layout = VK_IMAGE_LAYOUT_GENERAL;
1013 }
1014 image_infos[num_image_info].imageLayout = layout;
1015 image_infos[num_image_info].imageView = sampler_view->image_view;
1016 image_infos[num_image_info].sampler = ctx->samplers[i][index];
1017 wds[num_wds].pImageInfo = image_infos + num_image_info;
1018 ++num_image_info;
1019 }
1020
1021 wds[num_wds].sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET;
1022 wds[num_wds].pNext = NULL;
1023 wds[num_wds].dstBinding = shader->bindings[j].binding;
1024 wds[num_wds].dstArrayElement = 0;
1025 wds[num_wds].descriptorCount = 1;
1026 wds[num_wds].descriptorType = shader->bindings[j].type;
1027 ++num_wds;
1028 }
1029 }
1030
1031 struct zink_batch *batch;
1032 if (num_transitions > 0) {
1033 batch = zink_batch_no_rp(ctx);
1034
1035 for (int i = 0; i < num_transitions; ++i)
1036 zink_resource_barrier(batch->cmdbuf, transitions[i],
1037 transitions[i]->aspect,
1038 VK_IMAGE_LAYOUT_GENERAL);
1039 }
1040
1041 batch = zink_batch_rp(ctx);
1042
1043 if (batch->descs_left < gfx_program->num_descriptors) {
1044 flush_batch(ctx);
1045 batch = zink_batch_rp(ctx);
1046 assert(batch->descs_left >= gfx_program->num_descriptors);
1047 }
1048
1049 VkDescriptorSet desc_set = allocate_descriptor_set(screen, batch,
1050 gfx_program);
1051 assert(desc_set != VK_NULL_HANDLE);
1052
1053 for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1054 struct zink_shader *shader = ctx->gfx_stages[i];
1055 if (!shader)
1056 continue;
1057
1058 for (int j = 0; j < shader->num_bindings; j++) {
1059 int index = shader->bindings[j].index;
1060 if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1061 struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1062 zink_batch_reference_resoure(batch, res);
1063 } else {
1064 struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->image_views[i][index]);
1065 zink_batch_reference_sampler_view(batch, sampler_view);
1066 }
1067 }
1068 }
1069
1070 vkCmdSetViewport(batch->cmdbuf, 0, ctx->num_viewports, ctx->viewports);
1071 if (ctx->rast_state->base.scissor)
1072 vkCmdSetScissor(batch->cmdbuf, 0, ctx->num_viewports, ctx->scissors);
1073 else if (ctx->fb_state.width && ctx->fb_state.height) {
1074 VkRect2D fb_scissor = {};
1075 fb_scissor.extent.width = ctx->fb_state.width;
1076 fb_scissor.extent.height = ctx->fb_state.height;
1077 vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
1078 }
1079
1080 vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref.ref_value[0]);
1081 vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref.ref_value[1]);
1082
1083 if (depth_bias)
1084 vkCmdSetDepthBias(batch->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
1085 else
1086 vkCmdSetDepthBias(batch->cmdbuf, 0.0f, 0.0f, 0.0f);
1087
1088 if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
1089 vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
1090
1091 for (int i = 0; i < num_wds; ++i)
1092 wds[i].dstSet = desc_set;
1093
1094 vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
1095
1096 vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
1097 vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
1098 gfx_program->layout, 0, 1, &desc_set, 0, NULL);
1099 zink_bind_vertex_buffers(batch, ctx);
1100
1101 if (dinfo->index_size > 0) {
1102 assert(dinfo->index_size != 1);
1103 VkIndexType index_type = dinfo->index_size == 2 ? VK_INDEX_TYPE_UINT16 : VK_INDEX_TYPE_UINT32;
1104 struct zink_resource *res = zink_resource(index_buffer);
1105 vkCmdBindIndexBuffer(batch->cmdbuf, res->buffer, index_offset, index_type);
1106 zink_batch_reference_resoure(batch, res);
1107 vkCmdDrawIndexed(batch->cmdbuf,
1108 dinfo->count, dinfo->instance_count,
1109 dinfo->start, dinfo->index_bias, dinfo->start_instance);
1110 } else
1111 vkCmdDraw(batch->cmdbuf, dinfo->count, dinfo->instance_count, dinfo->start, dinfo->start_instance);
1112
1113 if (dinfo->index_size > 0 && dinfo->has_user_indices)
1114 pipe_resource_reference(&index_buffer, NULL);
1115 }
1116
1117 static void
1118 zink_flush(struct pipe_context *pctx,
1119 struct pipe_fence_handle **pfence,
1120 enum pipe_flush_flags flags)
1121 {
1122 struct zink_context *ctx = zink_context(pctx);
1123
1124 struct zink_batch *batch = zink_curr_batch(ctx);
1125 flush_batch(ctx);
1126
1127 if (pfence)
1128 zink_fence_reference(zink_screen(pctx->screen),
1129 (struct zink_fence **)pfence,
1130 batch->fence);
1131
1132 /* HACK:
1133 * For some strange reason, we need to finish before presenting, or else
1134 * we start rendering on top of the back-buffer for the next frame. This
1135 * seems like a bug in the DRI-driver to me, because we really should
1136 * be properly protected by fences here, and the back-buffer should
1137 * either be swapped with the front-buffer, or blitted from. But for
1138 * some strange reason, neither of these things happen.
1139 */
1140 if (flags & PIPE_FLUSH_END_OF_FRAME)
1141 pctx->screen->fence_finish(pctx->screen, pctx,
1142 (struct pipe_fence_handle *)batch->fence,
1143 PIPE_TIMEOUT_INFINITE);
1144 }
1145
1146 static bool
1147 blit_resolve(struct zink_context *ctx, const struct pipe_blit_info *info)
1148 {
1149 if (info->mask != PIPE_MASK_RGBA ||
1150 info->scissor_enable ||
1151 info->alpha_blend)
1152 return false;
1153
1154 struct zink_resource *src = zink_resource(info->src.resource);
1155 struct zink_resource *dst = zink_resource(info->dst.resource);
1156
1157 struct zink_batch *batch = zink_batch_no_rp(ctx);
1158
1159 zink_batch_reference_resoure(batch, src);
1160 zink_batch_reference_resoure(batch, dst);
1161
1162 VkImageResolve region = {};
1163
1164 region.srcSubresource.aspectMask = src->aspect;
1165 region.srcSubresource.mipLevel = info->src.level;
1166 region.srcSubresource.baseArrayLayer = 0; // no clue
1167 region.srcSubresource.layerCount = 1; // no clue
1168 region.srcOffset.x = info->src.box.x;
1169 region.srcOffset.y = info->src.box.y;
1170 region.srcOffset.z = info->src.box.z;
1171
1172 region.dstSubresource.aspectMask = dst->aspect;
1173 region.dstSubresource.mipLevel = info->dst.level;
1174 region.dstSubresource.baseArrayLayer = 0; // no clue
1175 region.dstSubresource.layerCount = 1; // no clue
1176 region.dstOffset.x = info->dst.box.x;
1177 region.dstOffset.y = info->dst.box.y;
1178 region.dstOffset.z = info->dst.box.z;
1179
1180 region.extent.width = info->dst.box.width;
1181 region.extent.height = info->dst.box.height;
1182 region.extent.depth = info->dst.box.depth;
1183 vkCmdResolveImage(batch->cmdbuf, src->image, src->layout,
1184 dst->image, dst->layout,
1185 1, &region);
1186
1187 /* HACK: I have no idea why this is needed, but without it ioquake3
1188 * randomly keeps fading to black.
1189 */
1190 flush_batch(ctx);
1191
1192 return true;
1193 }
1194
1195 static bool
1196 blit_native(struct zink_context *ctx, const struct pipe_blit_info *info)
1197 {
1198 if (info->mask != PIPE_MASK_RGBA ||
1199 info->scissor_enable ||
1200 info->alpha_blend)
1201 return false;
1202
1203 struct zink_resource *src = zink_resource(info->src.resource);
1204 struct zink_resource *dst = zink_resource(info->dst.resource);
1205
1206 struct zink_batch *batch = zink_batch_no_rp(ctx);
1207 zink_batch_reference_resoure(batch, src);
1208 zink_batch_reference_resoure(batch, dst);
1209
1210 if (dst->layout != VK_IMAGE_LAYOUT_GENERAL &&
1211 dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL)
1212 zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1213 VK_IMAGE_LAYOUT_GENERAL);
1214
1215 VkImageBlit region = {};
1216 region.srcSubresource.aspectMask = src->aspect;
1217 region.srcSubresource.mipLevel = info->src.level;
1218 region.srcOffsets[0].x = info->src.box.x;
1219 region.srcOffsets[0].y = info->src.box.y;
1220 region.srcOffsets[1].x = info->src.box.x + info->src.box.width;
1221 region.srcOffsets[1].y = info->src.box.y + info->src.box.height;
1222
1223 if (src->base.array_size > 1) {
1224 region.srcOffsets[0].z = 0;
1225 region.srcOffsets[1].z = 1;
1226 region.srcSubresource.baseArrayLayer = info->src.box.z;
1227 region.srcSubresource.layerCount = info->src.box.depth;
1228 } else {
1229 region.srcOffsets[0].z = info->src.box.z;
1230 region.srcOffsets[1].z = info->src.box.z + info->src.box.depth;
1231 region.srcSubresource.baseArrayLayer = 0;
1232 region.srcSubresource.layerCount = 1;
1233 }
1234
1235 region.dstSubresource.aspectMask = dst->aspect;
1236 region.dstSubresource.mipLevel = info->dst.level;
1237 region.dstOffsets[0].x = info->dst.box.x;
1238 region.dstOffsets[0].y = info->dst.box.y;
1239 region.dstOffsets[1].x = info->dst.box.x + info->dst.box.width;
1240 region.dstOffsets[1].y = info->dst.box.y + info->dst.box.height;
1241
1242 if (dst->base.array_size > 1) {
1243 region.dstOffsets[0].z = 0;
1244 region.dstOffsets[1].z = 1;
1245 region.dstSubresource.baseArrayLayer = info->dst.box.z;
1246 region.dstSubresource.layerCount = info->dst.box.depth;
1247 } else {
1248 region.dstOffsets[0].z = info->dst.box.z;
1249 region.dstOffsets[1].z = info->dst.box.z + info->dst.box.depth;
1250 region.dstSubresource.baseArrayLayer = 0;
1251 region.dstSubresource.layerCount = 1;
1252 }
1253
1254 vkCmdBlitImage(batch->cmdbuf, src->image, src->layout,
1255 dst->image, dst->layout,
1256 1, &region,
1257 filter(info->filter));
1258
1259 /* HACK: I have no idea why this is needed, but without it ioquake3
1260 * randomly keeps fading to black.
1261 */
1262 flush_batch(ctx);
1263
1264 return true;
1265 }
1266
1267 static void
1268 zink_blit(struct pipe_context *pctx,
1269 const struct pipe_blit_info *info)
1270 {
1271 struct zink_context *ctx = zink_context(pctx);
1272 if (info->src.resource->nr_samples > 1 &&
1273 info->dst.resource->nr_samples <= 1) {
1274 if (blit_resolve(ctx, info))
1275 return;
1276 } else {
1277 if (blit_native(ctx, info))
1278 return;
1279 }
1280
1281 if (!util_blitter_is_blit_supported(ctx->blitter, info)) {
1282 debug_printf("blit unsupported %s -> %s\n",
1283 util_format_short_name(info->src.resource->format),
1284 util_format_short_name(info->dst.resource->format));
1285 return;
1286 }
1287
1288 util_blitter_save_blend(ctx->blitter, ctx->gfx_pipeline_state.blend_state);
1289 util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->gfx_pipeline_state.depth_stencil_alpha_state);
1290 util_blitter_save_vertex_elements(ctx->blitter, ctx->element_state);
1291 util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
1292 util_blitter_save_rasterizer(ctx->blitter, ctx->rast_state);
1293 util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
1294 util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
1295 util_blitter_save_framebuffer(ctx->blitter, &ctx->fb_state);
1296 util_blitter_save_viewport(ctx->blitter, ctx->viewport_states);
1297 util_blitter_save_scissor(ctx->blitter, ctx->scissor_states);
1298 util_blitter_save_fragment_sampler_states(ctx->blitter,
1299 ctx->num_samplers[PIPE_SHADER_FRAGMENT],
1300 (void **)ctx->samplers[PIPE_SHADER_FRAGMENT]);
1301 util_blitter_save_fragment_sampler_views(ctx->blitter,
1302 ctx->num_image_views[PIPE_SHADER_FRAGMENT],
1303 ctx->image_views[PIPE_SHADER_FRAGMENT]);
1304 util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[PIPE_SHADER_FRAGMENT]);
1305 util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->buffers);
1306 util_blitter_save_sample_mask(ctx->blitter, ctx->gfx_pipeline_state.sample_mask);
1307
1308 util_blitter_blit(ctx->blitter, info);
1309 }
1310
1311 static void
1312 zink_flush_resource(struct pipe_context *pipe,
1313 struct pipe_resource *resource)
1314 {
1315 }
1316
1317 static void
1318 zink_resource_copy_region(struct pipe_context *pctx,
1319 struct pipe_resource *pdst,
1320 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1321 struct pipe_resource *psrc,
1322 unsigned src_level, const struct pipe_box *src_box)
1323 {
1324 struct zink_resource *dst = zink_resource(pdst);
1325 struct zink_resource *src = zink_resource(psrc);
1326 struct zink_context *ctx = zink_context(pctx);
1327 if (dst->base.target != PIPE_BUFFER && src->base.target != PIPE_BUFFER) {
1328 VkImageCopy region = {};
1329
1330 region.srcSubresource.aspectMask = src->aspect;
1331 region.srcSubresource.mipLevel = src_level;
1332 region.srcSubresource.layerCount = 1;
1333 if (src->base.array_size > 1) {
1334 region.srcSubresource.baseArrayLayer = src_box->z;
1335 region.srcSubresource.layerCount = src_box->depth;
1336 region.extent.depth = 1;
1337 } else {
1338 region.srcOffset.z = src_box->z;
1339 region.srcSubresource.layerCount = 1;
1340 region.extent.depth = src_box->depth;
1341 }
1342
1343 region.srcOffset.x = src_box->x;
1344 region.srcOffset.y = src_box->y;
1345
1346 region.dstSubresource.aspectMask = dst->aspect;
1347 region.dstSubresource.mipLevel = dst_level;
1348 if (dst->base.array_size > 1) {
1349 region.dstSubresource.baseArrayLayer = dstz;
1350 region.dstSubresource.layerCount = src_box->depth;
1351 } else {
1352 region.dstOffset.z = dstz;
1353 region.dstSubresource.layerCount = 1;
1354 }
1355
1356 region.dstOffset.x = dstx;
1357 region.dstOffset.y = dsty;
1358 region.extent.width = src_box->width;
1359 region.extent.height = src_box->height;
1360
1361 struct zink_batch *batch = zink_batch_no_rp(ctx);
1362 zink_batch_reference_resoure(batch, src);
1363 zink_batch_reference_resoure(batch, dst);
1364
1365 if (src->layout != VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL &&
1366 src->layout != VK_IMAGE_LAYOUT_GENERAL) {
1367 zink_resource_barrier(batch->cmdbuf, src, src->aspect,
1368 VK_IMAGE_LAYOUT_GENERAL);
1369 src->layout = VK_IMAGE_LAYOUT_GENERAL;
1370 }
1371
1372 if (dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1373 dst->layout != VK_IMAGE_LAYOUT_GENERAL) {
1374 zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1375 VK_IMAGE_LAYOUT_GENERAL);
1376 dst->layout = VK_IMAGE_LAYOUT_GENERAL;
1377 }
1378
1379 vkCmdCopyImage(batch->cmdbuf, src->image, src->layout,
1380 dst->image, dst->layout,
1381 1, &region);
1382 } else
1383 debug_printf("zink: TODO resource copy\n");
1384 }
1385
1386 struct pipe_context *
1387 zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
1388 {
1389 struct zink_screen *screen = zink_screen(pscreen);
1390 struct zink_context *ctx = CALLOC_STRUCT(zink_context);
1391
1392 ctx->base.screen = pscreen;
1393 ctx->base.priv = priv;
1394
1395 ctx->base.destroy = zink_context_destroy;
1396
1397 zink_context_state_init(&ctx->base);
1398
1399 ctx->base.create_sampler_state = zink_create_sampler_state;
1400 ctx->base.bind_sampler_states = zink_bind_sampler_states;
1401 ctx->base.delete_sampler_state = zink_delete_sampler_state;
1402
1403 ctx->base.create_sampler_view = zink_create_sampler_view;
1404 ctx->base.set_sampler_views = zink_set_sampler_views;
1405 ctx->base.sampler_view_destroy = zink_sampler_view_destroy;
1406
1407 ctx->base.create_vs_state = zink_create_vs_state;
1408 ctx->base.bind_vs_state = zink_bind_vs_state;
1409 ctx->base.delete_vs_state = zink_delete_vs_state;
1410
1411 ctx->base.create_fs_state = zink_create_fs_state;
1412 ctx->base.bind_fs_state = zink_bind_fs_state;
1413 ctx->base.delete_fs_state = zink_delete_fs_state;
1414
1415 ctx->base.set_polygon_stipple = zink_set_polygon_stipple;
1416 ctx->base.set_vertex_buffers = zink_set_vertex_buffers;
1417 ctx->base.set_viewport_states = zink_set_viewport_states;
1418 ctx->base.set_scissor_states = zink_set_scissor_states;
1419 ctx->base.set_constant_buffer = zink_set_constant_buffer;
1420 ctx->base.set_framebuffer_state = zink_set_framebuffer_state;
1421 ctx->base.set_stencil_ref = zink_set_stencil_ref;
1422 ctx->base.set_clip_state = zink_set_clip_state;
1423 ctx->base.set_blend_color = zink_set_blend_color;
1424
1425 ctx->base.set_sample_mask = zink_set_sample_mask;
1426
1427 ctx->base.clear = zink_clear;
1428 ctx->base.draw_vbo = zink_draw_vbo;
1429 ctx->base.flush = zink_flush;
1430
1431 ctx->base.resource_copy_region = zink_resource_copy_region;
1432 ctx->base.blit = zink_blit;
1433
1434 ctx->base.flush_resource = zink_flush_resource;
1435 zink_context_surface_init(&ctx->base);
1436 zink_context_resource_init(&ctx->base);
1437 zink_context_query_init(&ctx->base);
1438
1439 slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
1440
1441 ctx->base.stream_uploader = u_upload_create_default(&ctx->base);
1442 ctx->base.const_uploader = ctx->base.stream_uploader;
1443
1444 int prim_hwsupport = 1 << PIPE_PRIM_POINTS |
1445 1 << PIPE_PRIM_LINES |
1446 1 << PIPE_PRIM_LINE_STRIP |
1447 1 << PIPE_PRIM_TRIANGLES |
1448 1 << PIPE_PRIM_TRIANGLE_STRIP |
1449 1 << PIPE_PRIM_TRIANGLE_FAN;
1450
1451 ctx->primconvert = util_primconvert_create(&ctx->base, prim_hwsupport);
1452 if (!ctx->primconvert)
1453 goto fail;
1454
1455 ctx->blitter = util_blitter_create(&ctx->base);
1456 if (!ctx->blitter)
1457 goto fail;
1458
1459 VkCommandPoolCreateInfo cpci = {};
1460 cpci.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO;
1461 cpci.queueFamilyIndex = screen->gfx_queue;
1462 cpci.flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT;
1463 if (vkCreateCommandPool(screen->dev, &cpci, NULL, &ctx->cmdpool) != VK_SUCCESS)
1464 goto fail;
1465
1466 VkCommandBufferAllocateInfo cbai = {};
1467 cbai.sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO;
1468 cbai.commandPool = ctx->cmdpool;
1469 cbai.level = VK_COMMAND_BUFFER_LEVEL_PRIMARY;
1470 cbai.commandBufferCount = 1;
1471
1472 VkDescriptorPoolSize sizes[] = {
1473 {VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER, ZINK_BATCH_DESC_SIZE}
1474 };
1475 VkDescriptorPoolCreateInfo dpci = {};
1476 dpci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO;
1477 dpci.pPoolSizes = sizes;
1478 dpci.poolSizeCount = ARRAY_SIZE(sizes);
1479 dpci.flags = VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT;
1480 dpci.maxSets = ZINK_BATCH_DESC_SIZE;
1481
1482 for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i) {
1483 if (vkAllocateCommandBuffers(screen->dev, &cbai, &ctx->batches[i].cmdbuf) != VK_SUCCESS)
1484 goto fail;
1485
1486 ctx->batches[i].resources = _mesa_set_create(NULL, _mesa_hash_pointer,
1487 _mesa_key_pointer_equal);
1488 ctx->batches[i].sampler_views = _mesa_set_create(NULL,
1489 _mesa_hash_pointer,
1490 _mesa_key_pointer_equal);
1491
1492 if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views)
1493 goto fail;
1494
1495 util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL);
1496
1497 if (vkCreateDescriptorPool(screen->dev, &dpci, 0,
1498 &ctx->batches[i].descpool) != VK_SUCCESS)
1499 goto fail;
1500 }
1501
1502 vkGetDeviceQueue(screen->dev, screen->gfx_queue, 0, &ctx->queue);
1503
1504 ctx->program_cache = _mesa_hash_table_create(NULL,
1505 hash_gfx_program,
1506 equals_gfx_program);
1507 ctx->render_pass_cache = _mesa_hash_table_create(NULL,
1508 hash_render_pass_state,
1509 equals_render_pass_state);
1510 ctx->framebuffer_cache = _mesa_hash_table_create(NULL,
1511 hash_framebuffer_state,
1512 equals_framebuffer_state);
1513
1514 if (!ctx->program_cache || !ctx->render_pass_cache ||
1515 !ctx->framebuffer_cache)
1516 goto fail;
1517
1518 ctx->dirty = ZINK_DIRTY_PROGRAM;
1519
1520 /* start the first batch */
1521 zink_start_batch(ctx, zink_curr_batch(ctx));
1522
1523 return &ctx->base;
1524
1525 fail:
1526 if (ctx) {
1527 vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
1528 FREE(ctx);
1529 }
1530 return NULL;
1531 }