2 * Copyright 2018 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "zink_screen.h"
26 #include "zink_compiler.h"
27 #include "zink_context.h"
28 #include "zink_fence.h"
29 #include "zink_public.h"
30 #include "zink_resource.h"
32 #include "os/os_process.h"
33 #include "util/u_debug.h"
34 #include "util/u_format.h"
35 #include "util/u_math.h"
36 #include "util/u_memory.h"
37 #include "util/u_screen.h"
38 #include "util/u_string.h"
40 #include "state_tracker/sw_winsys.h"
42 static const struct debug_named_value
44 { "nir", ZINK_DEBUG_NIR
, "Dump NIR during program compile" },
45 { "spirv", ZINK_DEBUG_SPIRV
, "Dump SPIR-V during program compile" },
46 { "tgsi", ZINK_DEBUG_TGSI
, "Dump TGSI during program compile" },
50 DEBUG_GET_ONCE_FLAGS_OPTION(zink_debug
, "ZINK_DEBUG", debug_options
, 0)
56 zink_get_vendor(struct pipe_screen
*pscreen
)
58 return "Collabora Ltd";
62 zink_get_device_vendor(struct pipe_screen
*pscreen
)
64 struct zink_screen
*screen
= zink_screen(pscreen
);
65 static char buf
[1000];
66 snprintf(buf
, sizeof(buf
), "Unknown (vendor-id: 0x%04x)", screen
->props
.vendorID
);
71 zink_get_name(struct pipe_screen
*pscreen
)
73 struct zink_screen
*screen
= zink_screen(pscreen
);
74 static char buf
[1000];
75 snprintf(buf
, sizeof(buf
), "zink (%s)", screen
->props
.deviceName
);
80 get_video_mem(struct zink_screen
*screen
)
82 VkDeviceSize size
= 0;
83 for (uint32_t i
= 0; i
< screen
->mem_props
.memoryHeapCount
; ++i
)
84 size
+= screen
->mem_props
.memoryHeaps
[i
].size
;
85 return (int)(size
>> 20);
89 zink_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
91 struct zink_screen
*screen
= zink_screen(pscreen
);
94 case PIPE_CAP_NPOT_TEXTURES
:
97 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
98 return screen
->props
.limits
.maxFragmentDualSrcAttachments
;
100 case PIPE_CAP_POINT_SPRITE
:
103 case PIPE_CAP_MAX_RENDER_TARGETS
:
104 return screen
->props
.limits
.maxColorAttachments
;
106 case PIPE_CAP_OCCLUSION_QUERY
:
107 case PIPE_CAP_QUERY_TIME_ELAPSED
:
110 case PIPE_CAP_TEXTURE_SWIZZLE
:
113 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
114 return screen
->props
.limits
.maxImageDimension2D
;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
116 return 1 + util_logbase2(screen
->props
.limits
.maxImageDimension3D
);
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
118 return 1 + util_logbase2(screen
->props
.limits
.maxImageDimensionCube
);
120 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
123 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
124 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
125 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
128 case PIPE_CAP_INDEP_BLEND_ENABLE
:
129 case PIPE_CAP_INDEP_BLEND_FUNC
:
132 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
133 return screen
->props
.limits
.maxImageArrayLayers
;
135 #if 0 /* TODO: Enable me */
136 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
140 #if 0 /* TODO: Enable me */
141 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
145 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
148 case PIPE_CAP_MIN_TEXEL_OFFSET
:
149 return screen
->props
.limits
.minTexelOffset
;
150 case PIPE_CAP_MAX_TEXEL_OFFSET
:
151 return screen
->props
.limits
.maxTexelOffset
;
153 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
156 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
157 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
160 #if 0 /* TODO: Enable me */
161 case PIPE_CAP_COMPUTE
:
165 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
166 return screen
->props
.limits
.minUniformBufferOffsetAlignment
;
168 case PIPE_CAP_QUERY_TIMESTAMP
:
171 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
172 return screen
->props
.limits
.minMemoryMapAlignment
;
174 case PIPE_CAP_CUBE_MAP_ARRAY
:
175 return screen
->feats
.imageCubeArray
;
177 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
178 return 0; /* unsure */
180 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
181 return screen
->props
.limits
.maxTexelBufferElements
;
183 case PIPE_CAP_ENDIANNESS
:
184 return PIPE_ENDIAN_NATIVE
; /* unsure */
186 case PIPE_CAP_MAX_VIEWPORTS
:
187 return screen
->props
.limits
.maxViewports
;
189 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
192 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
193 return screen
->props
.limits
.maxGeometryOutputVertices
;
194 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
195 return screen
->props
.limits
.maxGeometryOutputComponents
;
197 #if 0 /* TODO: Enable me. Enables ARB_texture_gather */
198 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
202 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
203 return screen
->props
.limits
.minTexelGatherOffset
;
204 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
205 return screen
->props
.limits
.maxTexelGatherOffset
;
207 case PIPE_CAP_VENDOR_ID
:
208 return screen
->props
.vendorID
;
209 case PIPE_CAP_DEVICE_ID
:
210 return screen
->props
.deviceID
;
212 case PIPE_CAP_ACCELERATED
:
214 case PIPE_CAP_VIDEO_MEMORY
:
215 return get_video_mem(screen
);
217 return screen
->props
.deviceType
== VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
;
219 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
220 return screen
->props
.limits
.maxVertexInputBindingStride
;
222 #if 0 /* TODO: Enable me */
223 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
227 #if 0 /* TODO: Enable me */
228 case PIPE_CAP_CLIP_HALFZ
:
232 #if 0 /* TODO: Enable me */
233 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
234 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
238 case PIPE_CAP_SHAREABLE_SHADERS
:
241 #if 0 /* TODO: Enable me. Enables GL_ARB_shader_storage_buffer_object */
242 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
243 return screen
->props
.limits
.minStorageBufferOffsetAlignment
;
246 case PIPE_CAP_PCI_GROUP
:
247 case PIPE_CAP_PCI_BUS
:
248 case PIPE_CAP_PCI_DEVICE
:
249 case PIPE_CAP_PCI_FUNCTION
:
250 return 0; /* TODO: figure these out */
252 #if 0 /* TODO: Enable me */
253 case PIPE_CAP_CULL_DISTANCE
:
254 return screen
->feats
.shaderCullDistance
;
257 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
258 return screen
->props
.limits
.viewportSubPixelBits
;
260 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
261 return 0; /* not sure */
263 case PIPE_CAP_MAX_GS_INVOCATIONS
:
264 return 0; /* not implemented */
266 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
267 return screen
->props
.limits
.maxDescriptorSetStorageBuffers
;
269 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
270 return screen
->props
.limits
.maxStorageBufferRange
; /* unsure */
272 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
273 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
277 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
280 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
283 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
286 case PIPE_CAP_FLATSHADE
:
287 case PIPE_CAP_ALPHA_TEST
:
288 case PIPE_CAP_CLIP_PLANES
:
292 return u_pipe_screen_get_param_defaults(pscreen
, param
);
297 zink_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
299 struct zink_screen
*screen
= zink_screen(pscreen
);
302 case PIPE_CAPF_MAX_LINE_WIDTH
:
303 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
304 return screen
->props
.limits
.lineWidthRange
[1];
306 case PIPE_CAPF_MAX_POINT_WIDTH
:
307 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
308 return screen
->props
.limits
.pointSizeRange
[1];
310 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
311 return screen
->props
.limits
.maxSamplerAnisotropy
;
313 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
314 return screen
->props
.limits
.maxSamplerLodBias
;
316 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
317 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
318 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
319 return 0.0f
; /* not implemented */
322 /* should only get here on unhandled cases */
327 zink_get_shader_param(struct pipe_screen
*pscreen
,
328 enum pipe_shader_type shader
,
329 enum pipe_shader_cap param
)
331 struct zink_screen
*screen
= zink_screen(pscreen
);
334 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
335 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
336 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
337 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
338 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
339 if (shader
== PIPE_SHADER_VERTEX
||
340 shader
== PIPE_SHADER_FRAGMENT
)
344 case PIPE_SHADER_CAP_MAX_INPUTS
:
346 case PIPE_SHADER_VERTEX
:
347 return MIN2(screen
->props
.limits
.maxVertexInputAttributes
,
348 PIPE_MAX_SHADER_INPUTS
);
349 case PIPE_SHADER_FRAGMENT
:
350 return MIN2(screen
->props
.limits
.maxFragmentInputComponents
/ 4,
351 PIPE_MAX_SHADER_INPUTS
);
353 return 0; /* unsupported stage */
356 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
358 case PIPE_SHADER_VERTEX
:
359 return MIN2(screen
->props
.limits
.maxVertexOutputComponents
/ 4,
360 PIPE_MAX_SHADER_OUTPUTS
);
361 case PIPE_SHADER_FRAGMENT
:
362 return MIN2(screen
->props
.limits
.maxColorAttachments
,
363 PIPE_MAX_SHADER_OUTPUTS
);
365 return 0; /* unsupported stage */
368 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
369 /* this might be a bit simplistic... */
370 return MIN2(screen
->props
.limits
.maxPerStageDescriptorSamplers
,
373 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
374 return MIN2(screen
->props
.limits
.maxUniformBufferRange
, INT_MAX
);
376 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
377 return screen
->props
.limits
.maxPerStageDescriptorUniformBuffers
;
379 case PIPE_SHADER_CAP_MAX_TEMPS
:
382 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
383 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
384 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
385 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
386 case PIPE_SHADER_CAP_SUBROUTINES
:
387 case PIPE_SHADER_CAP_INTEGERS
:
388 case PIPE_SHADER_CAP_INT64_ATOMICS
:
389 case PIPE_SHADER_CAP_FP16
:
390 return 0; /* not implemented */
392 case PIPE_SHADER_CAP_PREFERRED_IR
:
393 return PIPE_SHADER_IR_NIR
;
395 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
396 return 0; /* not implemented */
398 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
399 return MIN2(screen
->props
.limits
.maxPerStageDescriptorSampledImages
,
400 PIPE_MAX_SHADER_SAMPLER_VIEWS
);
402 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
403 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
404 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
405 return 0; /* not implemented */
407 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
408 return 0; /* no idea */
410 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
411 return 32; /* arbitrary */
413 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
414 /* TODO: this limitation is dumb, and will need some fixes in mesa */
415 return MIN2(screen
->props
.limits
.maxPerStageDescriptorStorageBuffers
, 8);
417 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
418 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
420 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
421 return MIN2(screen
->props
.limits
.maxPerStageDescriptorStorageImages
,
422 PIPE_MAX_SHADER_IMAGES
);
424 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
425 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
426 return 0; /* unsure */
428 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
429 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
430 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
431 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
432 return 0; /* not implemented */
435 /* should only get here on unhandled cases */
439 static const VkFormat formats
[PIPE_FORMAT_COUNT
] = {
440 #define MAP_FORMAT_NORM(FMT) \
441 [PIPE_FORMAT_ ## FMT ## _UNORM] = VK_FORMAT_ ## FMT ## _UNORM, \
442 [PIPE_FORMAT_ ## FMT ## _SNORM] = VK_FORMAT_ ## FMT ## _SNORM,
444 #define MAP_FORMAT_SCALED(FMT) \
445 [PIPE_FORMAT_ ## FMT ## _USCALED] = VK_FORMAT_ ## FMT ## _USCALED, \
446 [PIPE_FORMAT_ ## FMT ## _SSCALED] = VK_FORMAT_ ## FMT ## _SSCALED,
448 #define MAP_FORMAT_INT(FMT) \
449 [PIPE_FORMAT_ ## FMT ## _UINT] = VK_FORMAT_ ## FMT ## _UINT, \
450 [PIPE_FORMAT_ ## FMT ## _SINT] = VK_FORMAT_ ## FMT ## _SINT,
452 #define MAP_FORMAT_SRGB(FMT) \
453 [PIPE_FORMAT_ ## FMT ## _SRGB] = VK_FORMAT_ ## FMT ## _SRGB,
455 #define MAP_FORMAT_FLOAT(FMT) \
456 [PIPE_FORMAT_ ## FMT ## _FLOAT] = VK_FORMAT_ ## FMT ## _SFLOAT,
462 MAP_FORMAT_SCALED(R8
)
466 MAP_FORMAT_SCALED(R16
)
468 MAP_FORMAT_FLOAT(R16
)
471 MAP_FORMAT_FLOAT(R32
)
476 MAP_FORMAT_NORM(R8G8
)
477 MAP_FORMAT_SCALED(R8G8
)
480 MAP_FORMAT_NORM(R16G16
)
481 MAP_FORMAT_SCALED(R16G16
)
482 MAP_FORMAT_INT(R16G16
)
483 MAP_FORMAT_FLOAT(R16G16
)
485 MAP_FORMAT_INT(R32G32
)
486 MAP_FORMAT_FLOAT(R32G32
)
491 MAP_FORMAT_NORM(R8G8B8
)
492 MAP_FORMAT_SCALED(R8G8B8
)
493 MAP_FORMAT_INT(R8G8B8
)
494 MAP_FORMAT_SRGB(R8G8B8
)
496 MAP_FORMAT_NORM(R16G16B16
)
497 MAP_FORMAT_SCALED(R16G16B16
)
498 MAP_FORMAT_INT(R16G16B16
)
499 MAP_FORMAT_FLOAT(R16G16B16
)
501 MAP_FORMAT_INT(R32G32B32
)
502 MAP_FORMAT_FLOAT(R32G32B32
)
507 MAP_FORMAT_NORM(R8G8B8A8
)
508 MAP_FORMAT_SCALED(R8G8B8A8
)
509 MAP_FORMAT_INT(R8G8B8A8
)
510 MAP_FORMAT_SRGB(R8G8B8A8
)
511 [PIPE_FORMAT_B8G8R8A8_UNORM
] = VK_FORMAT_B8G8R8A8_UNORM
,
512 MAP_FORMAT_SRGB(B8G8R8A8
)
513 [PIPE_FORMAT_A8B8G8R8_SRGB
] = VK_FORMAT_A8B8G8R8_SRGB_PACK32
,
515 MAP_FORMAT_NORM(R16G16B16A16
)
516 MAP_FORMAT_SCALED(R16G16B16A16
)
517 MAP_FORMAT_INT(R16G16B16A16
)
518 MAP_FORMAT_FLOAT(R16G16B16A16
)
520 MAP_FORMAT_INT(R32G32B32A32
)
521 MAP_FORMAT_FLOAT(R32G32B32A32
)
523 // other color formats
524 [PIPE_FORMAT_B5G6R5_UNORM
] = VK_FORMAT_R5G6B5_UNORM_PACK16
,
525 [PIPE_FORMAT_B5G5R5A1_UNORM
] = VK_FORMAT_B5G5R5A1_UNORM_PACK16
,
526 [PIPE_FORMAT_R11G11B10_FLOAT
] = VK_FORMAT_B10G11R11_UFLOAT_PACK32
,
527 [PIPE_FORMAT_R9G9B9E5_FLOAT
] = VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
,
528 [PIPE_FORMAT_R10G10B10A2_UNORM
] = VK_FORMAT_A2B10G10R10_UNORM_PACK32
,
529 [PIPE_FORMAT_B10G10R10A2_UNORM
] = VK_FORMAT_A2R10G10B10_UNORM_PACK32
,
530 [PIPE_FORMAT_R10G10B10A2_UINT
] = VK_FORMAT_A2B10G10R10_UINT_PACK32
,
531 [PIPE_FORMAT_B10G10R10A2_UINT
] = VK_FORMAT_A2R10G10B10_UINT_PACK32
,
533 // depth/stencil formats
534 [PIPE_FORMAT_Z32_FLOAT
] = VK_FORMAT_D32_SFLOAT
,
535 [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
] = VK_FORMAT_D32_SFLOAT_S8_UINT
,
536 [PIPE_FORMAT_Z16_UNORM
] = VK_FORMAT_D16_UNORM
,
537 [PIPE_FORMAT_X8Z24_UNORM
] = VK_FORMAT_X8_D24_UNORM_PACK32
,
538 [PIPE_FORMAT_Z24_UNORM_S8_UINT
] = VK_FORMAT_D24_UNORM_S8_UINT
,
540 // compressed formats
541 [PIPE_FORMAT_DXT1_RGB
] = VK_FORMAT_BC1_RGB_UNORM_BLOCK
,
542 [PIPE_FORMAT_DXT1_RGBA
] = VK_FORMAT_BC1_RGBA_UNORM_BLOCK
,
543 [PIPE_FORMAT_DXT3_RGBA
] = VK_FORMAT_BC2_UNORM_BLOCK
,
544 [PIPE_FORMAT_DXT5_RGBA
] = VK_FORMAT_BC3_UNORM_BLOCK
,
545 [PIPE_FORMAT_RGTC1_UNORM
] = VK_FORMAT_BC4_UNORM_BLOCK
,
546 [PIPE_FORMAT_RGTC1_SNORM
] = VK_FORMAT_BC4_SNORM_BLOCK
,
547 [PIPE_FORMAT_RGTC2_UNORM
] = VK_FORMAT_BC5_UNORM_BLOCK
,
548 [PIPE_FORMAT_RGTC2_SNORM
] = VK_FORMAT_BC5_SNORM_BLOCK
,
549 [PIPE_FORMAT_BPTC_RGBA_UNORM
] = VK_FORMAT_BC7_UNORM_BLOCK
,
550 [PIPE_FORMAT_BPTC_SRGBA
] = VK_FORMAT_BC7_SRGB_BLOCK
,
551 [PIPE_FORMAT_BPTC_RGB_FLOAT
] = VK_FORMAT_BC6H_SFLOAT_BLOCK
,
552 [PIPE_FORMAT_BPTC_RGB_UFLOAT
] = VK_FORMAT_BC6H_UFLOAT_BLOCK
,
556 zink_get_format(enum pipe_format format
)
558 return formats
[format
];
561 static VkSampleCountFlagBits
562 vk_sample_count_flags(uint32_t sample_count
)
564 switch (sample_count
) {
565 case 1: return VK_SAMPLE_COUNT_1_BIT
;
566 case 2: return VK_SAMPLE_COUNT_2_BIT
;
567 case 4: return VK_SAMPLE_COUNT_4_BIT
;
568 case 8: return VK_SAMPLE_COUNT_8_BIT
;
569 case 16: return VK_SAMPLE_COUNT_16_BIT
;
570 case 32: return VK_SAMPLE_COUNT_32_BIT
;
571 case 64: return VK_SAMPLE_COUNT_64_BIT
;
578 zink_is_format_supported(struct pipe_screen
*pscreen
,
579 enum pipe_format format
,
580 enum pipe_texture_target target
,
581 unsigned sample_count
,
582 unsigned storage_sample_count
,
585 struct zink_screen
*screen
= zink_screen(pscreen
);
587 if (format
== PIPE_FORMAT_NONE
)
588 return screen
->props
.limits
.framebufferNoAttachmentsSampleCounts
&
589 vk_sample_count_flags(sample_count
);
591 VkFormat vkformat
= formats
[format
];
592 if (vkformat
== VK_FORMAT_UNDEFINED
)
595 if (sample_count
>= 1) {
596 VkSampleCountFlagBits sample_mask
= vk_sample_count_flags(sample_count
);
597 const struct util_format_description
*desc
= util_format_description(format
);
598 if (util_format_is_depth_or_stencil(format
)) {
599 if (util_format_has_depth(desc
)) {
600 if (bind
& PIPE_BIND_DEPTH_STENCIL
&&
601 (screen
->props
.limits
.framebufferDepthSampleCounts
& sample_mask
) != sample_mask
)
603 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
604 (screen
->props
.limits
.sampledImageDepthSampleCounts
& sample_mask
) != sample_mask
)
607 if (util_format_has_stencil(desc
)) {
608 if (bind
& PIPE_BIND_DEPTH_STENCIL
&&
609 (screen
->props
.limits
.framebufferStencilSampleCounts
& sample_mask
) != sample_mask
)
611 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
612 (screen
->props
.limits
.sampledImageStencilSampleCounts
& sample_mask
) != sample_mask
)
615 } else if (util_format_is_pure_integer(format
)) {
616 if (bind
& PIPE_BIND_RENDER_TARGET
&&
617 !(screen
->props
.limits
.framebufferColorSampleCounts
& sample_mask
))
619 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
620 !(screen
->props
.limits
.sampledImageIntegerSampleCounts
& sample_mask
))
623 if (bind
& PIPE_BIND_RENDER_TARGET
&&
624 !(screen
->props
.limits
.framebufferColorSampleCounts
& sample_mask
))
626 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
627 !(screen
->props
.limits
.sampledImageColorSampleCounts
& sample_mask
))
632 VkFormatProperties props
;
633 vkGetPhysicalDeviceFormatProperties(screen
->pdev
, vkformat
, &props
);
635 if (target
== PIPE_BUFFER
) {
636 if (bind
& PIPE_BIND_VERTEX_BUFFER
&&
637 !(props
.bufferFeatures
& VK_FORMAT_FEATURE_VERTEX_BUFFER_BIT
))
640 /* all other targets are texture-targets */
641 if (bind
& PIPE_BIND_RENDER_TARGET
&&
642 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT
))
645 if (bind
& PIPE_BIND_BLENDABLE
&&
646 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT
))
649 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
650 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT
))
653 if (bind
& PIPE_BIND_DEPTH_STENCIL
&&
654 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT
))
658 if (util_format_is_compressed(format
)) {
659 const struct util_format_description
*desc
= util_format_description(format
);
660 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
&&
661 !screen
->feats
.textureCompressionBC
)
669 zink_destroy_screen(struct pipe_screen
*pscreen
)
671 struct zink_screen
*screen
= zink_screen(pscreen
);
672 slab_destroy_parent(&screen
->transfer_pool
);
679 VkApplicationInfo ai
= {};
680 ai
.sType
= VK_STRUCTURE_TYPE_APPLICATION_INFO
;
683 if (os_get_process_name(proc_name
, ARRAY_SIZE(proc_name
)))
684 ai
.pApplicationName
= proc_name
;
686 ai
.pApplicationName
= "unknown";
688 ai
.pEngineName
= "mesa zink";
689 ai
.apiVersion
= VK_API_VERSION_1_0
;
691 const char *extensions
[] = {
692 VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
693 VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
696 VkInstanceCreateInfo ici
= {};
697 ici
.sType
= VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
;
698 ici
.pApplicationInfo
= &ai
;
699 ici
.ppEnabledExtensionNames
= extensions
;
700 ici
.enabledExtensionCount
= ARRAY_SIZE(extensions
);
702 VkInstance instance
= VK_NULL_HANDLE
;
703 VkResult err
= vkCreateInstance(&ici
, NULL
, &instance
);
704 if (err
!= VK_SUCCESS
)
705 return VK_NULL_HANDLE
;
710 static VkPhysicalDevice
711 choose_pdev(const VkInstance instance
)
713 uint32_t i
, pdev_count
;
714 VkPhysicalDevice
*pdevs
, pdev
;
715 vkEnumeratePhysicalDevices(instance
, &pdev_count
, NULL
);
716 assert(pdev_count
> 0);
718 pdevs
= malloc(sizeof(*pdevs
) * pdev_count
);
719 vkEnumeratePhysicalDevices(instance
, &pdev_count
, pdevs
);
720 assert(pdev_count
> 0);
723 for (i
= 0; i
< pdev_count
; ++i
) {
724 VkPhysicalDeviceProperties props
;
725 vkGetPhysicalDeviceProperties(pdevs
[i
], &props
);
726 if (props
.deviceType
== VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
) {
736 find_gfx_queue(const VkPhysicalDevice pdev
)
739 vkGetPhysicalDeviceQueueFamilyProperties(pdev
, &num_queues
, NULL
);
740 assert(num_queues
> 0);
742 VkQueueFamilyProperties
*props
= malloc(sizeof(*props
) * num_queues
);
743 vkGetPhysicalDeviceQueueFamilyProperties(pdev
, &num_queues
, props
);
745 for (uint32_t i
= 0; i
< num_queues
; i
++) {
746 if (props
[i
].queueFlags
& VK_QUEUE_GRAPHICS_BIT
) {
756 zink_flush_frontbuffer(struct pipe_screen
*pscreen
,
757 struct pipe_resource
*pres
,
758 unsigned level
, unsigned layer
,
759 void *winsys_drawable_handle
,
760 struct pipe_box
*sub_box
)
762 struct zink_screen
*screen
= zink_screen(pscreen
);
763 struct sw_winsys
*winsys
= screen
->winsys
;
764 struct zink_resource
*res
= zink_resource(pres
);
768 void *map
= winsys
->displaytarget_map(winsys
, res
->dt
, 0);
771 VkImageSubresource isr
= {};
772 isr
.aspectMask
= res
->aspect
;
773 isr
.mipLevel
= level
;
774 isr
.arrayLayer
= layer
;
775 VkSubresourceLayout layout
;
776 vkGetImageSubresourceLayout(screen
->dev
, res
->image
, &isr
, &layout
);
779 VkResult result
= vkMapMemory(screen
->dev
, res
->mem
, res
->offset
, res
->size
, 0, &ptr
);
780 if (result
!= VK_SUCCESS
) {
781 debug_printf("failed to map memory for display\n");
784 for (int i
= 0; i
< pres
->height0
; ++i
) {
785 uint8_t *src
= (uint8_t *)ptr
+ i
* layout
.rowPitch
;
786 uint8_t *dst
= (uint8_t *)map
+ i
* res
->dt_stride
;
787 memcpy(dst
, src
, res
->dt_stride
);
789 vkUnmapMemory(screen
->dev
, res
->mem
);
792 winsys
->displaytarget_unmap(winsys
, res
->dt
);
796 winsys
->displaytarget_display(winsys
, res
->dt
, winsys_drawable_handle
, sub_box
);
799 static struct pipe_screen
*
800 zink_internal_create_screen(struct sw_winsys
*winsys
, int fd
)
802 struct zink_screen
*screen
= CALLOC_STRUCT(zink_screen
);
806 zink_debug
= debug_get_option_zink_debug();
808 screen
->instance
= create_instance();
809 screen
->pdev
= choose_pdev(screen
->instance
);
810 screen
->gfx_queue
= find_gfx_queue(screen
->pdev
);
812 vkGetPhysicalDeviceProperties(screen
->pdev
, &screen
->props
);
813 vkGetPhysicalDeviceFeatures(screen
->pdev
, &screen
->feats
);
814 vkGetPhysicalDeviceMemoryProperties(screen
->pdev
, &screen
->mem_props
);
816 uint32_t num_extensions
= 0;
817 if (vkEnumerateDeviceExtensionProperties(screen
->pdev
, NULL
,
818 &num_extensions
, NULL
) == VK_SUCCESS
&& num_extensions
> 0) {
819 VkExtensionProperties
*extensions
= MALLOC(sizeof(VkExtensionProperties
) *
822 vkEnumerateDeviceExtensionProperties(screen
->pdev
, NULL
,
823 &num_extensions
, extensions
);
825 for (uint32_t i
= 0; i
< num_extensions
; ++i
) {
826 if (!strcmp(extensions
[i
].extensionName
,
827 VK_KHR_MAINTENANCE1_EXTENSION_NAME
))
828 screen
->have_VK_KHR_maintenance1
= true;
834 VkDeviceQueueCreateInfo qci
= {};
836 qci
.sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO
;
837 qci
.queueFamilyIndex
= screen
->gfx_queue
;
839 qci
.pQueuePriorities
= &dummy
;
841 VkDeviceCreateInfo dci
= {};
842 dci
.sType
= VK_STRUCTURE_TYPE_DEVICE_CREATE_INFO
;
843 dci
.queueCreateInfoCount
= 1;
844 dci
.pQueueCreateInfos
= &qci
;
845 dci
.pEnabledFeatures
= &screen
->feats
;
846 const char *extensions
[] = {
847 VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
848 VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME
,
849 VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
851 dci
.ppEnabledExtensionNames
= extensions
;
852 dci
.enabledExtensionCount
= ARRAY_SIZE(extensions
);
853 if (vkCreateDevice(screen
->pdev
, &dci
, NULL
, &screen
->dev
) != VK_SUCCESS
)
856 screen
->winsys
= winsys
;
858 screen
->base
.get_name
= zink_get_name
;
859 screen
->base
.get_vendor
= zink_get_vendor
;
860 screen
->base
.get_device_vendor
= zink_get_device_vendor
;
861 screen
->base
.get_param
= zink_get_param
;
862 screen
->base
.get_paramf
= zink_get_paramf
;
863 screen
->base
.get_shader_param
= zink_get_shader_param
;
864 screen
->base
.get_compiler_options
= zink_get_compiler_options
;
865 screen
->base
.is_format_supported
= zink_is_format_supported
;
866 screen
->base
.context_create
= zink_context_create
;
867 screen
->base
.flush_frontbuffer
= zink_flush_frontbuffer
;
868 screen
->base
.destroy
= zink_destroy_screen
;
870 zink_screen_resource_init(&screen
->base
);
871 zink_screen_fence_init(&screen
->base
);
873 slab_create_parent(&screen
->transfer_pool
, sizeof(struct zink_transfer
), 16);
875 return &screen
->base
;
883 zink_create_screen(struct sw_winsys
*winsys
)
885 return zink_internal_create_screen(winsys
, -1);
889 zink_drm_create_screen(int fd
)
891 return zink_internal_create_screen(NULL
, fd
);