gallium: add interface and state tracker support for GL_AMD_pinned_memory
[mesa.git] / src / gallium / include / pipe / p_defines.h
1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
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27
28 #ifndef PIPE_DEFINES_H
29 #define PIPE_DEFINES_H
30
31 #include "p_compiler.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /**
38 * Gallium error codes.
39 *
40 * - A zero value always means success.
41 * - A negative value always means failure.
42 * - The meaning of a positive value is function dependent.
43 */
44 enum pipe_error {
45 PIPE_OK = 0,
46 PIPE_ERROR = -1, /**< Generic error */
47 PIPE_ERROR_BAD_INPUT = -2,
48 PIPE_ERROR_OUT_OF_MEMORY = -3,
49 PIPE_ERROR_RETRY = -4
50 /* TODO */
51 };
52
53
54 #define PIPE_BLENDFACTOR_ONE 0x1
55 #define PIPE_BLENDFACTOR_SRC_COLOR 0x2
56 #define PIPE_BLENDFACTOR_SRC_ALPHA 0x3
57 #define PIPE_BLENDFACTOR_DST_ALPHA 0x4
58 #define PIPE_BLENDFACTOR_DST_COLOR 0x5
59 #define PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
60 #define PIPE_BLENDFACTOR_CONST_COLOR 0x7
61 #define PIPE_BLENDFACTOR_CONST_ALPHA 0x8
62 #define PIPE_BLENDFACTOR_SRC1_COLOR 0x9
63 #define PIPE_BLENDFACTOR_SRC1_ALPHA 0x0A
64 #define PIPE_BLENDFACTOR_ZERO 0x11
65 #define PIPE_BLENDFACTOR_INV_SRC_COLOR 0x12
66 #define PIPE_BLENDFACTOR_INV_SRC_ALPHA 0x13
67 #define PIPE_BLENDFACTOR_INV_DST_ALPHA 0x14
68 #define PIPE_BLENDFACTOR_INV_DST_COLOR 0x15
69 #define PIPE_BLENDFACTOR_INV_CONST_COLOR 0x17
70 #define PIPE_BLENDFACTOR_INV_CONST_ALPHA 0x18
71 #define PIPE_BLENDFACTOR_INV_SRC1_COLOR 0x19
72 #define PIPE_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
73
74 #define PIPE_BLEND_ADD 0
75 #define PIPE_BLEND_SUBTRACT 1
76 #define PIPE_BLEND_REVERSE_SUBTRACT 2
77 #define PIPE_BLEND_MIN 3
78 #define PIPE_BLEND_MAX 4
79
80 #define PIPE_LOGICOP_CLEAR 0
81 #define PIPE_LOGICOP_NOR 1
82 #define PIPE_LOGICOP_AND_INVERTED 2
83 #define PIPE_LOGICOP_COPY_INVERTED 3
84 #define PIPE_LOGICOP_AND_REVERSE 4
85 #define PIPE_LOGICOP_INVERT 5
86 #define PIPE_LOGICOP_XOR 6
87 #define PIPE_LOGICOP_NAND 7
88 #define PIPE_LOGICOP_AND 8
89 #define PIPE_LOGICOP_EQUIV 9
90 #define PIPE_LOGICOP_NOOP 10
91 #define PIPE_LOGICOP_OR_INVERTED 11
92 #define PIPE_LOGICOP_COPY 12
93 #define PIPE_LOGICOP_OR_REVERSE 13
94 #define PIPE_LOGICOP_OR 14
95 #define PIPE_LOGICOP_SET 15
96
97 #define PIPE_MASK_R 0x1
98 #define PIPE_MASK_G 0x2
99 #define PIPE_MASK_B 0x4
100 #define PIPE_MASK_A 0x8
101 #define PIPE_MASK_RGBA 0xf
102 #define PIPE_MASK_Z 0x10
103 #define PIPE_MASK_S 0x20
104 #define PIPE_MASK_ZS 0x30
105 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
106
107
108 /**
109 * Inequality functions. Used for depth test, stencil compare, alpha
110 * test, shadow compare, etc.
111 */
112 #define PIPE_FUNC_NEVER 0
113 #define PIPE_FUNC_LESS 1
114 #define PIPE_FUNC_EQUAL 2
115 #define PIPE_FUNC_LEQUAL 3
116 #define PIPE_FUNC_GREATER 4
117 #define PIPE_FUNC_NOTEQUAL 5
118 #define PIPE_FUNC_GEQUAL 6
119 #define PIPE_FUNC_ALWAYS 7
120
121 /** Polygon fill mode */
122 #define PIPE_POLYGON_MODE_FILL 0
123 #define PIPE_POLYGON_MODE_LINE 1
124 #define PIPE_POLYGON_MODE_POINT 2
125
126 /** Polygon face specification, eg for culling */
127 #define PIPE_FACE_NONE 0
128 #define PIPE_FACE_FRONT 1
129 #define PIPE_FACE_BACK 2
130 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
131
132 /** Stencil ops */
133 #define PIPE_STENCIL_OP_KEEP 0
134 #define PIPE_STENCIL_OP_ZERO 1
135 #define PIPE_STENCIL_OP_REPLACE 2
136 #define PIPE_STENCIL_OP_INCR 3
137 #define PIPE_STENCIL_OP_DECR 4
138 #define PIPE_STENCIL_OP_INCR_WRAP 5
139 #define PIPE_STENCIL_OP_DECR_WRAP 6
140 #define PIPE_STENCIL_OP_INVERT 7
141
142 /** Texture types.
143 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D */
144 enum pipe_texture_target {
145 PIPE_BUFFER = 0,
146 PIPE_TEXTURE_1D = 1,
147 PIPE_TEXTURE_2D = 2,
148 PIPE_TEXTURE_3D = 3,
149 PIPE_TEXTURE_CUBE = 4,
150 PIPE_TEXTURE_RECT = 5,
151 PIPE_TEXTURE_1D_ARRAY = 6,
152 PIPE_TEXTURE_2D_ARRAY = 7,
153 PIPE_TEXTURE_CUBE_ARRAY = 8,
154 PIPE_MAX_TEXTURE_TYPES
155 };
156
157 #define PIPE_TEX_FACE_POS_X 0
158 #define PIPE_TEX_FACE_NEG_X 1
159 #define PIPE_TEX_FACE_POS_Y 2
160 #define PIPE_TEX_FACE_NEG_Y 3
161 #define PIPE_TEX_FACE_POS_Z 4
162 #define PIPE_TEX_FACE_NEG_Z 5
163 #define PIPE_TEX_FACE_MAX 6
164
165 #define PIPE_TEX_WRAP_REPEAT 0
166 #define PIPE_TEX_WRAP_CLAMP 1
167 #define PIPE_TEX_WRAP_CLAMP_TO_EDGE 2
168 #define PIPE_TEX_WRAP_CLAMP_TO_BORDER 3
169 #define PIPE_TEX_WRAP_MIRROR_REPEAT 4
170 #define PIPE_TEX_WRAP_MIRROR_CLAMP 5
171 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE 6
172 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER 7
173
174 /* Between mipmaps, ie mipfilter
175 */
176 #define PIPE_TEX_MIPFILTER_NEAREST 0
177 #define PIPE_TEX_MIPFILTER_LINEAR 1
178 #define PIPE_TEX_MIPFILTER_NONE 2
179
180 /* Within a mipmap, ie min/mag filter
181 */
182 #define PIPE_TEX_FILTER_NEAREST 0
183 #define PIPE_TEX_FILTER_LINEAR 1
184
185 #define PIPE_TEX_COMPARE_NONE 0
186 #define PIPE_TEX_COMPARE_R_TO_TEXTURE 1
187
188 /**
189 * Clear buffer bits
190 */
191 #define PIPE_CLEAR_DEPTH (1 << 0)
192 #define PIPE_CLEAR_STENCIL (1 << 1)
193 #define PIPE_CLEAR_COLOR0 (1 << 2)
194 #define PIPE_CLEAR_COLOR1 (1 << 3)
195 #define PIPE_CLEAR_COLOR2 (1 << 4)
196 #define PIPE_CLEAR_COLOR3 (1 << 5)
197 #define PIPE_CLEAR_COLOR4 (1 << 6)
198 #define PIPE_CLEAR_COLOR5 (1 << 7)
199 #define PIPE_CLEAR_COLOR6 (1 << 8)
200 #define PIPE_CLEAR_COLOR7 (1 << 9)
201 /** Combined flags */
202 /** All color buffers currently bound */
203 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
204 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
205 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
206 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
207 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
208
209 /**
210 * Transfer object usage flags
211 */
212 enum pipe_transfer_usage {
213 /**
214 * Resource contents read back (or accessed directly) at transfer
215 * create time.
216 */
217 PIPE_TRANSFER_READ = (1 << 0),
218
219 /**
220 * Resource contents will be written back at transfer_unmap
221 * time (or modified as a result of being accessed directly).
222 */
223 PIPE_TRANSFER_WRITE = (1 << 1),
224
225 /**
226 * Read/modify/write
227 */
228 PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
229
230 /**
231 * The transfer should map the texture storage directly. The driver may
232 * return NULL if that isn't possible, and the state tracker needs to cope
233 * with that and use an alternative path without this flag.
234 *
235 * E.g. the state tracker could have a simpler path which maps textures and
236 * does read/modify/write cycles on them directly, and a more complicated
237 * path which uses minimal read and write transfers.
238 */
239 PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
240
241 /**
242 * Discards the memory within the mapped region.
243 *
244 * It should not be used with PIPE_TRANSFER_READ.
245 *
246 * See also:
247 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
248 */
249 PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
250
251 /**
252 * Fail if the resource cannot be mapped immediately.
253 *
254 * See also:
255 * - Direct3D's D3DLOCK_DONOTWAIT flag.
256 * - Mesa3D's MESA_MAP_NOWAIT_BIT flag.
257 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
258 */
259 PIPE_TRANSFER_DONTBLOCK = (1 << 9),
260
261 /**
262 * Do not attempt to synchronize pending operations on the resource when mapping.
263 *
264 * It should not be used with PIPE_TRANSFER_READ.
265 *
266 * See also:
267 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
268 * - Direct3D's D3DLOCK_NOOVERWRITE flag.
269 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
270 */
271 PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
272
273 /**
274 * Written ranges will be notified later with
275 * pipe_context::transfer_flush_region.
276 *
277 * It should not be used with PIPE_TRANSFER_READ.
278 *
279 * See also:
280 * - pipe_context::transfer_flush_region
281 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
282 */
283 PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
284
285 /**
286 * Discards all memory backing the resource.
287 *
288 * It should not be used with PIPE_TRANSFER_READ.
289 *
290 * This is equivalent to:
291 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
292 * - BufferData(NULL) on a GL buffer
293 * - Direct3D's D3DLOCK_DISCARD flag.
294 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
295 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
296 * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
297 */
298 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
299
300 /**
301 * Allows the resource to be used for rendering while mapped.
302 *
303 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
304 * the resource.
305 *
306 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
307 * must be called to ensure the device can see what the CPU has written.
308 */
309 PIPE_TRANSFER_PERSISTENT = (1 << 13),
310
311 /**
312 * If PERSISTENT is set, this ensures any writes done by the device are
313 * immediately visible to the CPU and vice versa.
314 *
315 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
316 * the resource.
317 */
318 PIPE_TRANSFER_COHERENT = (1 << 14)
319 };
320
321 /**
322 * Flags for the flush function.
323 */
324 enum pipe_flush_flags {
325 PIPE_FLUSH_END_OF_FRAME = (1 << 0)
326 };
327
328 /**
329 * Flags for pipe_context::memory_barrier.
330 */
331 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0)
332
333 /*
334 * Resource binding flags -- state tracker must specify in advance all
335 * the ways a resource might be used.
336 */
337 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */
338 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */
339 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */
340 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */
341 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */
342 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */
343 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */
344 #define PIPE_BIND_DISPLAY_TARGET (1 << 8) /* flush_front_buffer */
345 #define PIPE_BIND_TRANSFER_WRITE (1 << 9) /* transfer_map */
346 #define PIPE_BIND_TRANSFER_READ (1 << 10) /* transfer_map */
347 #define PIPE_BIND_STREAM_OUTPUT (1 << 11) /* set_stream_output_buffers */
348 #define PIPE_BIND_CURSOR (1 << 16) /* mouse cursor */
349 #define PIPE_BIND_CUSTOM (1 << 17) /* state-tracker/winsys usages */
350 #define PIPE_BIND_GLOBAL (1 << 18) /* set_global_binding */
351 #define PIPE_BIND_SHADER_RESOURCE (1 << 19) /* set_shader_resources */
352 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 20) /* set_compute_resources */
353 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 21) /* pipe_draw_info.indirect */
354
355 /* The first two flags above were previously part of the amorphous
356 * TEXTURE_USAGE, most of which are now descriptions of the ways a
357 * particular texture can be bound to the gallium pipeline. The two flags
358 * below do not fit within that and probably need to be migrated to some
359 * other place.
360 *
361 * It seems like scanout is used by the Xorg state tracker to ask for
362 * a texture suitable for actual scanout (hence the name), which
363 * implies extra layout constraints on some hardware. It may also
364 * have some special meaning regarding mouse cursor images.
365 *
366 * The shared flag is quite underspecified, but certainly isn't a
367 * binding flag - it seems more like a message to the winsys to create
368 * a shareable allocation.
369 *
370 * The third flag has been added to be able to force textures to be created
371 * in linear mode (no tiling).
372 */
373 #define PIPE_BIND_SCANOUT (1 << 14) /* */
374 #define PIPE_BIND_SHARED (1 << 15) /* get_texture_handle ??? */
375 #define PIPE_BIND_LINEAR (1 << 21)
376
377
378 /* Flags for the driver about resource behaviour:
379 */
380 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
381 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
382 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
383 #define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
384
385 /* Hint about the expected lifecycle of a resource.
386 * Sorted according to GPU vs CPU access.
387 */
388 #define PIPE_USAGE_DEFAULT 0 /* fast GPU access */
389 #define PIPE_USAGE_IMMUTABLE 1 /* fast GPU access, immutable */
390 #define PIPE_USAGE_DYNAMIC 2 /* uploaded data is used multiple times */
391 #define PIPE_USAGE_STREAM 3 /* uploaded data is used once */
392 #define PIPE_USAGE_STAGING 4 /* fast CPU access */
393
394
395 /**
396 * Shaders
397 */
398 #define PIPE_SHADER_VERTEX 0
399 #define PIPE_SHADER_FRAGMENT 1
400 #define PIPE_SHADER_GEOMETRY 2
401 #define PIPE_SHADER_COMPUTE 3
402 #define PIPE_SHADER_TYPES 4
403
404
405 /**
406 * Primitive types:
407 */
408 #define PIPE_PRIM_POINTS 0
409 #define PIPE_PRIM_LINES 1
410 #define PIPE_PRIM_LINE_LOOP 2
411 #define PIPE_PRIM_LINE_STRIP 3
412 #define PIPE_PRIM_TRIANGLES 4
413 #define PIPE_PRIM_TRIANGLE_STRIP 5
414 #define PIPE_PRIM_TRIANGLE_FAN 6
415 #define PIPE_PRIM_QUADS 7
416 #define PIPE_PRIM_QUAD_STRIP 8
417 #define PIPE_PRIM_POLYGON 9
418 #define PIPE_PRIM_LINES_ADJACENCY 10
419 #define PIPE_PRIM_LINE_STRIP_ADJACENCY 11
420 #define PIPE_PRIM_TRIANGLES_ADJACENCY 12
421 #define PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY 13
422 #define PIPE_PRIM_MAX 14
423
424
425 /**
426 * Query object types
427 */
428 #define PIPE_QUERY_OCCLUSION_COUNTER 0
429 #define PIPE_QUERY_OCCLUSION_PREDICATE 1
430 #define PIPE_QUERY_TIMESTAMP 2
431 #define PIPE_QUERY_TIMESTAMP_DISJOINT 3
432 #define PIPE_QUERY_TIME_ELAPSED 4
433 #define PIPE_QUERY_PRIMITIVES_GENERATED 5
434 #define PIPE_QUERY_PRIMITIVES_EMITTED 6
435 #define PIPE_QUERY_SO_STATISTICS 7
436 #define PIPE_QUERY_SO_OVERFLOW_PREDICATE 8
437 #define PIPE_QUERY_GPU_FINISHED 9
438 #define PIPE_QUERY_PIPELINE_STATISTICS 10
439 #define PIPE_QUERY_TYPES 11
440
441 /* start of driver queries,
442 * see pipe_screen::get_driver_query_info */
443 #define PIPE_QUERY_DRIVER_SPECIFIC 256
444
445
446 /**
447 * Conditional rendering modes
448 */
449 #define PIPE_RENDER_COND_WAIT 0
450 #define PIPE_RENDER_COND_NO_WAIT 1
451 #define PIPE_RENDER_COND_BY_REGION_WAIT 2
452 #define PIPE_RENDER_COND_BY_REGION_NO_WAIT 3
453
454
455 /**
456 * Point sprite coord modes
457 */
458 #define PIPE_SPRITE_COORD_UPPER_LEFT 0
459 #define PIPE_SPRITE_COORD_LOWER_LEFT 1
460
461
462 /**
463 * Texture swizzles
464 */
465 #define PIPE_SWIZZLE_RED 0
466 #define PIPE_SWIZZLE_GREEN 1
467 #define PIPE_SWIZZLE_BLUE 2
468 #define PIPE_SWIZZLE_ALPHA 3
469 #define PIPE_SWIZZLE_ZERO 4
470 #define PIPE_SWIZZLE_ONE 5
471
472
473 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
474
475 /**
476 * Implementation capabilities/limits which are queried through
477 * pipe_screen::get_param()
478 */
479 enum pipe_cap {
480 PIPE_CAP_NPOT_TEXTURES = 1,
481 PIPE_CAP_TWO_SIDED_STENCIL = 2,
482 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS = 4,
483 PIPE_CAP_ANISOTROPIC_FILTER = 5,
484 PIPE_CAP_POINT_SPRITE = 6,
485 PIPE_CAP_MAX_RENDER_TARGETS = 7,
486 PIPE_CAP_OCCLUSION_QUERY = 8,
487 PIPE_CAP_QUERY_TIME_ELAPSED = 9,
488 PIPE_CAP_TEXTURE_SHADOW_MAP = 10,
489 PIPE_CAP_TEXTURE_SWIZZLE = 11,
490 PIPE_CAP_MAX_TEXTURE_2D_LEVELS = 12,
491 PIPE_CAP_MAX_TEXTURE_3D_LEVELS = 13,
492 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS = 14,
493 PIPE_CAP_TEXTURE_MIRROR_CLAMP = 25,
494 PIPE_CAP_BLEND_EQUATION_SEPARATE = 28,
495 PIPE_CAP_SM3 = 29, /*< Shader Model, supported */
496 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS = 30,
497 PIPE_CAP_PRIMITIVE_RESTART = 31,
498 /** blend enables and write masks per rendertarget */
499 PIPE_CAP_INDEP_BLEND_ENABLE = 33,
500 /** different blend funcs per rendertarget */
501 PIPE_CAP_INDEP_BLEND_FUNC = 34,
502 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS = 36,
503 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT = 37,
504 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT = 38,
505 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER = 39,
506 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER = 40,
507 PIPE_CAP_DEPTH_CLIP_DISABLE = 41,
508 PIPE_CAP_SHADER_STENCIL_EXPORT = 42,
509 PIPE_CAP_TGSI_INSTANCEID = 43,
510 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR = 44,
511 PIPE_CAP_FRAGMENT_COLOR_CLAMPED = 45,
512 PIPE_CAP_MIXED_COLORBUFFER_FORMATS = 46,
513 PIPE_CAP_SEAMLESS_CUBE_MAP = 47,
514 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE = 48,
515 PIPE_CAP_MIN_TEXEL_OFFSET = 50,
516 PIPE_CAP_MAX_TEXEL_OFFSET = 51,
517 PIPE_CAP_CONDITIONAL_RENDER = 52,
518 PIPE_CAP_TEXTURE_BARRIER = 53,
519 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS = 55,
520 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS = 56,
521 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME = 57,
522 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS = 59, /* temporary */
523 PIPE_CAP_VERTEX_COLOR_UNCLAMPED = 60,
524 PIPE_CAP_VERTEX_COLOR_CLAMPED = 61,
525 PIPE_CAP_GLSL_FEATURE_LEVEL = 62,
526 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION = 63,
527 PIPE_CAP_USER_VERTEX_BUFFERS = 64,
528 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY = 65,
529 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY = 66,
530 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY = 67,
531 PIPE_CAP_COMPUTE = 68,
532 PIPE_CAP_USER_INDEX_BUFFERS = 69,
533 PIPE_CAP_USER_CONSTANT_BUFFERS = 70,
534 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT = 71,
535 PIPE_CAP_START_INSTANCE = 72,
536 PIPE_CAP_QUERY_TIMESTAMP = 73,
537 PIPE_CAP_TEXTURE_MULTISAMPLE = 74,
538 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT = 75,
539 PIPE_CAP_CUBE_MAP_ARRAY = 76,
540 PIPE_CAP_TEXTURE_BUFFER_OBJECTS = 77,
541 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT = 78,
542 PIPE_CAP_TGSI_TEXCOORD = 79,
543 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER = 80,
544 PIPE_CAP_QUERY_PIPELINE_STATISTICS = 81,
545 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK = 82,
546 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE = 83,
547 PIPE_CAP_MAX_VIEWPORTS = 84,
548 PIPE_CAP_ENDIANNESS = 85,
549 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES = 86,
550 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT = 87,
551 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES = 88,
552 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS = 89,
553 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS = 90,
554 PIPE_CAP_TEXTURE_GATHER_SM5 = 91,
555 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT = 92,
556 PIPE_CAP_FAKE_SW_MSAA = 93,
557 PIPE_CAP_TEXTURE_QUERY_LOD = 94,
558 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET = 95,
559 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET = 96,
560 PIPE_CAP_SAMPLE_SHADING = 97,
561 PIPE_CAP_TEXTURE_GATHER_OFFSETS = 98,
562 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION = 99,
563 PIPE_CAP_MAX_VERTEX_STREAMS = 100,
564 PIPE_CAP_DRAW_INDIRECT = 101,
565 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE = 102,
566 PIPE_CAP_VENDOR_ID = 103,
567 PIPE_CAP_DEVICE_ID = 104,
568 PIPE_CAP_ACCELERATED = 105,
569 PIPE_CAP_VIDEO_MEMORY = 106,
570 PIPE_CAP_UMA = 107,
571 PIPE_CAP_CONDITIONAL_RENDER_INVERTED = 108,
572 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE = 109,
573 PIPE_CAP_SAMPLER_VIEW_TARGET = 110,
574 PIPE_CAP_CLIP_HALFZ = 111,
575 PIPE_CAP_VERTEXID_NOBASE = 112,
576 PIPE_CAP_POLYGON_OFFSET_CLAMP = 113,
577 PIPE_CAP_MULTISAMPLE_Z_RESOLVE = 114,
578 PIPE_CAP_RESOURCE_FROM_USER_MEMORY = 115,
579 };
580
581 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
582 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
583
584 enum pipe_endian {
585 PIPE_ENDIAN_LITTLE = 0,
586 PIPE_ENDIAN_BIG = 1,
587 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
588 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
589 #elif defined(PIPE_ARCH_BIG_ENDIAN)
590 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
591 #endif
592 };
593
594 /**
595 * Implementation limits which are queried through
596 * pipe_screen::get_paramf()
597 */
598 enum pipe_capf
599 {
600 PIPE_CAPF_MAX_LINE_WIDTH,
601 PIPE_CAPF_MAX_LINE_WIDTH_AA,
602 PIPE_CAPF_MAX_POINT_WIDTH,
603 PIPE_CAPF_MAX_POINT_WIDTH_AA,
604 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
605 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
606 PIPE_CAPF_GUARD_BAND_LEFT,
607 PIPE_CAPF_GUARD_BAND_TOP,
608 PIPE_CAPF_GUARD_BAND_RIGHT,
609 PIPE_CAPF_GUARD_BAND_BOTTOM
610 };
611
612 /* Shader caps not specific to any single stage */
613 enum pipe_shader_cap
614 {
615 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
616 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
617 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
618 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
619 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
620 PIPE_SHADER_CAP_MAX_INPUTS,
621 PIPE_SHADER_CAP_MAX_OUTPUTS,
622 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
623 PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
624 PIPE_SHADER_CAP_MAX_TEMPS,
625 PIPE_SHADER_CAP_MAX_PREDS,
626 /* boolean caps */
627 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
628 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
629 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
630 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
631 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
632 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
633 PIPE_SHADER_CAP_INTEGERS,
634 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
635 PIPE_SHADER_CAP_PREFERRED_IR,
636 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
637 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
638 PIPE_SHADER_CAP_DOUBLES
639 };
640
641 /**
642 * Shader intermediate representation.
643 */
644 enum pipe_shader_ir
645 {
646 PIPE_SHADER_IR_TGSI,
647 PIPE_SHADER_IR_LLVM,
648 PIPE_SHADER_IR_NATIVE
649 };
650
651 /**
652 * Compute-specific implementation capability. They can be queried
653 * using pipe_screen::get_compute_param.
654 */
655 enum pipe_compute_cap
656 {
657 PIPE_COMPUTE_CAP_IR_TARGET,
658 PIPE_COMPUTE_CAP_GRID_DIMENSION,
659 PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
660 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
661 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
662 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
663 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
664 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
665 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
666 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
667 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
668 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
669 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
670 };
671
672 /**
673 * Composite query types
674 */
675
676 /**
677 * Query result for PIPE_QUERY_SO_STATISTICS.
678 */
679 struct pipe_query_data_so_statistics
680 {
681 uint64_t num_primitives_written;
682 uint64_t primitives_storage_needed;
683 };
684
685 /**
686 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
687 */
688 struct pipe_query_data_timestamp_disjoint
689 {
690 uint64_t frequency;
691 boolean disjoint;
692 };
693
694 /**
695 * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
696 */
697 struct pipe_query_data_pipeline_statistics
698 {
699 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */
700 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */
701 uint64_t vs_invocations; /**< Num vertex shader invocations. */
702 uint64_t gs_invocations; /**< Num geometry shader invocations. */
703 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */
704 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */
705 uint64_t c_primitives; /**< Num primitives that were rendered. */
706 uint64_t ps_invocations; /**< Num pixel shader invocations. */
707 uint64_t hs_invocations; /**< Num hull shader invocations. */
708 uint64_t ds_invocations; /**< Num domain shader invocations. */
709 uint64_t cs_invocations; /**< Num compute shader invocations. */
710 };
711
712 /**
713 * Query result (returned by pipe_context::get_query_result).
714 */
715 union pipe_query_result
716 {
717 /* PIPE_QUERY_OCCLUSION_PREDICATE */
718 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
719 /* PIPE_QUERY_GPU_FINISHED */
720 boolean b;
721
722 /* PIPE_QUERY_OCCLUSION_COUNTER */
723 /* PIPE_QUERY_TIMESTAMP */
724 /* PIPE_QUERY_TIME_ELAPSED */
725 /* PIPE_QUERY_PRIMITIVES_GENERATED */
726 /* PIPE_QUERY_PRIMITIVES_EMITTED */
727 uint64_t u64;
728
729 /* PIPE_QUERY_SO_STATISTICS */
730 struct pipe_query_data_so_statistics so_statistics;
731
732 /* PIPE_QUERY_TIMESTAMP_DISJOINT */
733 struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
734
735 /* PIPE_QUERY_PIPELINE_STATISTICS */
736 struct pipe_query_data_pipeline_statistics pipeline_statistics;
737 };
738
739 union pipe_color_union
740 {
741 float f[4];
742 int i[4];
743 unsigned int ui[4];
744 };
745
746 struct pipe_driver_query_info
747 {
748 const char *name;
749 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
750 uint64_t max_value; /* max value that can be returned */
751 boolean uses_byte_units; /* whether the result is in bytes */
752 };
753
754 #ifdef __cplusplus
755 }
756 #endif
757
758 #endif