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[mesa.git] / src / gallium / include / pipe / p_defines.h
1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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26 **************************************************************************/
27
28 #ifndef PIPE_DEFINES_H
29 #define PIPE_DEFINES_H
30
31 #include "p_compiler.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /**
38 * Gallium error codes.
39 *
40 * - A zero value always means success.
41 * - A negative value always means failure.
42 * - The meaning of a positive value is function dependent.
43 */
44 enum pipe_error
45 {
46 PIPE_OK = 0,
47 PIPE_ERROR = -1, /**< Generic error */
48 PIPE_ERROR_BAD_INPUT = -2,
49 PIPE_ERROR_OUT_OF_MEMORY = -3,
50 PIPE_ERROR_RETRY = -4
51 /* TODO */
52 };
53
54
55 #define PIPE_BLENDFACTOR_ONE 0x1
56 #define PIPE_BLENDFACTOR_SRC_COLOR 0x2
57 #define PIPE_BLENDFACTOR_SRC_ALPHA 0x3
58 #define PIPE_BLENDFACTOR_DST_ALPHA 0x4
59 #define PIPE_BLENDFACTOR_DST_COLOR 0x5
60 #define PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
61 #define PIPE_BLENDFACTOR_CONST_COLOR 0x7
62 #define PIPE_BLENDFACTOR_CONST_ALPHA 0x8
63 #define PIPE_BLENDFACTOR_SRC1_COLOR 0x9
64 #define PIPE_BLENDFACTOR_SRC1_ALPHA 0x0A
65 #define PIPE_BLENDFACTOR_ZERO 0x11
66 #define PIPE_BLENDFACTOR_INV_SRC_COLOR 0x12
67 #define PIPE_BLENDFACTOR_INV_SRC_ALPHA 0x13
68 #define PIPE_BLENDFACTOR_INV_DST_ALPHA 0x14
69 #define PIPE_BLENDFACTOR_INV_DST_COLOR 0x15
70 #define PIPE_BLENDFACTOR_INV_CONST_COLOR 0x17
71 #define PIPE_BLENDFACTOR_INV_CONST_ALPHA 0x18
72 #define PIPE_BLENDFACTOR_INV_SRC1_COLOR 0x19
73 #define PIPE_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
74
75 #define PIPE_BLEND_ADD 0
76 #define PIPE_BLEND_SUBTRACT 1
77 #define PIPE_BLEND_REVERSE_SUBTRACT 2
78 #define PIPE_BLEND_MIN 3
79 #define PIPE_BLEND_MAX 4
80
81 #define PIPE_LOGICOP_CLEAR 0
82 #define PIPE_LOGICOP_NOR 1
83 #define PIPE_LOGICOP_AND_INVERTED 2
84 #define PIPE_LOGICOP_COPY_INVERTED 3
85 #define PIPE_LOGICOP_AND_REVERSE 4
86 #define PIPE_LOGICOP_INVERT 5
87 #define PIPE_LOGICOP_XOR 6
88 #define PIPE_LOGICOP_NAND 7
89 #define PIPE_LOGICOP_AND 8
90 #define PIPE_LOGICOP_EQUIV 9
91 #define PIPE_LOGICOP_NOOP 10
92 #define PIPE_LOGICOP_OR_INVERTED 11
93 #define PIPE_LOGICOP_COPY 12
94 #define PIPE_LOGICOP_OR_REVERSE 13
95 #define PIPE_LOGICOP_OR 14
96 #define PIPE_LOGICOP_SET 15
97
98 #define PIPE_MASK_R 0x1
99 #define PIPE_MASK_G 0x2
100 #define PIPE_MASK_B 0x4
101 #define PIPE_MASK_A 0x8
102 #define PIPE_MASK_RGBA 0xf
103 #define PIPE_MASK_Z 0x10
104 #define PIPE_MASK_S 0x20
105 #define PIPE_MASK_ZS 0x30
106 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
107
108
109 /**
110 * Inequality functions. Used for depth test, stencil compare, alpha
111 * test, shadow compare, etc.
112 */
113 #define PIPE_FUNC_NEVER 0
114 #define PIPE_FUNC_LESS 1
115 #define PIPE_FUNC_EQUAL 2
116 #define PIPE_FUNC_LEQUAL 3
117 #define PIPE_FUNC_GREATER 4
118 #define PIPE_FUNC_NOTEQUAL 5
119 #define PIPE_FUNC_GEQUAL 6
120 #define PIPE_FUNC_ALWAYS 7
121
122 /** Polygon fill mode */
123 #define PIPE_POLYGON_MODE_FILL 0
124 #define PIPE_POLYGON_MODE_LINE 1
125 #define PIPE_POLYGON_MODE_POINT 2
126
127 /** Polygon face specification, eg for culling */
128 #define PIPE_FACE_NONE 0
129 #define PIPE_FACE_FRONT 1
130 #define PIPE_FACE_BACK 2
131 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
132
133 /** Stencil ops */
134 #define PIPE_STENCIL_OP_KEEP 0
135 #define PIPE_STENCIL_OP_ZERO 1
136 #define PIPE_STENCIL_OP_REPLACE 2
137 #define PIPE_STENCIL_OP_INCR 3
138 #define PIPE_STENCIL_OP_DECR 4
139 #define PIPE_STENCIL_OP_INCR_WRAP 5
140 #define PIPE_STENCIL_OP_DECR_WRAP 6
141 #define PIPE_STENCIL_OP_INVERT 7
142
143 /** Texture types.
144 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
145 */
146 enum pipe_texture_target
147 {
148 PIPE_BUFFER = 0,
149 PIPE_TEXTURE_1D = 1,
150 PIPE_TEXTURE_2D = 2,
151 PIPE_TEXTURE_3D = 3,
152 PIPE_TEXTURE_CUBE = 4,
153 PIPE_TEXTURE_RECT = 5,
154 PIPE_TEXTURE_1D_ARRAY = 6,
155 PIPE_TEXTURE_2D_ARRAY = 7,
156 PIPE_TEXTURE_CUBE_ARRAY = 8,
157 PIPE_MAX_TEXTURE_TYPES
158 };
159
160 #define PIPE_TEX_FACE_POS_X 0
161 #define PIPE_TEX_FACE_NEG_X 1
162 #define PIPE_TEX_FACE_POS_Y 2
163 #define PIPE_TEX_FACE_NEG_Y 3
164 #define PIPE_TEX_FACE_POS_Z 4
165 #define PIPE_TEX_FACE_NEG_Z 5
166 #define PIPE_TEX_FACE_MAX 6
167
168 #define PIPE_TEX_WRAP_REPEAT 0
169 #define PIPE_TEX_WRAP_CLAMP 1
170 #define PIPE_TEX_WRAP_CLAMP_TO_EDGE 2
171 #define PIPE_TEX_WRAP_CLAMP_TO_BORDER 3
172 #define PIPE_TEX_WRAP_MIRROR_REPEAT 4
173 #define PIPE_TEX_WRAP_MIRROR_CLAMP 5
174 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE 6
175 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER 7
176
177 /** Between mipmaps, ie mipfilter */
178 #define PIPE_TEX_MIPFILTER_NEAREST 0
179 #define PIPE_TEX_MIPFILTER_LINEAR 1
180 #define PIPE_TEX_MIPFILTER_NONE 2
181
182 /** Within a mipmap, ie min/mag filter */
183 #define PIPE_TEX_FILTER_NEAREST 0
184 #define PIPE_TEX_FILTER_LINEAR 1
185
186 #define PIPE_TEX_COMPARE_NONE 0
187 #define PIPE_TEX_COMPARE_R_TO_TEXTURE 1
188
189 /**
190 * Clear buffer bits
191 */
192 #define PIPE_CLEAR_DEPTH (1 << 0)
193 #define PIPE_CLEAR_STENCIL (1 << 1)
194 #define PIPE_CLEAR_COLOR0 (1 << 2)
195 #define PIPE_CLEAR_COLOR1 (1 << 3)
196 #define PIPE_CLEAR_COLOR2 (1 << 4)
197 #define PIPE_CLEAR_COLOR3 (1 << 5)
198 #define PIPE_CLEAR_COLOR4 (1 << 6)
199 #define PIPE_CLEAR_COLOR5 (1 << 7)
200 #define PIPE_CLEAR_COLOR6 (1 << 8)
201 #define PIPE_CLEAR_COLOR7 (1 << 9)
202 /** Combined flags */
203 /** All color buffers currently bound */
204 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
205 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
206 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
207 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
208 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
209
210 /**
211 * Transfer object usage flags
212 */
213 enum pipe_transfer_usage
214 {
215 /**
216 * Resource contents read back (or accessed directly) at transfer
217 * create time.
218 */
219 PIPE_TRANSFER_READ = (1 << 0),
220
221 /**
222 * Resource contents will be written back at transfer_unmap
223 * time (or modified as a result of being accessed directly).
224 */
225 PIPE_TRANSFER_WRITE = (1 << 1),
226
227 /**
228 * Read/modify/write
229 */
230 PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
231
232 /**
233 * The transfer should map the texture storage directly. The driver may
234 * return NULL if that isn't possible, and the state tracker needs to cope
235 * with that and use an alternative path without this flag.
236 *
237 * E.g. the state tracker could have a simpler path which maps textures and
238 * does read/modify/write cycles on them directly, and a more complicated
239 * path which uses minimal read and write transfers.
240 */
241 PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
242
243 /**
244 * Discards the memory within the mapped region.
245 *
246 * It should not be used with PIPE_TRANSFER_READ.
247 *
248 * See also:
249 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
250 */
251 PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
252
253 /**
254 * Fail if the resource cannot be mapped immediately.
255 *
256 * See also:
257 * - Direct3D's D3DLOCK_DONOTWAIT flag.
258 * - Mesa3D's MESA_MAP_NOWAIT_BIT flag.
259 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
260 */
261 PIPE_TRANSFER_DONTBLOCK = (1 << 9),
262
263 /**
264 * Do not attempt to synchronize pending operations on the resource when mapping.
265 *
266 * It should not be used with PIPE_TRANSFER_READ.
267 *
268 * See also:
269 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
270 * - Direct3D's D3DLOCK_NOOVERWRITE flag.
271 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
272 */
273 PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
274
275 /**
276 * Written ranges will be notified later with
277 * pipe_context::transfer_flush_region.
278 *
279 * It should not be used with PIPE_TRANSFER_READ.
280 *
281 * See also:
282 * - pipe_context::transfer_flush_region
283 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
284 */
285 PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
286
287 /**
288 * Discards all memory backing the resource.
289 *
290 * It should not be used with PIPE_TRANSFER_READ.
291 *
292 * This is equivalent to:
293 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
294 * - BufferData(NULL) on a GL buffer
295 * - Direct3D's D3DLOCK_DISCARD flag.
296 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
297 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
298 * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
299 */
300 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
301
302 /**
303 * Allows the resource to be used for rendering while mapped.
304 *
305 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
306 * the resource.
307 *
308 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
309 * must be called to ensure the device can see what the CPU has written.
310 */
311 PIPE_TRANSFER_PERSISTENT = (1 << 13),
312
313 /**
314 * If PERSISTENT is set, this ensures any writes done by the device are
315 * immediately visible to the CPU and vice versa.
316 *
317 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
318 * the resource.
319 */
320 PIPE_TRANSFER_COHERENT = (1 << 14)
321 };
322
323 /**
324 * Flags for the flush function.
325 */
326 enum pipe_flush_flags
327 {
328 PIPE_FLUSH_END_OF_FRAME = (1 << 0)
329 };
330
331 /**
332 * Flags for pipe_context::memory_barrier.
333 */
334 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0)
335
336 /**
337 * Resource binding flags -- state tracker must specify in advance all
338 * the ways a resource might be used.
339 */
340 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */
341 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */
342 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */
343 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */
344 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */
345 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */
346 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */
347 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */
348 #define PIPE_BIND_TRANSFER_WRITE (1 << 8) /* transfer_map */
349 #define PIPE_BIND_TRANSFER_READ (1 << 9) /* transfer_map */
350 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */
351 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */
352 #define PIPE_BIND_CUSTOM (1 << 12) /* state-tracker/winsys usages */
353 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */
354 #define PIPE_BIND_SHADER_RESOURCE (1 << 14) /* set_shader_resources */
355 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 15) /* set_compute_resources */
356 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 16) /* pipe_draw_info.indirect */
357
358 /**
359 * The first two flags above were previously part of the amorphous
360 * TEXTURE_USAGE, most of which are now descriptions of the ways a
361 * particular texture can be bound to the gallium pipeline. The two flags
362 * below do not fit within that and probably need to be migrated to some
363 * other place.
364 *
365 * It seems like scanout is used by the Xorg state tracker to ask for
366 * a texture suitable for actual scanout (hence the name), which
367 * implies extra layout constraints on some hardware. It may also
368 * have some special meaning regarding mouse cursor images.
369 *
370 * The shared flag is quite underspecified, but certainly isn't a
371 * binding flag - it seems more like a message to the winsys to create
372 * a shareable allocation.
373 *
374 * The third flag has been added to be able to force textures to be created
375 * in linear mode (no tiling).
376 */
377 #define PIPE_BIND_SCANOUT (1 << 17) /* */
378 #define PIPE_BIND_SHARED (1 << 18) /* get_texture_handle ??? */
379 #define PIPE_BIND_LINEAR (1 << 19)
380
381
382 /**
383 * Flags for the driver about resource behaviour:
384 */
385 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
386 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
387 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
388 #define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
389
390 /**
391 * Hint about the expected lifecycle of a resource.
392 * Sorted according to GPU vs CPU access.
393 */
394 #define PIPE_USAGE_DEFAULT 0 /* fast GPU access */
395 #define PIPE_USAGE_IMMUTABLE 1 /* fast GPU access, immutable */
396 #define PIPE_USAGE_DYNAMIC 2 /* uploaded data is used multiple times */
397 #define PIPE_USAGE_STREAM 3 /* uploaded data is used once */
398 #define PIPE_USAGE_STAGING 4 /* fast CPU access */
399
400
401 /**
402 * Shaders
403 */
404 #define PIPE_SHADER_VERTEX 0
405 #define PIPE_SHADER_FRAGMENT 1
406 #define PIPE_SHADER_GEOMETRY 2
407 #define PIPE_SHADER_TESS_CTRL 3
408 #define PIPE_SHADER_TESS_EVAL 4
409 #define PIPE_SHADER_COMPUTE 5
410 #define PIPE_SHADER_TYPES 6
411
412
413 /**
414 * Primitive types:
415 */
416 #define PIPE_PRIM_POINTS 0
417 #define PIPE_PRIM_LINES 1
418 #define PIPE_PRIM_LINE_LOOP 2
419 #define PIPE_PRIM_LINE_STRIP 3
420 #define PIPE_PRIM_TRIANGLES 4
421 #define PIPE_PRIM_TRIANGLE_STRIP 5
422 #define PIPE_PRIM_TRIANGLE_FAN 6
423 #define PIPE_PRIM_QUADS 7
424 #define PIPE_PRIM_QUAD_STRIP 8
425 #define PIPE_PRIM_POLYGON 9
426 #define PIPE_PRIM_LINES_ADJACENCY 10
427 #define PIPE_PRIM_LINE_STRIP_ADJACENCY 11
428 #define PIPE_PRIM_TRIANGLES_ADJACENCY 12
429 #define PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY 13
430 #define PIPE_PRIM_PATCHES 14
431 #define PIPE_PRIM_MAX 15
432
433
434 /**
435 * Query object types
436 */
437 #define PIPE_QUERY_OCCLUSION_COUNTER 0
438 #define PIPE_QUERY_OCCLUSION_PREDICATE 1
439 #define PIPE_QUERY_TIMESTAMP 2
440 #define PIPE_QUERY_TIMESTAMP_DISJOINT 3
441 #define PIPE_QUERY_TIME_ELAPSED 4
442 #define PIPE_QUERY_PRIMITIVES_GENERATED 5
443 #define PIPE_QUERY_PRIMITIVES_EMITTED 6
444 #define PIPE_QUERY_SO_STATISTICS 7
445 #define PIPE_QUERY_SO_OVERFLOW_PREDICATE 8
446 #define PIPE_QUERY_GPU_FINISHED 9
447 #define PIPE_QUERY_PIPELINE_STATISTICS 10
448 #define PIPE_QUERY_TYPES 11
449 /* start of driver queries, see pipe_screen::get_driver_query_info */
450 #define PIPE_QUERY_DRIVER_SPECIFIC 256
451
452
453 /**
454 * Conditional rendering modes
455 */
456 #define PIPE_RENDER_COND_WAIT 0
457 #define PIPE_RENDER_COND_NO_WAIT 1
458 #define PIPE_RENDER_COND_BY_REGION_WAIT 2
459 #define PIPE_RENDER_COND_BY_REGION_NO_WAIT 3
460
461
462 /**
463 * Point sprite coord modes
464 */
465 #define PIPE_SPRITE_COORD_UPPER_LEFT 0
466 #define PIPE_SPRITE_COORD_LOWER_LEFT 1
467
468
469 /**
470 * Texture swizzles
471 */
472 #define PIPE_SWIZZLE_RED 0
473 #define PIPE_SWIZZLE_GREEN 1
474 #define PIPE_SWIZZLE_BLUE 2
475 #define PIPE_SWIZZLE_ALPHA 3
476 #define PIPE_SWIZZLE_ZERO 4
477 #define PIPE_SWIZZLE_ONE 5
478
479
480 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
481
482
483 /**
484 * Device reset status.
485 */
486 enum pipe_reset_status
487 {
488 PIPE_NO_RESET = 0,
489 PIPE_GUILTY_CONTEXT_RESET = 1,
490 PIPE_INNOCENT_CONTEXT_RESET = 2,
491 PIPE_UNKNOWN_CONTEXT_RESET = 3
492 };
493
494
495 /**
496 * Implementation capabilities/limits which are queried through
497 * pipe_screen::get_param()
498 */
499 enum pipe_cap
500 {
501 PIPE_CAP_NPOT_TEXTURES = 1,
502 PIPE_CAP_TWO_SIDED_STENCIL = 2,
503 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS = 4,
504 PIPE_CAP_ANISOTROPIC_FILTER = 5,
505 PIPE_CAP_POINT_SPRITE = 6,
506 PIPE_CAP_MAX_RENDER_TARGETS = 7,
507 PIPE_CAP_OCCLUSION_QUERY = 8,
508 PIPE_CAP_QUERY_TIME_ELAPSED = 9,
509 PIPE_CAP_TEXTURE_SHADOW_MAP = 10,
510 PIPE_CAP_TEXTURE_SWIZZLE = 11,
511 PIPE_CAP_MAX_TEXTURE_2D_LEVELS = 12,
512 PIPE_CAP_MAX_TEXTURE_3D_LEVELS = 13,
513 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS = 14,
514 PIPE_CAP_TEXTURE_MIRROR_CLAMP = 25,
515 PIPE_CAP_BLEND_EQUATION_SEPARATE = 28,
516 PIPE_CAP_SM3 = 29, /*< Shader Model, supported */
517 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS = 30,
518 PIPE_CAP_PRIMITIVE_RESTART = 31,
519 /** blend enables and write masks per rendertarget */
520 PIPE_CAP_INDEP_BLEND_ENABLE = 33,
521 /** different blend funcs per rendertarget */
522 PIPE_CAP_INDEP_BLEND_FUNC = 34,
523 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS = 36,
524 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT = 37,
525 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT = 38,
526 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER = 39,
527 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER = 40,
528 PIPE_CAP_DEPTH_CLIP_DISABLE = 41,
529 PIPE_CAP_SHADER_STENCIL_EXPORT = 42,
530 PIPE_CAP_TGSI_INSTANCEID = 43,
531 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR = 44,
532 PIPE_CAP_FRAGMENT_COLOR_CLAMPED = 45,
533 PIPE_CAP_MIXED_COLORBUFFER_FORMATS = 46,
534 PIPE_CAP_SEAMLESS_CUBE_MAP = 47,
535 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE = 48,
536 PIPE_CAP_MIN_TEXEL_OFFSET = 50,
537 PIPE_CAP_MAX_TEXEL_OFFSET = 51,
538 PIPE_CAP_CONDITIONAL_RENDER = 52,
539 PIPE_CAP_TEXTURE_BARRIER = 53,
540 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS = 55,
541 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS = 56,
542 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME = 57,
543 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS = 59, /* temporary */
544 PIPE_CAP_VERTEX_COLOR_UNCLAMPED = 60,
545 PIPE_CAP_VERTEX_COLOR_CLAMPED = 61,
546 PIPE_CAP_GLSL_FEATURE_LEVEL = 62,
547 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION = 63,
548 PIPE_CAP_USER_VERTEX_BUFFERS = 64,
549 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY = 65,
550 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY = 66,
551 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY = 67,
552 PIPE_CAP_COMPUTE = 68,
553 PIPE_CAP_USER_INDEX_BUFFERS = 69,
554 PIPE_CAP_USER_CONSTANT_BUFFERS = 70,
555 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT = 71,
556 PIPE_CAP_START_INSTANCE = 72,
557 PIPE_CAP_QUERY_TIMESTAMP = 73,
558 PIPE_CAP_TEXTURE_MULTISAMPLE = 74,
559 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT = 75,
560 PIPE_CAP_CUBE_MAP_ARRAY = 76,
561 PIPE_CAP_TEXTURE_BUFFER_OBJECTS = 77,
562 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT = 78,
563 PIPE_CAP_TGSI_TEXCOORD = 79,
564 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER = 80,
565 PIPE_CAP_QUERY_PIPELINE_STATISTICS = 81,
566 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK = 82,
567 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE = 83,
568 PIPE_CAP_MAX_VIEWPORTS = 84,
569 PIPE_CAP_ENDIANNESS = 85,
570 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES = 86,
571 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT = 87,
572 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES = 88,
573 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS = 89,
574 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS = 90,
575 PIPE_CAP_TEXTURE_GATHER_SM5 = 91,
576 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT = 92,
577 PIPE_CAP_FAKE_SW_MSAA = 93,
578 PIPE_CAP_TEXTURE_QUERY_LOD = 94,
579 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET = 95,
580 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET = 96,
581 PIPE_CAP_SAMPLE_SHADING = 97,
582 PIPE_CAP_TEXTURE_GATHER_OFFSETS = 98,
583 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION = 99,
584 PIPE_CAP_MAX_VERTEX_STREAMS = 100,
585 PIPE_CAP_DRAW_INDIRECT = 101,
586 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE = 102,
587 PIPE_CAP_VENDOR_ID = 103,
588 PIPE_CAP_DEVICE_ID = 104,
589 PIPE_CAP_ACCELERATED = 105,
590 PIPE_CAP_VIDEO_MEMORY = 106,
591 PIPE_CAP_UMA = 107,
592 PIPE_CAP_CONDITIONAL_RENDER_INVERTED = 108,
593 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE = 109,
594 PIPE_CAP_SAMPLER_VIEW_TARGET = 110,
595 PIPE_CAP_CLIP_HALFZ = 111,
596 PIPE_CAP_VERTEXID_NOBASE = 112,
597 PIPE_CAP_POLYGON_OFFSET_CLAMP = 113,
598 PIPE_CAP_MULTISAMPLE_Z_RESOLVE = 114,
599 PIPE_CAP_RESOURCE_FROM_USER_MEMORY = 115,
600 PIPE_CAP_DEVICE_RESET_STATUS_QUERY = 116,
601 };
602
603 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
604 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
605
606 enum pipe_endian
607 {
608 PIPE_ENDIAN_LITTLE = 0,
609 PIPE_ENDIAN_BIG = 1,
610 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
611 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
612 #elif defined(PIPE_ARCH_BIG_ENDIAN)
613 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
614 #endif
615 };
616
617 /**
618 * Implementation limits which are queried through
619 * pipe_screen::get_paramf()
620 */
621 enum pipe_capf
622 {
623 PIPE_CAPF_MAX_LINE_WIDTH,
624 PIPE_CAPF_MAX_LINE_WIDTH_AA,
625 PIPE_CAPF_MAX_POINT_WIDTH,
626 PIPE_CAPF_MAX_POINT_WIDTH_AA,
627 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
628 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
629 PIPE_CAPF_GUARD_BAND_LEFT,
630 PIPE_CAPF_GUARD_BAND_TOP,
631 PIPE_CAPF_GUARD_BAND_RIGHT,
632 PIPE_CAPF_GUARD_BAND_BOTTOM
633 };
634
635 /** Shader caps not specific to any single stage */
636 enum pipe_shader_cap
637 {
638 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
639 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
640 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
641 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
642 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
643 PIPE_SHADER_CAP_MAX_INPUTS,
644 PIPE_SHADER_CAP_MAX_OUTPUTS,
645 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
646 PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
647 PIPE_SHADER_CAP_MAX_TEMPS,
648 PIPE_SHADER_CAP_MAX_PREDS,
649 /* boolean caps */
650 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
651 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
652 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
653 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
654 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
655 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
656 PIPE_SHADER_CAP_INTEGERS,
657 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
658 PIPE_SHADER_CAP_PREFERRED_IR,
659 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
660 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
661 PIPE_SHADER_CAP_DOUBLES,
662 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
663 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
664 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
665 };
666
667 /**
668 * Shader intermediate representation.
669 */
670 enum pipe_shader_ir
671 {
672 PIPE_SHADER_IR_TGSI,
673 PIPE_SHADER_IR_LLVM,
674 PIPE_SHADER_IR_NATIVE
675 };
676
677 /**
678 * Compute-specific implementation capability. They can be queried
679 * using pipe_screen::get_compute_param.
680 */
681 enum pipe_compute_cap
682 {
683 PIPE_COMPUTE_CAP_IR_TARGET,
684 PIPE_COMPUTE_CAP_GRID_DIMENSION,
685 PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
686 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
687 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
688 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
689 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
690 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
691 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
692 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
693 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
694 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
695 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
696 };
697
698 /**
699 * Composite query types
700 */
701
702 /**
703 * Query result for PIPE_QUERY_SO_STATISTICS.
704 */
705 struct pipe_query_data_so_statistics
706 {
707 uint64_t num_primitives_written;
708 uint64_t primitives_storage_needed;
709 };
710
711 /**
712 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
713 */
714 struct pipe_query_data_timestamp_disjoint
715 {
716 uint64_t frequency;
717 boolean disjoint;
718 };
719
720 /**
721 * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
722 */
723 struct pipe_query_data_pipeline_statistics
724 {
725 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */
726 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */
727 uint64_t vs_invocations; /**< Num vertex shader invocations. */
728 uint64_t gs_invocations; /**< Num geometry shader invocations. */
729 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */
730 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */
731 uint64_t c_primitives; /**< Num primitives that were rendered. */
732 uint64_t ps_invocations; /**< Num pixel shader invocations. */
733 uint64_t hs_invocations; /**< Num hull shader invocations. */
734 uint64_t ds_invocations; /**< Num domain shader invocations. */
735 uint64_t cs_invocations; /**< Num compute shader invocations. */
736 };
737
738 /**
739 * Query result (returned by pipe_context::get_query_result).
740 */
741 union pipe_query_result
742 {
743 /* PIPE_QUERY_OCCLUSION_PREDICATE */
744 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
745 /* PIPE_QUERY_GPU_FINISHED */
746 boolean b;
747
748 /* PIPE_QUERY_OCCLUSION_COUNTER */
749 /* PIPE_QUERY_TIMESTAMP */
750 /* PIPE_QUERY_TIME_ELAPSED */
751 /* PIPE_QUERY_PRIMITIVES_GENERATED */
752 /* PIPE_QUERY_PRIMITIVES_EMITTED */
753 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
754 uint64_t u64;
755
756 /* PIPE_DRIVER_QUERY_TYPE_UINT */
757 uint32_t u32;
758
759 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
760 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
761 float f;
762
763 /* PIPE_QUERY_SO_STATISTICS */
764 struct pipe_query_data_so_statistics so_statistics;
765
766 /* PIPE_QUERY_TIMESTAMP_DISJOINT */
767 struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
768
769 /* PIPE_QUERY_PIPELINE_STATISTICS */
770 struct pipe_query_data_pipeline_statistics pipeline_statistics;
771 };
772
773 union pipe_color_union
774 {
775 float f[4];
776 int i[4];
777 unsigned int ui[4];
778 };
779
780 enum pipe_driver_query_type
781 {
782 PIPE_DRIVER_QUERY_TYPE_UINT64 = 0,
783 PIPE_DRIVER_QUERY_TYPE_UINT = 1,
784 PIPE_DRIVER_QUERY_TYPE_FLOAT = 2,
785 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE = 3,
786 PIPE_DRIVER_QUERY_TYPE_BYTES = 4,
787 };
788
789 enum pipe_driver_query_group_type
790 {
791 PIPE_DRIVER_QUERY_GROUP_TYPE_CPU = 0,
792 PIPE_DRIVER_QUERY_GROUP_TYPE_GPU = 1,
793 };
794
795 union pipe_numeric_type_union
796 {
797 uint64_t u64;
798 uint32_t u32;
799 float f;
800 };
801
802 struct pipe_driver_query_info
803 {
804 const char *name;
805 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
806 union pipe_numeric_type_union max_value; /* max value that can be returned */
807 enum pipe_driver_query_type type;
808 unsigned group_id;
809 };
810
811 struct pipe_driver_query_group_info
812 {
813 const char *name;
814 enum pipe_driver_query_group_type type;
815 unsigned max_active_queries;
816 unsigned num_queries;
817 };
818
819 #ifdef __cplusplus
820 }
821 #endif
822
823 #endif