1 /**************************************************************************
3 * Copyright 2007 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef PIPE_DEFINES_H
29 #define PIPE_DEFINES_H
31 #include "p_compiler.h"
38 * Gallium error codes.
40 * - A zero value always means success.
41 * - A negative value always means failure.
42 * - The meaning of a positive value is function dependent.
47 PIPE_ERROR
= -1, /**< Generic error */
48 PIPE_ERROR_BAD_INPUT
= -2,
49 PIPE_ERROR_OUT_OF_MEMORY
= -3,
54 enum pipe_blendfactor
{
55 PIPE_BLENDFACTOR_ONE
= 1,
56 PIPE_BLENDFACTOR_SRC_COLOR
,
57 PIPE_BLENDFACTOR_SRC_ALPHA
,
58 PIPE_BLENDFACTOR_DST_ALPHA
,
59 PIPE_BLENDFACTOR_DST_COLOR
,
60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
,
61 PIPE_BLENDFACTOR_CONST_COLOR
,
62 PIPE_BLENDFACTOR_CONST_ALPHA
,
63 PIPE_BLENDFACTOR_SRC1_COLOR
,
64 PIPE_BLENDFACTOR_SRC1_ALPHA
,
66 PIPE_BLENDFACTOR_ZERO
= 0x11,
67 PIPE_BLENDFACTOR_INV_SRC_COLOR
,
68 PIPE_BLENDFACTOR_INV_SRC_ALPHA
,
69 PIPE_BLENDFACTOR_INV_DST_ALPHA
,
70 PIPE_BLENDFACTOR_INV_DST_COLOR
,
72 PIPE_BLENDFACTOR_INV_CONST_COLOR
= 0x17,
73 PIPE_BLENDFACTOR_INV_CONST_ALPHA
,
74 PIPE_BLENDFACTOR_INV_SRC1_COLOR
,
75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA
,
78 enum pipe_blend_func
{
81 PIPE_BLEND_REVERSE_SUBTRACT
,
89 PIPE_LOGICOP_AND_INVERTED
,
90 PIPE_LOGICOP_COPY_INVERTED
,
91 PIPE_LOGICOP_AND_REVERSE
,
98 PIPE_LOGICOP_OR_INVERTED
,
100 PIPE_LOGICOP_OR_REVERSE
,
105 #define PIPE_MASK_R 0x1
106 #define PIPE_MASK_G 0x2
107 #define PIPE_MASK_B 0x4
108 #define PIPE_MASK_A 0x8
109 #define PIPE_MASK_RGBA 0xf
110 #define PIPE_MASK_Z 0x10
111 #define PIPE_MASK_S 0x20
112 #define PIPE_MASK_ZS 0x30
113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
117 * Inequality functions. Used for depth test, stencil compare, alpha
118 * test, shadow compare, etc.
120 enum pipe_compare_func
{
131 /** Polygon fill mode */
133 PIPE_POLYGON_MODE_FILL
,
134 PIPE_POLYGON_MODE_LINE
,
135 PIPE_POLYGON_MODE_POINT
,
138 /** Polygon face specification, eg for culling */
139 #define PIPE_FACE_NONE 0
140 #define PIPE_FACE_FRONT 1
141 #define PIPE_FACE_BACK 2
142 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
145 enum pipe_stencil_op
{
146 PIPE_STENCIL_OP_KEEP
,
147 PIPE_STENCIL_OP_ZERO
,
148 PIPE_STENCIL_OP_REPLACE
,
149 PIPE_STENCIL_OP_INCR
,
150 PIPE_STENCIL_OP_DECR
,
151 PIPE_STENCIL_OP_INCR_WRAP
,
152 PIPE_STENCIL_OP_DECR_WRAP
,
153 PIPE_STENCIL_OP_INVERT
,
157 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
159 enum pipe_texture_target
167 PIPE_TEXTURE_1D_ARRAY
,
168 PIPE_TEXTURE_2D_ARRAY
,
169 PIPE_TEXTURE_CUBE_ARRAY
,
170 PIPE_MAX_TEXTURE_TYPES
,
184 PIPE_TEX_WRAP_REPEAT
,
186 PIPE_TEX_WRAP_CLAMP_TO_EDGE
,
187 PIPE_TEX_WRAP_CLAMP_TO_BORDER
,
188 PIPE_TEX_WRAP_MIRROR_REPEAT
,
189 PIPE_TEX_WRAP_MIRROR_CLAMP
,
190 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
,
191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
,
194 /** Between mipmaps, ie mipfilter */
195 enum pipe_tex_mipfilter
{
196 PIPE_TEX_MIPFILTER_NEAREST
,
197 PIPE_TEX_MIPFILTER_LINEAR
,
198 PIPE_TEX_MIPFILTER_NONE
,
201 /** Within a mipmap, ie min/mag filter */
202 enum pipe_tex_filter
{
203 PIPE_TEX_FILTER_NEAREST
,
204 PIPE_TEX_FILTER_LINEAR
,
207 enum pipe_tex_compare
{
208 PIPE_TEX_COMPARE_NONE
,
209 PIPE_TEX_COMPARE_R_TO_TEXTURE
,
215 #define PIPE_CLEAR_DEPTH (1 << 0)
216 #define PIPE_CLEAR_STENCIL (1 << 1)
217 #define PIPE_CLEAR_COLOR0 (1 << 2)
218 #define PIPE_CLEAR_COLOR1 (1 << 3)
219 #define PIPE_CLEAR_COLOR2 (1 << 4)
220 #define PIPE_CLEAR_COLOR3 (1 << 5)
221 #define PIPE_CLEAR_COLOR4 (1 << 6)
222 #define PIPE_CLEAR_COLOR5 (1 << 7)
223 #define PIPE_CLEAR_COLOR6 (1 << 8)
224 #define PIPE_CLEAR_COLOR7 (1 << 9)
225 /** Combined flags */
226 /** All color buffers currently bound */
227 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
228 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
229 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
230 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
231 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
234 * Transfer object usage flags
236 enum pipe_transfer_usage
239 * Resource contents read back (or accessed directly) at transfer
242 PIPE_TRANSFER_READ
= (1 << 0),
245 * Resource contents will be written back at transfer_unmap
246 * time (or modified as a result of being accessed directly).
248 PIPE_TRANSFER_WRITE
= (1 << 1),
253 PIPE_TRANSFER_READ_WRITE
= PIPE_TRANSFER_READ
| PIPE_TRANSFER_WRITE
,
256 * The transfer should map the texture storage directly. The driver may
257 * return NULL if that isn't possible, and the state tracker needs to cope
258 * with that and use an alternative path without this flag.
260 * E.g. the state tracker could have a simpler path which maps textures and
261 * does read/modify/write cycles on them directly, and a more complicated
262 * path which uses minimal read and write transfers.
264 PIPE_TRANSFER_MAP_DIRECTLY
= (1 << 2),
267 * Discards the memory within the mapped region.
269 * It should not be used with PIPE_TRANSFER_READ.
272 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
274 PIPE_TRANSFER_DISCARD_RANGE
= (1 << 8),
277 * Fail if the resource cannot be mapped immediately.
280 * - Direct3D's D3DLOCK_DONOTWAIT flag.
281 * - Mesa's MESA_MAP_NOWAIT_BIT flag.
282 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
284 PIPE_TRANSFER_DONTBLOCK
= (1 << 9),
287 * Do not attempt to synchronize pending operations on the resource when mapping.
289 * It should not be used with PIPE_TRANSFER_READ.
292 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
293 * - Direct3D's D3DLOCK_NOOVERWRITE flag.
294 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
296 PIPE_TRANSFER_UNSYNCHRONIZED
= (1 << 10),
299 * Written ranges will be notified later with
300 * pipe_context::transfer_flush_region.
302 * It should not be used with PIPE_TRANSFER_READ.
305 * - pipe_context::transfer_flush_region
306 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
308 PIPE_TRANSFER_FLUSH_EXPLICIT
= (1 << 11),
311 * Discards all memory backing the resource.
313 * It should not be used with PIPE_TRANSFER_READ.
315 * This is equivalent to:
316 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
317 * - BufferData(NULL) on a GL buffer
318 * - Direct3D's D3DLOCK_DISCARD flag.
319 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
320 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
321 * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
323 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
= (1 << 12),
326 * Allows the resource to be used for rendering while mapped.
328 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
331 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
332 * must be called to ensure the device can see what the CPU has written.
334 PIPE_TRANSFER_PERSISTENT
= (1 << 13),
337 * If PERSISTENT is set, this ensures any writes done by the device are
338 * immediately visible to the CPU and vice versa.
340 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
343 PIPE_TRANSFER_COHERENT
= (1 << 14)
347 * Flags for the flush function.
349 enum pipe_flush_flags
351 PIPE_FLUSH_END_OF_FRAME
= (1 << 0),
352 PIPE_FLUSH_DEFERRED
= (1 << 1),
356 * Flags for pipe_context::dump_debug_state.
358 #define PIPE_DEBUG_DEVICE_IS_HUNG (1 << 0)
361 * Create a compute-only context. Use in pipe_screen::context_create.
362 * This disables draw, blit, and clear*, render_condition, and other graphics
363 * functions. Interop with other graphics contexts is still allowed.
364 * This allows scheduling jobs on a compute-only hardware command queue that
365 * can run in parallel with graphics without stalling it.
367 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0)
370 * Gather debug information and expect that pipe_context::dump_debug_state
371 * will be called. Use in pipe_screen::context_create.
373 #define PIPE_CONTEXT_DEBUG (1 << 1)
376 * Whether out-of-bounds shader loads must return zero and out-of-bounds
377 * shader stores must be dropped.
379 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
382 * Flags for pipe_context::memory_barrier.
384 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0)
385 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1)
386 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2)
387 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3)
388 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4)
389 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5)
390 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6)
391 #define PIPE_BARRIER_TEXTURE (1 << 7)
392 #define PIPE_BARRIER_IMAGE (1 << 8)
393 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9)
394 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10)
395 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
396 #define PIPE_BARRIER_ALL ((1 << 12) - 1)
399 * Resource binding flags -- state tracker must specify in advance all
400 * the ways a resource might be used.
402 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */
403 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */
404 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */
405 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */
406 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */
407 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */
408 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */
409 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */
410 #define PIPE_BIND_TRANSFER_WRITE (1 << 8) /* transfer_map */
411 #define PIPE_BIND_TRANSFER_READ (1 << 9) /* transfer_map */
412 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */
413 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */
414 #define PIPE_BIND_CUSTOM (1 << 12) /* state-tracker/winsys usages */
415 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */
416 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */
417 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */
418 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */
419 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */
420 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */
423 * The first two flags above were previously part of the amorphous
424 * TEXTURE_USAGE, most of which are now descriptions of the ways a
425 * particular texture can be bound to the gallium pipeline. The two flags
426 * below do not fit within that and probably need to be migrated to some
429 * It seems like scanout is used by the Xorg state tracker to ask for
430 * a texture suitable for actual scanout (hence the name), which
431 * implies extra layout constraints on some hardware. It may also
432 * have some special meaning regarding mouse cursor images.
434 * The shared flag is quite underspecified, but certainly isn't a
435 * binding flag - it seems more like a message to the winsys to create
436 * a shareable allocation.
438 * The third flag has been added to be able to force textures to be created
439 * in linear mode (no tiling).
441 #define PIPE_BIND_SCANOUT (1 << 19) /* */
442 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */
443 #define PIPE_BIND_LINEAR (1 << 21)
447 * Flags for the driver about resource behaviour:
449 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
450 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
451 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
452 #define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
455 * Hint about the expected lifecycle of a resource.
456 * Sorted according to GPU vs CPU access.
458 enum pipe_resource_usage
{
459 PIPE_USAGE_DEFAULT
, /* fast GPU access */
460 PIPE_USAGE_IMMUTABLE
, /* fast GPU access, immutable */
461 PIPE_USAGE_DYNAMIC
, /* uploaded data is used multiple times */
462 PIPE_USAGE_STREAM
, /* uploaded data is used once */
463 PIPE_USAGE_STAGING
, /* fast CPU access */
469 enum pipe_shader_type
{
471 PIPE_SHADER_FRAGMENT
,
472 PIPE_SHADER_GEOMETRY
,
473 PIPE_SHADER_TESS_CTRL
,
474 PIPE_SHADER_TESS_EVAL
,
482 enum pipe_prim_type
{
486 PIPE_PRIM_LINE_STRIP
,
488 PIPE_PRIM_TRIANGLE_STRIP
,
489 PIPE_PRIM_TRIANGLE_FAN
,
491 PIPE_PRIM_QUAD_STRIP
,
493 PIPE_PRIM_LINES_ADJACENCY
,
494 PIPE_PRIM_LINE_STRIP_ADJACENCY
,
495 PIPE_PRIM_TRIANGLES_ADJACENCY
,
496 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
,
502 * Tessellator spacing types
504 enum pipe_tess_spacing
{
505 PIPE_TESS_SPACING_FRACTIONAL_ODD
,
506 PIPE_TESS_SPACING_FRACTIONAL_EVEN
,
507 PIPE_TESS_SPACING_EQUAL
,
513 enum pipe_query_type
{
514 PIPE_QUERY_OCCLUSION_COUNTER
,
515 PIPE_QUERY_OCCLUSION_PREDICATE
,
516 PIPE_QUERY_TIMESTAMP
,
517 PIPE_QUERY_TIMESTAMP_DISJOINT
,
518 PIPE_QUERY_TIME_ELAPSED
,
519 PIPE_QUERY_PRIMITIVES_GENERATED
,
520 PIPE_QUERY_PRIMITIVES_EMITTED
,
521 PIPE_QUERY_SO_STATISTICS
,
522 PIPE_QUERY_SO_OVERFLOW_PREDICATE
,
523 PIPE_QUERY_GPU_FINISHED
,
524 PIPE_QUERY_PIPELINE_STATISTICS
,
526 /* start of driver queries, see pipe_screen::get_driver_query_info */
527 PIPE_QUERY_DRIVER_SPECIFIC
= 256,
531 * Conditional rendering modes
533 enum pipe_render_cond_flag
{
534 PIPE_RENDER_COND_WAIT
,
535 PIPE_RENDER_COND_NO_WAIT
,
536 PIPE_RENDER_COND_BY_REGION_WAIT
,
537 PIPE_RENDER_COND_BY_REGION_NO_WAIT
,
541 * Point sprite coord modes
543 enum pipe_sprite_coord_mode
{
544 PIPE_SPRITE_COORD_UPPER_LEFT
,
545 PIPE_SPRITE_COORD_LOWER_LEFT
,
549 * Texture & format swizzles
559 PIPE_SWIZZLE_MAX
, /**< Number of enums counter (must be last) */
562 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
566 * Device reset status.
568 enum pipe_reset_status
571 PIPE_GUILTY_CONTEXT_RESET
,
572 PIPE_INNOCENT_CONTEXT_RESET
,
573 PIPE_UNKNOWN_CONTEXT_RESET
,
578 * resource_get_handle flags.
580 /* Requires pipe_context::flush_resource before external use. */
581 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
582 /* Expected external use of the resource: */
583 #define PIPE_HANDLE_USAGE_READ (1 << 1)
584 #define PIPE_HANDLE_USAGE_WRITE (1 << 2)
585 #define PIPE_HANDLE_USAGE_READ_WRITE (PIPE_HANDLE_USAGE_READ | \
586 PIPE_HANDLE_USAGE_WRITE)
589 * pipe_image_view access flags.
591 #define PIPE_IMAGE_ACCESS_READ (1 << 0)
592 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1)
593 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
594 PIPE_IMAGE_ACCESS_WRITE)
597 * Implementation capabilities/limits which are queried through
598 * pipe_screen::get_param()
602 PIPE_CAP_NPOT_TEXTURES
,
603 PIPE_CAP_TWO_SIDED_STENCIL
,
604 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
,
605 PIPE_CAP_ANISOTROPIC_FILTER
,
606 PIPE_CAP_POINT_SPRITE
,
607 PIPE_CAP_MAX_RENDER_TARGETS
,
608 PIPE_CAP_OCCLUSION_QUERY
,
609 PIPE_CAP_QUERY_TIME_ELAPSED
,
610 PIPE_CAP_TEXTURE_SHADOW_MAP
,
611 PIPE_CAP_TEXTURE_SWIZZLE
,
612 PIPE_CAP_MAX_TEXTURE_2D_LEVELS
,
613 PIPE_CAP_MAX_TEXTURE_3D_LEVELS
,
614 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
,
615 PIPE_CAP_TEXTURE_MIRROR_CLAMP
,
616 PIPE_CAP_BLEND_EQUATION_SEPARATE
,
618 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
,
619 PIPE_CAP_PRIMITIVE_RESTART
,
620 /** blend enables and write masks per rendertarget */
621 PIPE_CAP_INDEP_BLEND_ENABLE
,
622 /** different blend funcs per rendertarget */
623 PIPE_CAP_INDEP_BLEND_FUNC
,
624 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
,
625 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
,
626 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
,
627 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
,
628 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
,
629 PIPE_CAP_DEPTH_CLIP_DISABLE
,
630 PIPE_CAP_SHADER_STENCIL_EXPORT
,
631 PIPE_CAP_TGSI_INSTANCEID
,
632 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
,
633 PIPE_CAP_FRAGMENT_COLOR_CLAMPED
,
634 PIPE_CAP_MIXED_COLORBUFFER_FORMATS
,
635 PIPE_CAP_SEAMLESS_CUBE_MAP
,
636 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
,
637 PIPE_CAP_MIN_TEXEL_OFFSET
,
638 PIPE_CAP_MAX_TEXEL_OFFSET
,
639 PIPE_CAP_CONDITIONAL_RENDER
,
640 PIPE_CAP_TEXTURE_BARRIER
,
641 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
,
642 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
,
643 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
,
644 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
,
645 PIPE_CAP_VERTEX_COLOR_UNCLAMPED
,
646 PIPE_CAP_VERTEX_COLOR_CLAMPED
,
647 PIPE_CAP_GLSL_FEATURE_LEVEL
,
648 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
,
649 PIPE_CAP_USER_VERTEX_BUFFERS
,
650 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
,
651 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
,
652 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
,
654 PIPE_CAP_USER_INDEX_BUFFERS
,
655 PIPE_CAP_USER_CONSTANT_BUFFERS
,
656 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
,
657 PIPE_CAP_START_INSTANCE
,
658 PIPE_CAP_QUERY_TIMESTAMP
,
659 PIPE_CAP_TEXTURE_MULTISAMPLE
,
660 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
,
661 PIPE_CAP_CUBE_MAP_ARRAY
,
662 PIPE_CAP_TEXTURE_BUFFER_OBJECTS
,
663 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
,
664 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
,
665 PIPE_CAP_TGSI_TEXCOORD
,
666 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
,
667 PIPE_CAP_QUERY_PIPELINE_STATISTICS
,
668 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
,
669 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
,
670 PIPE_CAP_MAX_VIEWPORTS
,
672 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
,
673 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
,
674 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
,
675 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
,
676 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
,
677 PIPE_CAP_TEXTURE_GATHER_SM5
,
678 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
,
679 PIPE_CAP_FAKE_SW_MSAA
,
680 PIPE_CAP_TEXTURE_QUERY_LOD
,
681 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
,
682 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
,
683 PIPE_CAP_SAMPLE_SHADING
,
684 PIPE_CAP_TEXTURE_GATHER_OFFSETS
,
685 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
,
686 PIPE_CAP_MAX_VERTEX_STREAMS
,
687 PIPE_CAP_DRAW_INDIRECT
,
688 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
,
691 PIPE_CAP_ACCELERATED
,
692 PIPE_CAP_VIDEO_MEMORY
,
694 PIPE_CAP_CONDITIONAL_RENDER_INVERTED
,
695 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
,
696 PIPE_CAP_SAMPLER_VIEW_TARGET
,
698 PIPE_CAP_VERTEXID_NOBASE
,
699 PIPE_CAP_POLYGON_OFFSET_CLAMP
,
700 PIPE_CAP_MULTISAMPLE_Z_RESOLVE
,
701 PIPE_CAP_RESOURCE_FROM_USER_MEMORY
,
702 PIPE_CAP_DEVICE_RESET_STATUS_QUERY
,
703 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
,
704 PIPE_CAP_TEXTURE_FLOAT_LINEAR
,
705 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
,
706 PIPE_CAP_DEPTH_BOUNDS_TEST
,
708 PIPE_CAP_FORCE_PERSAMPLE_INTERP
,
709 PIPE_CAP_SHAREABLE_SHADERS
,
710 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
,
711 PIPE_CAP_CLEAR_TEXTURE
,
712 PIPE_CAP_DRAW_PARAMETERS
,
713 PIPE_CAP_TGSI_PACK_HALF_FLOAT
,
714 PIPE_CAP_MULTI_DRAW_INDIRECT
,
715 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
,
716 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
,
717 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
,
718 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
,
719 PIPE_CAP_INVALIDATE_BUFFER
,
720 PIPE_CAP_GENERATE_MIPMAP
,
721 PIPE_CAP_STRING_MARKER
,
722 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
,
723 PIPE_CAP_QUERY_BUFFER_OBJECT
,
724 PIPE_CAP_QUERY_MEMORY_INFO
,
728 PIPE_CAP_PCI_FUNCTION
,
729 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
,
730 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
,
731 PIPE_CAP_CULL_DISTANCE
,
732 PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
,
734 PIPE_CAP_MAX_WINDOW_RECTANGLES
,
735 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
,
736 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
,
739 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
740 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
744 PIPE_ENDIAN_LITTLE
= 0,
746 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
747 PIPE_ENDIAN_NATIVE
= PIPE_ENDIAN_LITTLE
748 #elif defined(PIPE_ARCH_BIG_ENDIAN)
749 PIPE_ENDIAN_NATIVE
= PIPE_ENDIAN_BIG
754 * Implementation limits which are queried through
755 * pipe_screen::get_paramf()
759 PIPE_CAPF_MAX_LINE_WIDTH
,
760 PIPE_CAPF_MAX_LINE_WIDTH_AA
,
761 PIPE_CAPF_MAX_POINT_WIDTH
,
762 PIPE_CAPF_MAX_POINT_WIDTH_AA
,
763 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
,
764 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
,
765 PIPE_CAPF_GUARD_BAND_LEFT
,
766 PIPE_CAPF_GUARD_BAND_TOP
,
767 PIPE_CAPF_GUARD_BAND_RIGHT
,
768 PIPE_CAPF_GUARD_BAND_BOTTOM
771 /** Shader caps not specific to any single stage */
774 PIPE_SHADER_CAP_MAX_INSTRUCTIONS
, /* if 0, it means the stage is unsupported */
775 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
,
776 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
,
777 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
,
778 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
,
779 PIPE_SHADER_CAP_MAX_INPUTS
,
780 PIPE_SHADER_CAP_MAX_OUTPUTS
,
781 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
,
782 PIPE_SHADER_CAP_MAX_CONST_BUFFERS
,
783 PIPE_SHADER_CAP_MAX_TEMPS
,
784 PIPE_SHADER_CAP_MAX_PREDS
,
786 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
,
787 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
,
788 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
,
789 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
,
790 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
,
791 PIPE_SHADER_CAP_SUBROUTINES
, /* BGNSUB, ENDSUB, CAL, RET */
792 PIPE_SHADER_CAP_INTEGERS
,
793 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
,
794 PIPE_SHADER_CAP_PREFERRED_IR
,
795 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
,
796 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
,
797 PIPE_SHADER_CAP_DOUBLES
,
798 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
, /* all rounding modes */
799 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
,
800 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
,
801 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
,
802 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
,
803 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
,
804 PIPE_SHADER_CAP_SUPPORTED_IRS
,
805 PIPE_SHADER_CAP_MAX_SHADER_IMAGES
,
809 * Shader intermediate representation.
811 * Note that if the driver requests something other than TGSI, it must
812 * always be prepared to receive TGSI in addition to its preferred IR.
813 * If the driver requests TGSI as its preferred IR, it will *always*
816 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
817 * state trackers that only understand TGSI.
821 PIPE_SHADER_IR_TGSI
= 0,
823 PIPE_SHADER_IR_NATIVE
,
828 * Compute-specific implementation capability. They can be queried
829 * using pipe_screen::get_compute_param.
831 enum pipe_compute_cap
833 PIPE_COMPUTE_CAP_IR_TARGET
,
834 PIPE_COMPUTE_CAP_GRID_DIMENSION
,
835 PIPE_COMPUTE_CAP_MAX_GRID_SIZE
,
836 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
,
837 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
838 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
,
839 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
,
840 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
,
841 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
,
842 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
843 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
,
844 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
,
845 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
,
846 PIPE_COMPUTE_CAP_SUBGROUP_SIZE
850 * Composite query types
854 * Query result for PIPE_QUERY_SO_STATISTICS.
856 struct pipe_query_data_so_statistics
858 uint64_t num_primitives_written
;
859 uint64_t primitives_storage_needed
;
863 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
865 struct pipe_query_data_timestamp_disjoint
872 * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
874 struct pipe_query_data_pipeline_statistics
876 uint64_t ia_vertices
; /**< Num vertices read by the vertex fetcher. */
877 uint64_t ia_primitives
; /**< Num primitives read by the vertex fetcher. */
878 uint64_t vs_invocations
; /**< Num vertex shader invocations. */
879 uint64_t gs_invocations
; /**< Num geometry shader invocations. */
880 uint64_t gs_primitives
; /**< Num primitives output by a geometry shader. */
881 uint64_t c_invocations
; /**< Num primitives sent to the rasterizer. */
882 uint64_t c_primitives
; /**< Num primitives that were rendered. */
883 uint64_t ps_invocations
; /**< Num pixel shader invocations. */
884 uint64_t hs_invocations
; /**< Num hull shader invocations. */
885 uint64_t ds_invocations
; /**< Num domain shader invocations. */
886 uint64_t cs_invocations
; /**< Num compute shader invocations. */
892 union pipe_numeric_type_union
900 * Query result (returned by pipe_context::get_query_result).
902 union pipe_query_result
904 /* PIPE_QUERY_OCCLUSION_PREDICATE */
905 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
906 /* PIPE_QUERY_GPU_FINISHED */
909 /* PIPE_QUERY_OCCLUSION_COUNTER */
910 /* PIPE_QUERY_TIMESTAMP */
911 /* PIPE_QUERY_TIME_ELAPSED */
912 /* PIPE_QUERY_PRIMITIVES_GENERATED */
913 /* PIPE_QUERY_PRIMITIVES_EMITTED */
914 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
915 /* PIPE_DRIVER_QUERY_TYPE_BYTES */
916 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
917 /* PIPE_DRIVER_QUERY_TYPE_HZ */
920 /* PIPE_DRIVER_QUERY_TYPE_UINT */
923 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
924 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
927 /* PIPE_QUERY_SO_STATISTICS */
928 struct pipe_query_data_so_statistics so_statistics
;
930 /* PIPE_QUERY_TIMESTAMP_DISJOINT */
931 struct pipe_query_data_timestamp_disjoint timestamp_disjoint
;
933 /* PIPE_QUERY_PIPELINE_STATISTICS */
934 struct pipe_query_data_pipeline_statistics pipeline_statistics
;
936 /* batch queries (variable length) */
937 union pipe_numeric_type_union batch
[1];
940 enum pipe_query_value_type
948 union pipe_color_union
955 enum pipe_driver_query_type
957 PIPE_DRIVER_QUERY_TYPE_UINT64
,
958 PIPE_DRIVER_QUERY_TYPE_UINT
,
959 PIPE_DRIVER_QUERY_TYPE_FLOAT
,
960 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE
,
961 PIPE_DRIVER_QUERY_TYPE_BYTES
,
962 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
,
963 PIPE_DRIVER_QUERY_TYPE_HZ
,
966 /* Whether an average value per frame or a cumulative value should be
969 enum pipe_driver_query_result_type
971 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE
,
972 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
,
976 * Some hardware requires some hardware-specific queries to be submitted
977 * as batched queries. The corresponding query objects are created using
978 * create_batch_query, and at most one such query may be active at
981 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0)
983 /* Do not list this query in the HUD. */
984 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
986 struct pipe_driver_query_info
989 unsigned query_type
; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
990 union pipe_numeric_type_union max_value
; /* max value that can be returned */
991 enum pipe_driver_query_type type
;
992 enum pipe_driver_query_result_type result_type
;
997 struct pipe_driver_query_group_info
1000 unsigned max_active_queries
;
1001 unsigned num_queries
;
1004 enum pipe_debug_type
1006 PIPE_DEBUG_TYPE_OUT_OF_MEMORY
= 1,
1007 PIPE_DEBUG_TYPE_ERROR
,
1008 PIPE_DEBUG_TYPE_SHADER_INFO
,
1009 PIPE_DEBUG_TYPE_PERF_INFO
,
1010 PIPE_DEBUG_TYPE_INFO
,
1011 PIPE_DEBUG_TYPE_FALLBACK
,
1012 PIPE_DEBUG_TYPE_CONFORMANCE
,