src/gallium/include/pipe/p_defines.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef PIPE_DEFINES_H
  29 #define PIPE_DEFINES_H
  30
  31 #include "p_compiler.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /**
  38  * Gallium error codes.
  39  *
  40  * - A zero value always means success.
  41  * - A negative value always means failure.
  42  * - The meaning of a positive value is function dependent.
  43  */
  44 enum pipe_error
  45 {
  46    PIPE_OK = 0,
  47    PIPE_ERROR = -1,    /**< Generic error */
  48    PIPE_ERROR_BAD_INPUT = -2,
  49    PIPE_ERROR_OUT_OF_MEMORY = -3,
  50    PIPE_ERROR_RETRY = -4
  51    /* TODO */
  52 };
  53
  54 enum pipe_blendfactor {
  55    PIPE_BLENDFACTOR_ONE = 1,
  56    PIPE_BLENDFACTOR_SRC_COLOR,
  57    PIPE_BLENDFACTOR_SRC_ALPHA,
  58    PIPE_BLENDFACTOR_DST_ALPHA,
  59    PIPE_BLENDFACTOR_DST_COLOR,
  60    PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE,
  61    PIPE_BLENDFACTOR_CONST_COLOR,
  62    PIPE_BLENDFACTOR_CONST_ALPHA,
  63    PIPE_BLENDFACTOR_SRC1_COLOR,
  64    PIPE_BLENDFACTOR_SRC1_ALPHA,
  65
  66    PIPE_BLENDFACTOR_ZERO = 0x11,
  67    PIPE_BLENDFACTOR_INV_SRC_COLOR,
  68    PIPE_BLENDFACTOR_INV_SRC_ALPHA,
  69    PIPE_BLENDFACTOR_INV_DST_ALPHA,
  70    PIPE_BLENDFACTOR_INV_DST_COLOR,
  71
  72    PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17,
  73    PIPE_BLENDFACTOR_INV_CONST_ALPHA,
  74    PIPE_BLENDFACTOR_INV_SRC1_COLOR,
  75    PIPE_BLENDFACTOR_INV_SRC1_ALPHA,
  76 };
  77
  78 enum pipe_blend_func {
  79    PIPE_BLEND_ADD,
  80    PIPE_BLEND_SUBTRACT,
  81    PIPE_BLEND_REVERSE_SUBTRACT,
  82    PIPE_BLEND_MIN,
  83    PIPE_BLEND_MAX,
  84 };
  85
  86 enum pipe_logicop {
  87    PIPE_LOGICOP_CLEAR,
  88    PIPE_LOGICOP_NOR,
  89    PIPE_LOGICOP_AND_INVERTED,
  90    PIPE_LOGICOP_COPY_INVERTED,
  91    PIPE_LOGICOP_AND_REVERSE,
  92    PIPE_LOGICOP_INVERT,
  93    PIPE_LOGICOP_XOR,
  94    PIPE_LOGICOP_NAND,
  95    PIPE_LOGICOP_AND,
  96    PIPE_LOGICOP_EQUIV,
  97    PIPE_LOGICOP_NOOP,
  98    PIPE_LOGICOP_OR_INVERTED,
  99    PIPE_LOGICOP_COPY,
 100    PIPE_LOGICOP_OR_REVERSE,
 101    PIPE_LOGICOP_OR,
 102    PIPE_LOGICOP_SET,
 103 };
 104
 105 #define PIPE_MASK_R  0x1
 106 #define PIPE_MASK_G  0x2
 107 #define PIPE_MASK_B  0x4
 108 #define PIPE_MASK_A  0x8
 109 #define PIPE_MASK_RGBA 0xf
 110 #define PIPE_MASK_Z  0x10
 111 #define PIPE_MASK_S  0x20
 112 #define PIPE_MASK_ZS 0x30
 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
 114
 115
 116 /**
 117  * Inequality functions.  Used for depth test, stencil compare, alpha
 118  * test, shadow compare, etc.
 119  */
 120 enum pipe_compare_func {
 121    PIPE_FUNC_NEVER,
 122    PIPE_FUNC_LESS,
 123    PIPE_FUNC_EQUAL,
 124    PIPE_FUNC_LEQUAL,
 125    PIPE_FUNC_GREATER,
 126    PIPE_FUNC_NOTEQUAL,
 127    PIPE_FUNC_GEQUAL,
 128    PIPE_FUNC_ALWAYS,
 129 };
 130
 131 /** Polygon fill mode */
 132 enum {
 133    PIPE_POLYGON_MODE_FILL,
 134    PIPE_POLYGON_MODE_LINE,
 135    PIPE_POLYGON_MODE_POINT,
 136 };
 137
 138 /** Polygon face specification, eg for culling */
 139 #define PIPE_FACE_NONE           0
 140 #define PIPE_FACE_FRONT          1
 141 #define PIPE_FACE_BACK           2
 142 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
 143
 144 /** Stencil ops */
 145 enum pipe_stencil_op {
 146    PIPE_STENCIL_OP_KEEP,
 147    PIPE_STENCIL_OP_ZERO,
 148    PIPE_STENCIL_OP_REPLACE,
 149    PIPE_STENCIL_OP_INCR,
 150    PIPE_STENCIL_OP_DECR,
 151    PIPE_STENCIL_OP_INCR_WRAP,
 152    PIPE_STENCIL_OP_DECR_WRAP,
 153    PIPE_STENCIL_OP_INVERT,
 154 };
 155
 156 /** Texture types.
 157  * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
 158  */
 159 enum pipe_texture_target
 160 {
 161    PIPE_BUFFER,
 162    PIPE_TEXTURE_1D,
 163    PIPE_TEXTURE_2D,
 164    PIPE_TEXTURE_3D,
 165    PIPE_TEXTURE_CUBE,
 166    PIPE_TEXTURE_RECT,
 167    PIPE_TEXTURE_1D_ARRAY,
 168    PIPE_TEXTURE_2D_ARRAY,
 169    PIPE_TEXTURE_CUBE_ARRAY,
 170    PIPE_MAX_TEXTURE_TYPES,
 171 };
 172
 173 enum pipe_tex_face {
 174    PIPE_TEX_FACE_POS_X,
 175    PIPE_TEX_FACE_NEG_X,
 176    PIPE_TEX_FACE_POS_Y,
 177    PIPE_TEX_FACE_NEG_Y,
 178    PIPE_TEX_FACE_POS_Z,
 179    PIPE_TEX_FACE_NEG_Z,
 180    PIPE_TEX_FACE_MAX,
 181 };
 182
 183 enum pipe_tex_wrap {
 184    PIPE_TEX_WRAP_REPEAT,
 185    PIPE_TEX_WRAP_CLAMP,
 186    PIPE_TEX_WRAP_CLAMP_TO_EDGE,
 187    PIPE_TEX_WRAP_CLAMP_TO_BORDER,
 188    PIPE_TEX_WRAP_MIRROR_REPEAT,
 189    PIPE_TEX_WRAP_MIRROR_CLAMP,
 190    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE,
 191    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER,
 192 };
 193
 194 /** Between mipmaps, ie mipfilter */
 195 enum pipe_tex_mipfilter {
 196    PIPE_TEX_MIPFILTER_NEAREST,
 197    PIPE_TEX_MIPFILTER_LINEAR,
 198    PIPE_TEX_MIPFILTER_NONE,
 199 };
 200
 201 /** Within a mipmap, ie min/mag filter */
 202 enum pipe_tex_filter {
 203    PIPE_TEX_FILTER_NEAREST,
 204    PIPE_TEX_FILTER_LINEAR,
 205 };
 206
 207 enum pipe_tex_compare {
 208    PIPE_TEX_COMPARE_NONE,
 209    PIPE_TEX_COMPARE_R_TO_TEXTURE,
 210 };
 211
 212 /**
 213  * Clear buffer bits
 214  */
 215 #define PIPE_CLEAR_DEPTH        (1 << 0)
 216 #define PIPE_CLEAR_STENCIL      (1 << 1)
 217 #define PIPE_CLEAR_COLOR0       (1 << 2)
 218 #define PIPE_CLEAR_COLOR1       (1 << 3)
 219 #define PIPE_CLEAR_COLOR2       (1 << 4)
 220 #define PIPE_CLEAR_COLOR3       (1 << 5)
 221 #define PIPE_CLEAR_COLOR4       (1 << 6)
 222 #define PIPE_CLEAR_COLOR5       (1 << 7)
 223 #define PIPE_CLEAR_COLOR6       (1 << 8)
 224 #define PIPE_CLEAR_COLOR7       (1 << 9)
 225 /** Combined flags */
 226 /** All color buffers currently bound */
 227 #define PIPE_CLEAR_COLOR        (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
 228                                  PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
 229                                  PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
 230                                  PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
 231 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
 232
 233 /**
 234  * Transfer object usage flags
 235  */
 236 enum pipe_transfer_usage
 237 {
 238    /**
 239     * Resource contents read back (or accessed directly) at transfer
 240     * create time.
 241     */
 242    PIPE_TRANSFER_READ = (1 << 0),
 243
 244    /**
 245     * Resource contents will be written back at transfer_unmap
 246     * time (or modified as a result of being accessed directly).
 247     */
 248    PIPE_TRANSFER_WRITE = (1 << 1),
 249
 250    /**
 251     * Read/modify/write
 252     */
 253    PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
 254
 255    /**
 256     * The transfer should map the texture storage directly. The driver may
 257     * return NULL if that isn't possible, and the state tracker needs to cope
 258     * with that and use an alternative path without this flag.
 259     *
 260     * E.g. the state tracker could have a simpler path which maps textures and
 261     * does read/modify/write cycles on them directly, and a more complicated
 262     * path which uses minimal read and write transfers.
 263     */
 264    PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
 265
 266    /**
 267     * Discards the memory within the mapped region.
 268     *
 269     * It should not be used with PIPE_TRANSFER_READ.
 270     *
 271     * See also:
 272     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
 273     */
 274    PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
 275
 276    /**
 277     * Fail if the resource cannot be mapped immediately.
 278     *
 279     * See also:
 280     * - Direct3D's D3DLOCK_DONOTWAIT flag.
 281     * - Mesa's MESA_MAP_NOWAIT_BIT flag.
 282     * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
 283     */
 284    PIPE_TRANSFER_DONTBLOCK = (1 << 9),
 285
 286    /**
 287     * Do not attempt to synchronize pending operations on the resource when mapping.
 288     *
 289     * It should not be used with PIPE_TRANSFER_READ.
 290     *
 291     * See also:
 292     * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
 293     * - Direct3D's D3DLOCK_NOOVERWRITE flag.
 294     * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
 295     */
 296    PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
 297
 298    /**
 299     * Written ranges will be notified later with
 300     * pipe_context::transfer_flush_region.
 301     *
 302     * It should not be used with PIPE_TRANSFER_READ.
 303     *
 304     * See also:
 305     * - pipe_context::transfer_flush_region
 306     * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
 307     */
 308    PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
 309
 310    /**
 311     * Discards all memory backing the resource.
 312     *
 313     * It should not be used with PIPE_TRANSFER_READ.
 314     *
 315     * This is equivalent to:
 316     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
 317     * - BufferData(NULL) on a GL buffer
 318     * - Direct3D's D3DLOCK_DISCARD flag.
 319     * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
 320     * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
 321     * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
 322     */
 323    PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
 324
 325    /**
 326     * Allows the resource to be used for rendering while mapped.
 327     *
 328     * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
 329     * the resource.
 330     *
 331     * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
 332     * must be called to ensure the device can see what the CPU has written.
 333     */
 334    PIPE_TRANSFER_PERSISTENT = (1 << 13),
 335
 336    /**
 337     * If PERSISTENT is set, this ensures any writes done by the device are
 338     * immediately visible to the CPU and vice versa.
 339     *
 340     * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
 341     * the resource.
 342     */
 343    PIPE_TRANSFER_COHERENT = (1 << 14)
 344 };
 345
 346 /**
 347  * Flags for the flush function.
 348  */
 349 enum pipe_flush_flags
 350 {
 351    PIPE_FLUSH_END_OF_FRAME = (1 << 0),
 352    PIPE_FLUSH_DEFERRED = (1 << 1),
 353    PIPE_FLUSH_FENCE_FD = (1 << 2),
 354 };
 355
 356 /**
 357  * Flags for pipe_context::dump_debug_state.
 358  */
 359 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS    (1 << 0)
 360 #define PIPE_DUMP_CURRENT_STATES             (1 << 1)
 361 #define PIPE_DUMP_CURRENT_SHADERS            (1 << 2)
 362 #define PIPE_DUMP_LAST_COMMAND_BUFFER        (1 << 3)
 363
 364 /**
 365  * Create a compute-only context. Use in pipe_screen::context_create.
 366  * This disables draw, blit, and clear*, render_condition, and other graphics
 367  * functions. Interop with other graphics contexts is still allowed.
 368  * This allows scheduling jobs on a compute-only hardware command queue that
 369  * can run in parallel with graphics without stalling it.
 370  */
 371 #define PIPE_CONTEXT_COMPUTE_ONLY      (1 << 0)
 372
 373 /**
 374  * Gather debug information and expect that pipe_context::dump_debug_state
 375  * will be called. Use in pipe_screen::context_create.
 376  */
 377 #define PIPE_CONTEXT_DEBUG             (1 << 1)
 378
 379 /**
 380  * Whether out-of-bounds shader loads must return zero and out-of-bounds
 381  * shader stores must be dropped.
 382  */
 383 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
 384
 385 /**
 386  * Flags for pipe_context::memory_barrier.
 387  */
 388 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
 389 #define PIPE_BARRIER_SHADER_BUFFER     (1 << 1)
 390 #define PIPE_BARRIER_QUERY_BUFFER      (1 << 2)
 391 #define PIPE_BARRIER_VERTEX_BUFFER     (1 << 3)
 392 #define PIPE_BARRIER_INDEX_BUFFER      (1 << 4)
 393 #define PIPE_BARRIER_CONSTANT_BUFFER   (1 << 5)
 394 #define PIPE_BARRIER_INDIRECT_BUFFER   (1 << 6)
 395 #define PIPE_BARRIER_TEXTURE           (1 << 7)
 396 #define PIPE_BARRIER_IMAGE             (1 << 8)
 397 #define PIPE_BARRIER_FRAMEBUFFER       (1 << 9)
 398 #define PIPE_BARRIER_STREAMOUT_BUFFER  (1 << 10)
 399 #define PIPE_BARRIER_GLOBAL_BUFFER     (1 << 11)
 400 #define PIPE_BARRIER_ALL               ((1 << 12) - 1)
 401
 402 /**
 403  * Flags for pipe_context::texture_barrier.
 404  */
 405 #define PIPE_TEXTURE_BARRIER_SAMPLER      (1 << 0)
 406 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER  (1 << 1)
 407
 408 /**
 409  * Resource binding flags -- state tracker must specify in advance all
 410  * the ways a resource might be used.
 411  */
 412 #define PIPE_BIND_DEPTH_STENCIL        (1 << 0) /* create_surface */
 413 #define PIPE_BIND_RENDER_TARGET        (1 << 1) /* create_surface */
 414 #define PIPE_BIND_BLENDABLE            (1 << 2) /* create_surface */
 415 #define PIPE_BIND_SAMPLER_VIEW         (1 << 3) /* create_sampler_view */
 416 #define PIPE_BIND_VERTEX_BUFFER        (1 << 4) /* set_vertex_buffers */
 417 #define PIPE_BIND_INDEX_BUFFER         (1 << 5) /* draw_elements */
 418 #define PIPE_BIND_CONSTANT_BUFFER      (1 << 6) /* set_constant_buffer */
 419 #define PIPE_BIND_DISPLAY_TARGET       (1 << 7) /* flush_front_buffer */
 420 /* gap */
 421 #define PIPE_BIND_STREAM_OUTPUT        (1 << 10) /* set_stream_output_buffers */
 422 #define PIPE_BIND_CURSOR               (1 << 11) /* mouse cursor */
 423 #define PIPE_BIND_CUSTOM               (1 << 12) /* state-tracker/winsys usages */
 424 #define PIPE_BIND_GLOBAL               (1 << 13) /* set_global_binding */
 425 #define PIPE_BIND_SHADER_BUFFER        (1 << 14) /* set_shader_buffers */
 426 #define PIPE_BIND_SHADER_IMAGE         (1 << 15) /* set_shader_images */
 427 #define PIPE_BIND_COMPUTE_RESOURCE     (1 << 16) /* set_compute_resources */
 428 #define PIPE_BIND_COMMAND_ARGS_BUFFER  (1 << 17) /* pipe_draw_info.indirect */
 429 #define PIPE_BIND_QUERY_BUFFER         (1 << 18) /* get_query_result_resource */
 430
 431 /**
 432  * The first two flags above were previously part of the amorphous
 433  * TEXTURE_USAGE, most of which are now descriptions of the ways a
 434  * particular texture can be bound to the gallium pipeline.  The two flags
 435  * below do not fit within that and probably need to be migrated to some
 436  * other place.
 437  *
 438  * It seems like scanout is used by the Xorg state tracker to ask for
 439  * a texture suitable for actual scanout (hence the name), which
 440  * implies extra layout constraints on some hardware.  It may also
 441  * have some special meaning regarding mouse cursor images.
 442  *
 443  * The shared flag is quite underspecified, but certainly isn't a
 444  * binding flag - it seems more like a message to the winsys to create
 445  * a shareable allocation.
 446  *
 447  * The third flag has been added to be able to force textures to be created
 448  * in linear mode (no tiling).
 449  */
 450 #define PIPE_BIND_SCANOUT     (1 << 19) /*  */
 451 #define PIPE_BIND_SHARED      (1 << 20) /* get_texture_handle ??? */
 452 #define PIPE_BIND_LINEAR      (1 << 21)
 453
 454
 455 /**
 456  * Flags for the driver about resource behaviour:
 457  */
 458 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
 459 #define PIPE_RESOURCE_FLAG_MAP_COHERENT   (1 << 1)
 460 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
 461 #define PIPE_RESOURCE_FLAG_DRV_PRIV    (1 << 16) /* driver/winsys private */
 462 #define PIPE_RESOURCE_FLAG_ST_PRIV     (1 << 24) /* state-tracker/winsys private */
 463
 464 /**
 465  * Hint about the expected lifecycle of a resource.
 466  * Sorted according to GPU vs CPU access.
 467  */
 468 enum pipe_resource_usage {
 469    PIPE_USAGE_DEFAULT,        /* fast GPU access */
 470    PIPE_USAGE_IMMUTABLE,      /* fast GPU access, immutable */
 471    PIPE_USAGE_DYNAMIC,        /* uploaded data is used multiple times */
 472    PIPE_USAGE_STREAM,         /* uploaded data is used once */
 473    PIPE_USAGE_STAGING,        /* fast CPU access */
 474 };
 475
 476 /**
 477  * Shaders
 478  */
 479 enum pipe_shader_type {
 480    PIPE_SHADER_VERTEX,
 481    PIPE_SHADER_FRAGMENT,
 482    PIPE_SHADER_GEOMETRY,
 483    PIPE_SHADER_TESS_CTRL,
 484    PIPE_SHADER_TESS_EVAL,
 485    PIPE_SHADER_COMPUTE,
 486    PIPE_SHADER_TYPES,
 487 };
 488
 489 /**
 490  * Primitive types:
 491  */
 492 enum pipe_prim_type {
 493    PIPE_PRIM_POINTS,
 494    PIPE_PRIM_LINES,
 495    PIPE_PRIM_LINE_LOOP,
 496    PIPE_PRIM_LINE_STRIP,
 497    PIPE_PRIM_TRIANGLES,
 498    PIPE_PRIM_TRIANGLE_STRIP,
 499    PIPE_PRIM_TRIANGLE_FAN,
 500    PIPE_PRIM_QUADS,
 501    PIPE_PRIM_QUAD_STRIP,
 502    PIPE_PRIM_POLYGON,
 503    PIPE_PRIM_LINES_ADJACENCY,
 504    PIPE_PRIM_LINE_STRIP_ADJACENCY,
 505    PIPE_PRIM_TRIANGLES_ADJACENCY,
 506    PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY,
 507    PIPE_PRIM_PATCHES,
 508    PIPE_PRIM_MAX,
 509 };
 510
 511 /**
 512  * Tessellator spacing types
 513  */
 514 enum pipe_tess_spacing {
 515    PIPE_TESS_SPACING_FRACTIONAL_ODD,
 516    PIPE_TESS_SPACING_FRACTIONAL_EVEN,
 517    PIPE_TESS_SPACING_EQUAL,
 518 };
 519
 520 /**
 521  * Query object types
 522  */
 523 enum pipe_query_type {
 524    PIPE_QUERY_OCCLUSION_COUNTER,
 525    PIPE_QUERY_OCCLUSION_PREDICATE,
 526    PIPE_QUERY_TIMESTAMP,
 527    PIPE_QUERY_TIMESTAMP_DISJOINT,
 528    PIPE_QUERY_TIME_ELAPSED,
 529    PIPE_QUERY_PRIMITIVES_GENERATED,
 530    PIPE_QUERY_PRIMITIVES_EMITTED,
 531    PIPE_QUERY_SO_STATISTICS,
 532    PIPE_QUERY_SO_OVERFLOW_PREDICATE,
 533    PIPE_QUERY_GPU_FINISHED,
 534    PIPE_QUERY_PIPELINE_STATISTICS,
 535    PIPE_QUERY_TYPES,
 536    /* start of driver queries, see pipe_screen::get_driver_query_info */
 537    PIPE_QUERY_DRIVER_SPECIFIC = 256,
 538 };
 539
 540 /**
 541  * Conditional rendering modes
 542  */
 543 enum pipe_render_cond_flag {
 544    PIPE_RENDER_COND_WAIT,
 545    PIPE_RENDER_COND_NO_WAIT,
 546    PIPE_RENDER_COND_BY_REGION_WAIT,
 547    PIPE_RENDER_COND_BY_REGION_NO_WAIT,
 548 };
 549
 550 /**
 551  * Point sprite coord modes
 552  */
 553 enum pipe_sprite_coord_mode {
 554    PIPE_SPRITE_COORD_UPPER_LEFT,
 555    PIPE_SPRITE_COORD_LOWER_LEFT,
 556 };
 557
 558 /**
 559  * Texture & format swizzles
 560  */
 561 enum pipe_swizzle {
 562    PIPE_SWIZZLE_X,
 563    PIPE_SWIZZLE_Y,
 564    PIPE_SWIZZLE_Z,
 565    PIPE_SWIZZLE_W,
 566    PIPE_SWIZZLE_0,
 567    PIPE_SWIZZLE_1,
 568    PIPE_SWIZZLE_NONE,
 569    PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */
 570 };
 571
 572 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
 573
 574
 575 /**
 576  * Device reset status.
 577  */
 578 enum pipe_reset_status
 579 {
 580    PIPE_NO_RESET,
 581    PIPE_GUILTY_CONTEXT_RESET,
 582    PIPE_INNOCENT_CONTEXT_RESET,
 583    PIPE_UNKNOWN_CONTEXT_RESET,
 584 };
 585
 586
 587 /**
 588  * resource_get_handle flags.
 589  */
 590 /* Requires pipe_context::flush_resource before external use. */
 591 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH  (1 << 0)
 592 /* Expected external use of the resource: */
 593 #define PIPE_HANDLE_USAGE_READ            (1 << 1)
 594 #define PIPE_HANDLE_USAGE_WRITE           (1 << 2)
 595 #define PIPE_HANDLE_USAGE_READ_WRITE      (PIPE_HANDLE_USAGE_READ | \
 596                                            PIPE_HANDLE_USAGE_WRITE)
 597
 598 /**
 599  * pipe_image_view access flags.
 600  */
 601 #define PIPE_IMAGE_ACCESS_READ       (1 << 0)
 602 #define PIPE_IMAGE_ACCESS_WRITE      (1 << 1)
 603 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
 604                                       PIPE_IMAGE_ACCESS_WRITE)
 605
 606 /**
 607  * Implementation capabilities/limits which are queried through
 608  * pipe_screen::get_param()
 609  */
 610 enum pipe_cap
 611 {
 612    PIPE_CAP_NPOT_TEXTURES,
 613    PIPE_CAP_TWO_SIDED_STENCIL,
 614    PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
 615    PIPE_CAP_ANISOTROPIC_FILTER,
 616    PIPE_CAP_POINT_SPRITE,
 617    PIPE_CAP_MAX_RENDER_TARGETS,
 618    PIPE_CAP_OCCLUSION_QUERY,
 619    PIPE_CAP_QUERY_TIME_ELAPSED,
 620    PIPE_CAP_TEXTURE_SHADOW_MAP,
 621    PIPE_CAP_TEXTURE_SWIZZLE,
 622    PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
 623    PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
 624    PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
 625    PIPE_CAP_TEXTURE_MIRROR_CLAMP,
 626    PIPE_CAP_BLEND_EQUATION_SEPARATE,
 627    PIPE_CAP_SM3,
 628    PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
 629    PIPE_CAP_PRIMITIVE_RESTART,
 630    /** blend enables and write masks per rendertarget */
 631    PIPE_CAP_INDEP_BLEND_ENABLE,
 632    /** different blend funcs per rendertarget */
 633    PIPE_CAP_INDEP_BLEND_FUNC,
 634    PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
 635    PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
 636    PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
 637    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
 638    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
 639    PIPE_CAP_DEPTH_CLIP_DISABLE,
 640    PIPE_CAP_SHADER_STENCIL_EXPORT,
 641    PIPE_CAP_TGSI_INSTANCEID,
 642    PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
 643    PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
 644    PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
 645    PIPE_CAP_SEAMLESS_CUBE_MAP,
 646    PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
 647    PIPE_CAP_MIN_TEXEL_OFFSET,
 648    PIPE_CAP_MAX_TEXEL_OFFSET,
 649    PIPE_CAP_CONDITIONAL_RENDER,
 650    PIPE_CAP_TEXTURE_BARRIER,
 651    PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS,
 652    PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS,
 653    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
 654    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
 655    PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
 656    PIPE_CAP_VERTEX_COLOR_CLAMPED,
 657    PIPE_CAP_GLSL_FEATURE_LEVEL,
 658    PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
 659    PIPE_CAP_USER_VERTEX_BUFFERS,
 660    PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
 661    PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
 662    PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
 663    PIPE_CAP_COMPUTE,
 664    PIPE_CAP_USER_CONSTANT_BUFFERS,
 665    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
 666    PIPE_CAP_START_INSTANCE,
 667    PIPE_CAP_QUERY_TIMESTAMP,
 668    PIPE_CAP_TEXTURE_MULTISAMPLE,
 669    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
 670    PIPE_CAP_CUBE_MAP_ARRAY,
 671    PIPE_CAP_TEXTURE_BUFFER_OBJECTS,
 672    PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT,
 673    PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY,
 674    PIPE_CAP_TGSI_TEXCOORD,
 675    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
 676    PIPE_CAP_QUERY_PIPELINE_STATISTICS,
 677    PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
 678    PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
 679    PIPE_CAP_MAX_VIEWPORTS,
 680    PIPE_CAP_ENDIANNESS,
 681    PIPE_CAP_MIXED_FRAMEBUFFER_SIZES,
 682    PIPE_CAP_TGSI_VS_LAYER_VIEWPORT,
 683    PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES,
 684    PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
 685    PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
 686    PIPE_CAP_TEXTURE_GATHER_SM5,
 687    PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
 688    PIPE_CAP_FAKE_SW_MSAA,
 689    PIPE_CAP_TEXTURE_QUERY_LOD,
 690    PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
 691    PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET,
 692    PIPE_CAP_SAMPLE_SHADING,
 693    PIPE_CAP_TEXTURE_GATHER_OFFSETS,
 694    PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
 695    PIPE_CAP_MAX_VERTEX_STREAMS,
 696    PIPE_CAP_DRAW_INDIRECT,
 697    PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
 698    PIPE_CAP_VENDOR_ID,
 699    PIPE_CAP_DEVICE_ID,
 700    PIPE_CAP_ACCELERATED,
 701    PIPE_CAP_VIDEO_MEMORY,
 702    PIPE_CAP_UMA,
 703    PIPE_CAP_CONDITIONAL_RENDER_INVERTED,
 704    PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
 705    PIPE_CAP_SAMPLER_VIEW_TARGET,
 706    PIPE_CAP_CLIP_HALFZ,
 707    PIPE_CAP_VERTEXID_NOBASE,
 708    PIPE_CAP_POLYGON_OFFSET_CLAMP,
 709    PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
 710    PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
 711    PIPE_CAP_DEVICE_RESET_STATUS_QUERY,
 712    PIPE_CAP_MAX_SHADER_PATCH_VARYINGS,
 713    PIPE_CAP_TEXTURE_FLOAT_LINEAR,
 714    PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
 715    PIPE_CAP_DEPTH_BOUNDS_TEST,
 716    PIPE_CAP_TGSI_TXQS,
 717    PIPE_CAP_FORCE_PERSAMPLE_INTERP,
 718    PIPE_CAP_SHAREABLE_SHADERS,
 719    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
 720    PIPE_CAP_CLEAR_TEXTURE,
 721    PIPE_CAP_DRAW_PARAMETERS,
 722    PIPE_CAP_TGSI_PACK_HALF_FLOAT,
 723    PIPE_CAP_MULTI_DRAW_INDIRECT,
 724    PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
 725    PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
 726    PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
 727    PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
 728    PIPE_CAP_INVALIDATE_BUFFER,
 729    PIPE_CAP_GENERATE_MIPMAP,
 730    PIPE_CAP_STRING_MARKER,
 731    PIPE_CAP_SURFACE_REINTERPRET_BLOCKS,
 732    PIPE_CAP_QUERY_BUFFER_OBJECT,
 733    PIPE_CAP_QUERY_MEMORY_INFO,
 734    PIPE_CAP_PCI_GROUP,
 735    PIPE_CAP_PCI_BUS,
 736    PIPE_CAP_PCI_DEVICE,
 737    PIPE_CAP_PCI_FUNCTION,
 738    PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT,
 739    PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR,
 740    PIPE_CAP_CULL_DISTANCE,
 741    PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES,
 742    PIPE_CAP_TGSI_VOTE,
 743    PIPE_CAP_MAX_WINDOW_RECTANGLES,
 744    PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
 745    PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
 746    PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
 747    PIPE_CAP_TGSI_ARRAY_COMPONENTS,
 748    PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
 749    PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
 750    PIPE_CAP_NATIVE_FENCE_FD,
 751    PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
 752    PIPE_CAP_TGSI_FS_FBFETCH,
 753    PIPE_CAP_TGSI_MUL_ZERO_WINS,
 754    PIPE_CAP_DOUBLES,
 755    PIPE_CAP_INT64,
 756    PIPE_CAP_INT64_DIVMOD,
 757    PIPE_CAP_TGSI_TEX_TXF_LZ,
 758 };
 759
 760 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
 761 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
 762
 763 enum pipe_endian
 764 {
 765    PIPE_ENDIAN_LITTLE = 0,
 766    PIPE_ENDIAN_BIG = 1,
 767 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
 768    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
 769 #elif defined(PIPE_ARCH_BIG_ENDIAN)
 770    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
 771 #endif
 772 };
 773
 774 /**
 775  * Implementation limits which are queried through
 776  * pipe_screen::get_paramf()
 777  */
 778 enum pipe_capf
 779 {
 780    PIPE_CAPF_MAX_LINE_WIDTH,
 781    PIPE_CAPF_MAX_LINE_WIDTH_AA,
 782    PIPE_CAPF_MAX_POINT_WIDTH,
 783    PIPE_CAPF_MAX_POINT_WIDTH_AA,
 784    PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
 785    PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
 786    PIPE_CAPF_GUARD_BAND_LEFT,
 787    PIPE_CAPF_GUARD_BAND_TOP,
 788    PIPE_CAPF_GUARD_BAND_RIGHT,
 789    PIPE_CAPF_GUARD_BAND_BOTTOM
 790 };
 791
 792 /** Shader caps not specific to any single stage */
 793 enum pipe_shader_cap
 794 {
 795    PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
 796    PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
 797    PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
 798    PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
 799    PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
 800    PIPE_SHADER_CAP_MAX_INPUTS,
 801    PIPE_SHADER_CAP_MAX_OUTPUTS,
 802    PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
 803    PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
 804    PIPE_SHADER_CAP_MAX_TEMPS,
 805    PIPE_SHADER_CAP_MAX_PREDS,
 806    /* boolean caps */
 807    PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
 808    PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
 809    PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
 810    PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
 811    PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
 812    PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
 813    PIPE_SHADER_CAP_INTEGERS,
 814    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
 815    PIPE_SHADER_CAP_PREFERRED_IR,
 816    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
 817    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
 818    PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
 819    PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
 820    PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
 821    PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
 822    PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
 823    PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
 824    PIPE_SHADER_CAP_SUPPORTED_IRS,
 825    PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
 826    PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
 827 };
 828
 829 /**
 830  * Shader intermediate representation.
 831  *
 832  * Note that if the driver requests something other than TGSI, it must
 833  * always be prepared to receive TGSI in addition to its preferred IR.
 834  * If the driver requests TGSI as its preferred IR, it will *always*
 835  * get TGSI.
 836  *
 837  * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
 838  * state trackers that only understand TGSI.
 839  */
 840 enum pipe_shader_ir
 841 {
 842    PIPE_SHADER_IR_TGSI = 0,
 843    PIPE_SHADER_IR_LLVM,
 844    PIPE_SHADER_IR_NATIVE,
 845    PIPE_SHADER_IR_NIR,
 846 };
 847
 848 /**
 849  * Compute-specific implementation capability.  They can be queried
 850  * using pipe_screen::get_compute_param.
 851  */
 852 enum pipe_compute_cap
 853 {
 854    PIPE_COMPUTE_CAP_ADDRESS_BITS,
 855    PIPE_COMPUTE_CAP_IR_TARGET,
 856    PIPE_COMPUTE_CAP_GRID_DIMENSION,
 857    PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
 858    PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
 859    PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 860    PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 861    PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
 862    PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
 863    PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
 864    PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 865    PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
 866    PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
 867    PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
 868    PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
 869    PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 870 };
 871
 872 /**
 873  * Composite query types
 874  */
 875
 876 /**
 877  * Query result for PIPE_QUERY_SO_STATISTICS.
 878  */
 879 struct pipe_query_data_so_statistics
 880 {
 881    uint64_t num_primitives_written;
 882    uint64_t primitives_storage_needed;
 883 };
 884
 885 /**
 886  * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
 887  */
 888 struct pipe_query_data_timestamp_disjoint
 889 {
 890    uint64_t frequency;
 891    boolean  disjoint;
 892 };
 893
 894 /**
 895  * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
 896  */
 897 struct pipe_query_data_pipeline_statistics
 898 {
 899    uint64_t ia_vertices;    /**< Num vertices read by the vertex fetcher. */
 900    uint64_t ia_primitives;  /**< Num primitives read by the vertex fetcher. */
 901    uint64_t vs_invocations; /**< Num vertex shader invocations. */
 902    uint64_t gs_invocations; /**< Num geometry shader invocations. */
 903    uint64_t gs_primitives;  /**< Num primitives output by a geometry shader. */
 904    uint64_t c_invocations;  /**< Num primitives sent to the rasterizer. */
 905    uint64_t c_primitives;   /**< Num primitives that were rendered. */
 906    uint64_t ps_invocations; /**< Num pixel shader invocations. */
 907    uint64_t hs_invocations; /**< Num hull shader invocations. */
 908    uint64_t ds_invocations; /**< Num domain shader invocations. */
 909    uint64_t cs_invocations; /**< Num compute shader invocations. */
 910 };
 911
 912 /**
 913  * For batch queries.
 914  */
 915 union pipe_numeric_type_union
 916 {
 917    uint64_t u64;
 918    uint32_t u32;
 919    float f;
 920 };
 921
 922 /**
 923  * Query result (returned by pipe_context::get_query_result).
 924  */
 925 union pipe_query_result
 926 {
 927    /* PIPE_QUERY_OCCLUSION_PREDICATE */
 928    /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
 929    /* PIPE_QUERY_GPU_FINISHED */
 930    boolean b;
 931
 932    /* PIPE_QUERY_OCCLUSION_COUNTER */
 933    /* PIPE_QUERY_TIMESTAMP */
 934    /* PIPE_QUERY_TIME_ELAPSED */
 935    /* PIPE_QUERY_PRIMITIVES_GENERATED */
 936    /* PIPE_QUERY_PRIMITIVES_EMITTED */
 937    /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
 938    /* PIPE_DRIVER_QUERY_TYPE_BYTES */
 939    /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
 940    /* PIPE_DRIVER_QUERY_TYPE_HZ */
 941    uint64_t u64;
 942
 943    /* PIPE_DRIVER_QUERY_TYPE_UINT */
 944    uint32_t u32;
 945
 946    /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
 947    /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
 948    float f;
 949
 950    /* PIPE_QUERY_SO_STATISTICS */
 951    struct pipe_query_data_so_statistics so_statistics;
 952
 953    /* PIPE_QUERY_TIMESTAMP_DISJOINT */
 954    struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
 955
 956    /* PIPE_QUERY_PIPELINE_STATISTICS */
 957    struct pipe_query_data_pipeline_statistics pipeline_statistics;
 958
 959    /* batch queries (variable length) */
 960    union pipe_numeric_type_union batch[1];
 961 };
 962
 963 enum pipe_query_value_type
 964 {
 965    PIPE_QUERY_TYPE_I32,
 966    PIPE_QUERY_TYPE_U32,
 967    PIPE_QUERY_TYPE_I64,
 968    PIPE_QUERY_TYPE_U64,
 969 };
 970
 971 union pipe_color_union
 972 {
 973    float f[4];
 974    int i[4];
 975    unsigned int ui[4];
 976 };
 977
 978 enum pipe_driver_query_type
 979 {
 980    PIPE_DRIVER_QUERY_TYPE_UINT64,
 981    PIPE_DRIVER_QUERY_TYPE_UINT,
 982    PIPE_DRIVER_QUERY_TYPE_FLOAT,
 983    PIPE_DRIVER_QUERY_TYPE_PERCENTAGE,
 984    PIPE_DRIVER_QUERY_TYPE_BYTES,
 985    PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
 986    PIPE_DRIVER_QUERY_TYPE_HZ,
 987    PIPE_DRIVER_QUERY_TYPE_DBM,
 988    PIPE_DRIVER_QUERY_TYPE_TEMPERATURE,
 989    PIPE_DRIVER_QUERY_TYPE_VOLTS,
 990    PIPE_DRIVER_QUERY_TYPE_AMPS,
 991    PIPE_DRIVER_QUERY_TYPE_WATTS,
 992 };
 993
 994 /* Whether an average value per frame or a cumulative value should be
 995  * displayed.
 996  */
 997 enum pipe_driver_query_result_type
 998 {
 999    PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE,
1000    PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE,
1001 };
1002
1003 /**
1004  * Some hardware requires some hardware-specific queries to be submitted
1005  * as batched queries. The corresponding query objects are created using
1006  * create_batch_query, and at most one such query may be active at
1007  * any time.
1008  */
1009 #define PIPE_DRIVER_QUERY_FLAG_BATCH     (1 << 0)
1010
1011 /* Do not list this query in the HUD. */
1012 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
1013
1014 struct pipe_driver_query_info
1015 {
1016    const char *name;
1017    unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
1018    union pipe_numeric_type_union max_value; /* max value that can be returned */
1019    enum pipe_driver_query_type type;
1020    enum pipe_driver_query_result_type result_type;
1021    unsigned group_id;
1022    unsigned flags;
1023 };
1024
1025 struct pipe_driver_query_group_info
1026 {
1027    const char *name;
1028    unsigned max_active_queries;
1029    unsigned num_queries;
1030 };
1031
1032 enum pipe_debug_type
1033 {
1034    PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1,
1035    PIPE_DEBUG_TYPE_ERROR,
1036    PIPE_DEBUG_TYPE_SHADER_INFO,
1037    PIPE_DEBUG_TYPE_PERF_INFO,
1038    PIPE_DEBUG_TYPE_INFO,
1039    PIPE_DEBUG_TYPE_FALLBACK,
1040    PIPE_DEBUG_TYPE_CONFORMANCE,
1041 };
1042
1043
1044 #ifdef __cplusplus
1045 }
1046 #endif
1047
1048 #endif