src/gallium/include/pipe/p_defines.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
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  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef PIPE_DEFINES_H
  29 #define PIPE_DEFINES_H
  30
  31 #include "p_compiler.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /**
  38  * Gallium error codes.
  39  *
  40  * - A zero value always means success.
  41  * - A negative value always means failure.
  42  * - The meaning of a positive value is function dependent.
  43  */
  44 enum pipe_error
  45 {
  46    PIPE_OK = 0,
  47    PIPE_ERROR = -1,    /**< Generic error */
  48    PIPE_ERROR_BAD_INPUT = -2,
  49    PIPE_ERROR_OUT_OF_MEMORY = -3,
  50    PIPE_ERROR_RETRY = -4
  51    /* TODO */
  52 };
  53
  54
  55 #define PIPE_BLENDFACTOR_ONE                 0x1
  56 #define PIPE_BLENDFACTOR_SRC_COLOR           0x2
  57 #define PIPE_BLENDFACTOR_SRC_ALPHA           0x3
  58 #define PIPE_BLENDFACTOR_DST_ALPHA           0x4
  59 #define PIPE_BLENDFACTOR_DST_COLOR           0x5
  60 #define PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE  0x6
  61 #define PIPE_BLENDFACTOR_CONST_COLOR         0x7
  62 #define PIPE_BLENDFACTOR_CONST_ALPHA         0x8
  63 #define PIPE_BLENDFACTOR_SRC1_COLOR          0x9
  64 #define PIPE_BLENDFACTOR_SRC1_ALPHA          0x0A
  65 #define PIPE_BLENDFACTOR_ZERO                0x11
  66 #define PIPE_BLENDFACTOR_INV_SRC_COLOR       0x12
  67 #define PIPE_BLENDFACTOR_INV_SRC_ALPHA       0x13
  68 #define PIPE_BLENDFACTOR_INV_DST_ALPHA       0x14
  69 #define PIPE_BLENDFACTOR_INV_DST_COLOR       0x15
  70 #define PIPE_BLENDFACTOR_INV_CONST_COLOR     0x17
  71 #define PIPE_BLENDFACTOR_INV_CONST_ALPHA     0x18
  72 #define PIPE_BLENDFACTOR_INV_SRC1_COLOR      0x19
  73 #define PIPE_BLENDFACTOR_INV_SRC1_ALPHA      0x1A
  74
  75 #define PIPE_BLEND_ADD               0
  76 #define PIPE_BLEND_SUBTRACT          1
  77 #define PIPE_BLEND_REVERSE_SUBTRACT  2
  78 #define PIPE_BLEND_MIN               3
  79 #define PIPE_BLEND_MAX               4
  80
  81 #define PIPE_LOGICOP_CLEAR            0
  82 #define PIPE_LOGICOP_NOR              1
  83 #define PIPE_LOGICOP_AND_INVERTED     2
  84 #define PIPE_LOGICOP_COPY_INVERTED    3
  85 #define PIPE_LOGICOP_AND_REVERSE      4
  86 #define PIPE_LOGICOP_INVERT           5
  87 #define PIPE_LOGICOP_XOR              6
  88 #define PIPE_LOGICOP_NAND             7
  89 #define PIPE_LOGICOP_AND              8
  90 #define PIPE_LOGICOP_EQUIV            9
  91 #define PIPE_LOGICOP_NOOP             10
  92 #define PIPE_LOGICOP_OR_INVERTED      11
  93 #define PIPE_LOGICOP_COPY             12
  94 #define PIPE_LOGICOP_OR_REVERSE       13
  95 #define PIPE_LOGICOP_OR               14
  96 #define PIPE_LOGICOP_SET              15
  97
  98 #define PIPE_MASK_R  0x1
  99 #define PIPE_MASK_G  0x2
 100 #define PIPE_MASK_B  0x4
 101 #define PIPE_MASK_A  0x8
 102 #define PIPE_MASK_RGBA 0xf
 103 #define PIPE_MASK_Z  0x10
 104 #define PIPE_MASK_S  0x20
 105 #define PIPE_MASK_ZS 0x30
 106 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
 107
 108
 109 /**
 110  * Inequality functions.  Used for depth test, stencil compare, alpha
 111  * test, shadow compare, etc.
 112  */
 113 #define PIPE_FUNC_NEVER    0
 114 #define PIPE_FUNC_LESS     1
 115 #define PIPE_FUNC_EQUAL    2
 116 #define PIPE_FUNC_LEQUAL   3
 117 #define PIPE_FUNC_GREATER  4
 118 #define PIPE_FUNC_NOTEQUAL 5
 119 #define PIPE_FUNC_GEQUAL   6
 120 #define PIPE_FUNC_ALWAYS   7
 121
 122 /** Polygon fill mode */
 123 #define PIPE_POLYGON_MODE_FILL  0
 124 #define PIPE_POLYGON_MODE_LINE  1
 125 #define PIPE_POLYGON_MODE_POINT 2
 126
 127 /** Polygon face specification, eg for culling */
 128 #define PIPE_FACE_NONE           0
 129 #define PIPE_FACE_FRONT          1
 130 #define PIPE_FACE_BACK           2
 131 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
 132
 133 /** Stencil ops */
 134 #define PIPE_STENCIL_OP_KEEP       0
 135 #define PIPE_STENCIL_OP_ZERO       1
 136 #define PIPE_STENCIL_OP_REPLACE    2
 137 #define PIPE_STENCIL_OP_INCR       3
 138 #define PIPE_STENCIL_OP_DECR       4
 139 #define PIPE_STENCIL_OP_INCR_WRAP  5
 140 #define PIPE_STENCIL_OP_DECR_WRAP  6
 141 #define PIPE_STENCIL_OP_INVERT     7
 142
 143 /** Texture types.
 144  * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
 145  */
 146 enum pipe_texture_target
 147 {
 148    PIPE_BUFFER           = 0,
 149    PIPE_TEXTURE_1D       = 1,
 150    PIPE_TEXTURE_2D       = 2,
 151    PIPE_TEXTURE_3D       = 3,
 152    PIPE_TEXTURE_CUBE     = 4,
 153    PIPE_TEXTURE_RECT     = 5,
 154    PIPE_TEXTURE_1D_ARRAY = 6,
 155    PIPE_TEXTURE_2D_ARRAY = 7,
 156    PIPE_TEXTURE_CUBE_ARRAY = 8,
 157    PIPE_MAX_TEXTURE_TYPES
 158 };
 159
 160 #define PIPE_TEX_FACE_POS_X 0
 161 #define PIPE_TEX_FACE_NEG_X 1
 162 #define PIPE_TEX_FACE_POS_Y 2
 163 #define PIPE_TEX_FACE_NEG_Y 3
 164 #define PIPE_TEX_FACE_POS_Z 4
 165 #define PIPE_TEX_FACE_NEG_Z 5
 166 #define PIPE_TEX_FACE_MAX   6
 167
 168 #define PIPE_TEX_WRAP_REPEAT                   0
 169 #define PIPE_TEX_WRAP_CLAMP                    1
 170 #define PIPE_TEX_WRAP_CLAMP_TO_EDGE            2
 171 #define PIPE_TEX_WRAP_CLAMP_TO_BORDER          3
 172 #define PIPE_TEX_WRAP_MIRROR_REPEAT            4
 173 #define PIPE_TEX_WRAP_MIRROR_CLAMP             5
 174 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE     6
 175 #define PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER   7
 176
 177 /** Between mipmaps, ie mipfilter */
 178 #define PIPE_TEX_MIPFILTER_NEAREST  0
 179 #define PIPE_TEX_MIPFILTER_LINEAR   1
 180 #define PIPE_TEX_MIPFILTER_NONE     2
 181
 182 /** Within a mipmap, ie min/mag filter */
 183 #define PIPE_TEX_FILTER_NEAREST      0
 184 #define PIPE_TEX_FILTER_LINEAR       1
 185
 186 #define PIPE_TEX_COMPARE_NONE          0
 187 #define PIPE_TEX_COMPARE_R_TO_TEXTURE  1
 188
 189 /**
 190  * Clear buffer bits
 191  */
 192 #define PIPE_CLEAR_DEPTH        (1 << 0)
 193 #define PIPE_CLEAR_STENCIL      (1 << 1)
 194 #define PIPE_CLEAR_COLOR0       (1 << 2)
 195 #define PIPE_CLEAR_COLOR1       (1 << 3)
 196 #define PIPE_CLEAR_COLOR2       (1 << 4)
 197 #define PIPE_CLEAR_COLOR3       (1 << 5)
 198 #define PIPE_CLEAR_COLOR4       (1 << 6)
 199 #define PIPE_CLEAR_COLOR5       (1 << 7)
 200 #define PIPE_CLEAR_COLOR6       (1 << 8)
 201 #define PIPE_CLEAR_COLOR7       (1 << 9)
 202 /** Combined flags */
 203 /** All color buffers currently bound */
 204 #define PIPE_CLEAR_COLOR        (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
 205                                  PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
 206                                  PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
 207                                  PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
 208 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
 209
 210 /**
 211  * Transfer object usage flags
 212  */
 213 enum pipe_transfer_usage
 214 {
 215    /**
 216     * Resource contents read back (or accessed directly) at transfer
 217     * create time.
 218     */
 219    PIPE_TRANSFER_READ = (1 << 0),
 220
 221    /**
 222     * Resource contents will be written back at transfer_unmap
 223     * time (or modified as a result of being accessed directly).
 224     */
 225    PIPE_TRANSFER_WRITE = (1 << 1),
 226
 227    /**
 228     * Read/modify/write
 229     */
 230    PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
 231
 232    /**
 233     * The transfer should map the texture storage directly. The driver may
 234     * return NULL if that isn't possible, and the state tracker needs to cope
 235     * with that and use an alternative path without this flag.
 236     *
 237     * E.g. the state tracker could have a simpler path which maps textures and
 238     * does read/modify/write cycles on them directly, and a more complicated
 239     * path which uses minimal read and write transfers.
 240     */
 241    PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
 242
 243    /**
 244     * Discards the memory within the mapped region.
 245     *
 246     * It should not be used with PIPE_TRANSFER_READ.
 247     *
 248     * See also:
 249     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
 250     */
 251    PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
 252
 253    /**
 254     * Fail if the resource cannot be mapped immediately.
 255     *
 256     * See also:
 257     * - Direct3D's D3DLOCK_DONOTWAIT flag.
 258     * - Mesa3D's MESA_MAP_NOWAIT_BIT flag.
 259     * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
 260     */
 261    PIPE_TRANSFER_DONTBLOCK = (1 << 9),
 262
 263    /**
 264     * Do not attempt to synchronize pending operations on the resource when mapping.
 265     *
 266     * It should not be used with PIPE_TRANSFER_READ.
 267     *
 268     * See also:
 269     * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
 270     * - Direct3D's D3DLOCK_NOOVERWRITE flag.
 271     * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
 272     */
 273    PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
 274
 275    /**
 276     * Written ranges will be notified later with
 277     * pipe_context::transfer_flush_region.
 278     *
 279     * It should not be used with PIPE_TRANSFER_READ.
 280     *
 281     * See also:
 282     * - pipe_context::transfer_flush_region
 283     * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
 284     */
 285    PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
 286
 287    /**
 288     * Discards all memory backing the resource.
 289     *
 290     * It should not be used with PIPE_TRANSFER_READ.
 291     *
 292     * This is equivalent to:
 293     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
 294     * - BufferData(NULL) on a GL buffer
 295     * - Direct3D's D3DLOCK_DISCARD flag.
 296     * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
 297     * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
 298     * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
 299     */
 300    PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
 301
 302    /**
 303     * Allows the resource to be used for rendering while mapped.
 304     *
 305     * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
 306     * the resource.
 307     *
 308     * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
 309     * must be called to ensure the device can see what the CPU has written.
 310     */
 311    PIPE_TRANSFER_PERSISTENT = (1 << 13),
 312
 313    /**
 314     * If PERSISTENT is set, this ensures any writes done by the device are
 315     * immediately visible to the CPU and vice versa.
 316     *
 317     * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
 318     * the resource.
 319     */
 320    PIPE_TRANSFER_COHERENT = (1 << 14)
 321 };
 322
 323 /**
 324  * Flags for the flush function.
 325  */
 326 enum pipe_flush_flags
 327 {
 328    PIPE_FLUSH_END_OF_FRAME = (1 << 0)
 329 };
 330
 331 /**
 332  * Flags for pipe_context::dump_debug_state.
 333  */
 334 #define PIPE_DEBUG_DEVICE_IS_HUNG      (1 << 0)
 335
 336 /**
 337  * Create a compute-only context. Use in pipe_screen::context_create.
 338  * This disables draw, blit, and clear*, render_condition, and other graphics
 339  * functions. Interop with other graphics contexts is still allowed.
 340  * This allows scheduling jobs on a compute-only hardware command queue that
 341  * can run in parallel with graphics without stalling it.
 342  */
 343 #define PIPE_CONTEXT_COMPUTE_ONLY      (1 << 0)
 344
 345 /**
 346  * Gather debug information and expect that pipe_context::dump_debug_state
 347  * will be called. Use in pipe_screen::context_create.
 348  */
 349 #define PIPE_CONTEXT_DEBUG             (1 << 1)
 350
 351 /**
 352  * Whether out-of-bounds shader loads must return zero and out-of-bounds
 353  * shader stores must be dropped.
 354  */
 355 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
 356
 357 /**
 358  * Flags for pipe_context::memory_barrier.
 359  */
 360 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
 361 #define PIPE_BARRIER_SHADER_BUFFER     (1 << 1)
 362 #define PIPE_BARRIER_QUERY_BUFFER      (1 << 2)
 363
 364 /**
 365  * Resource binding flags -- state tracker must specify in advance all
 366  * the ways a resource might be used.
 367  */
 368 #define PIPE_BIND_DEPTH_STENCIL        (1 << 0) /* create_surface */
 369 #define PIPE_BIND_RENDER_TARGET        (1 << 1) /* create_surface */
 370 #define PIPE_BIND_BLENDABLE            (1 << 2) /* create_surface */
 371 #define PIPE_BIND_SAMPLER_VIEW         (1 << 3) /* create_sampler_view */
 372 #define PIPE_BIND_VERTEX_BUFFER        (1 << 4) /* set_vertex_buffers */
 373 #define PIPE_BIND_INDEX_BUFFER         (1 << 5) /* draw_elements */
 374 #define PIPE_BIND_CONSTANT_BUFFER      (1 << 6) /* set_constant_buffer */
 375 #define PIPE_BIND_DISPLAY_TARGET       (1 << 7) /* flush_front_buffer */
 376 #define PIPE_BIND_TRANSFER_WRITE       (1 << 8) /* transfer_map */
 377 #define PIPE_BIND_TRANSFER_READ        (1 << 9) /* transfer_map */
 378 #define PIPE_BIND_STREAM_OUTPUT        (1 << 10) /* set_stream_output_buffers */
 379 #define PIPE_BIND_CURSOR               (1 << 11) /* mouse cursor */
 380 #define PIPE_BIND_CUSTOM               (1 << 12) /* state-tracker/winsys usages */
 381 #define PIPE_BIND_GLOBAL               (1 << 13) /* set_global_binding */
 382 #define PIPE_BIND_SHADER_BUFFER        (1 << 14) /* set_shader_buffers */
 383 #define PIPE_BIND_SHADER_IMAGE         (1 << 15) /* set_shader_images */
 384 #define PIPE_BIND_COMPUTE_RESOURCE     (1 << 16) /* set_compute_resources */
 385 #define PIPE_BIND_COMMAND_ARGS_BUFFER  (1 << 17) /* pipe_draw_info.indirect */
 386 #define PIPE_BIND_QUERY_BUFFER         (1 << 18) /* get_query_result_resource */
 387
 388 /**
 389  * The first two flags above were previously part of the amorphous
 390  * TEXTURE_USAGE, most of which are now descriptions of the ways a
 391  * particular texture can be bound to the gallium pipeline.  The two flags
 392  * below do not fit within that and probably need to be migrated to some
 393  * other place.
 394  *
 395  * It seems like scanout is used by the Xorg state tracker to ask for
 396  * a texture suitable for actual scanout (hence the name), which
 397  * implies extra layout constraints on some hardware.  It may also
 398  * have some special meaning regarding mouse cursor images.
 399  *
 400  * The shared flag is quite underspecified, but certainly isn't a
 401  * binding flag - it seems more like a message to the winsys to create
 402  * a shareable allocation.
 403  *
 404  * The third flag has been added to be able to force textures to be created
 405  * in linear mode (no tiling).
 406  */
 407 #define PIPE_BIND_SCANOUT     (1 << 19) /*  */
 408 #define PIPE_BIND_SHARED      (1 << 20) /* get_texture_handle ??? */
 409 #define PIPE_BIND_LINEAR      (1 << 21)
 410
 411
 412 /**
 413  * Flags for the driver about resource behaviour:
 414  */
 415 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
 416 #define PIPE_RESOURCE_FLAG_MAP_COHERENT   (1 << 1)
 417 #define PIPE_RESOURCE_FLAG_DRV_PRIV    (1 << 16) /* driver/winsys private */
 418 #define PIPE_RESOURCE_FLAG_ST_PRIV     (1 << 24) /* state-tracker/winsys private */
 419
 420 /**
 421  * Hint about the expected lifecycle of a resource.
 422  * Sorted according to GPU vs CPU access.
 423  */
 424 #define PIPE_USAGE_DEFAULT        0 /* fast GPU access */
 425 #define PIPE_USAGE_IMMUTABLE      1 /* fast GPU access, immutable */
 426 #define PIPE_USAGE_DYNAMIC        2 /* uploaded data is used multiple times */
 427 #define PIPE_USAGE_STREAM         3 /* uploaded data is used once */
 428 #define PIPE_USAGE_STAGING        4 /* fast CPU access */
 429
 430
 431 /**
 432  * Shaders
 433  */
 434 #define PIPE_SHADER_VERTEX   0
 435 #define PIPE_SHADER_FRAGMENT 1
 436 #define PIPE_SHADER_GEOMETRY 2
 437 #define PIPE_SHADER_TESS_CTRL 3
 438 #define PIPE_SHADER_TESS_EVAL 4
 439 #define PIPE_SHADER_COMPUTE  5
 440 #define PIPE_SHADER_TYPES    6
 441
 442
 443 /**
 444  * Primitive types:
 445  */
 446 #define PIPE_PRIM_POINTS                    0
 447 #define PIPE_PRIM_LINES                     1
 448 #define PIPE_PRIM_LINE_LOOP                 2
 449 #define PIPE_PRIM_LINE_STRIP                3
 450 #define PIPE_PRIM_TRIANGLES                 4
 451 #define PIPE_PRIM_TRIANGLE_STRIP            5
 452 #define PIPE_PRIM_TRIANGLE_FAN              6
 453 #define PIPE_PRIM_QUADS                     7
 454 #define PIPE_PRIM_QUAD_STRIP                8
 455 #define PIPE_PRIM_POLYGON                   9
 456 #define PIPE_PRIM_LINES_ADJACENCY          10
 457 #define PIPE_PRIM_LINE_STRIP_ADJACENCY     11
 458 #define PIPE_PRIM_TRIANGLES_ADJACENCY      12
 459 #define PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY 13
 460 #define PIPE_PRIM_PATCHES                  14
 461 #define PIPE_PRIM_MAX                      15
 462
 463
 464 /**
 465  * Tessellator spacing types
 466  */
 467 #define PIPE_TESS_SPACING_FRACTIONAL_ODD    0
 468 #define PIPE_TESS_SPACING_FRACTIONAL_EVEN   1
 469 #define PIPE_TESS_SPACING_EQUAL             2
 470
 471 /**
 472  * Query object types
 473  */
 474 #define PIPE_QUERY_OCCLUSION_COUNTER     0
 475 #define PIPE_QUERY_OCCLUSION_PREDICATE   1
 476 #define PIPE_QUERY_TIMESTAMP             2
 477 #define PIPE_QUERY_TIMESTAMP_DISJOINT    3
 478 #define PIPE_QUERY_TIME_ELAPSED          4
 479 #define PIPE_QUERY_PRIMITIVES_GENERATED  5
 480 #define PIPE_QUERY_PRIMITIVES_EMITTED    6
 481 #define PIPE_QUERY_SO_STATISTICS         7
 482 #define PIPE_QUERY_SO_OVERFLOW_PREDICATE 8
 483 #define PIPE_QUERY_GPU_FINISHED          9
 484 #define PIPE_QUERY_PIPELINE_STATISTICS  10
 485 #define PIPE_QUERY_TYPES                11
 486 /* start of driver queries, see pipe_screen::get_driver_query_info */
 487 #define PIPE_QUERY_DRIVER_SPECIFIC     256
 488
 489
 490 /**
 491  * Conditional rendering modes
 492  */
 493 #define PIPE_RENDER_COND_WAIT              0
 494 #define PIPE_RENDER_COND_NO_WAIT           1
 495 #define PIPE_RENDER_COND_BY_REGION_WAIT    2
 496 #define PIPE_RENDER_COND_BY_REGION_NO_WAIT 3
 497
 498
 499 /**
 500  * Point sprite coord modes
 501  */
 502 #define PIPE_SPRITE_COORD_UPPER_LEFT 0
 503 #define PIPE_SPRITE_COORD_LOWER_LEFT 1
 504
 505
 506 /**
 507  * Texture swizzles
 508  */
 509 #define PIPE_SWIZZLE_RED   0
 510 #define PIPE_SWIZZLE_GREEN 1
 511 #define PIPE_SWIZZLE_BLUE  2
 512 #define PIPE_SWIZZLE_ALPHA 3
 513 #define PIPE_SWIZZLE_ZERO  4
 514 #define PIPE_SWIZZLE_ONE   5
 515
 516
 517 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
 518
 519
 520 /**
 521  * Device reset status.
 522  */
 523 enum pipe_reset_status
 524 {
 525    PIPE_NO_RESET = 0,
 526    PIPE_GUILTY_CONTEXT_RESET = 1,
 527    PIPE_INNOCENT_CONTEXT_RESET = 2,
 528    PIPE_UNKNOWN_CONTEXT_RESET = 3
 529 };
 530
 531
 532 /**
 533  * resource_get_handle flags.
 534  */
 535 /* Requires pipe_context::flush_resource before external use. */
 536 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH  (1 << 0)
 537 /* Expected external use of the resource: */
 538 #define PIPE_HANDLE_USAGE_READ            (1 << 1)
 539 #define PIPE_HANDLE_USAGE_WRITE           (1 << 2)
 540 #define PIPE_HANDLE_USAGE_READ_WRITE      (PIPE_HANDLE_USAGE_READ | \
 541                                            PIPE_HANDLE_USAGE_WRITE)
 542
 543 /**
 544  * Implementation capabilities/limits which are queried through
 545  * pipe_screen::get_param()
 546  */
 547 enum pipe_cap
 548 {
 549    PIPE_CAP_NPOT_TEXTURES,
 550    PIPE_CAP_TWO_SIDED_STENCIL,
 551    PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
 552    PIPE_CAP_ANISOTROPIC_FILTER,
 553    PIPE_CAP_POINT_SPRITE,
 554    PIPE_CAP_MAX_RENDER_TARGETS,
 555    PIPE_CAP_OCCLUSION_QUERY,
 556    PIPE_CAP_QUERY_TIME_ELAPSED,
 557    PIPE_CAP_TEXTURE_SHADOW_MAP,
 558    PIPE_CAP_TEXTURE_SWIZZLE,
 559    PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
 560    PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
 561    PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
 562    PIPE_CAP_TEXTURE_MIRROR_CLAMP,
 563    PIPE_CAP_BLEND_EQUATION_SEPARATE,
 564    PIPE_CAP_SM3,
 565    PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
 566    PIPE_CAP_PRIMITIVE_RESTART,
 567    /** blend enables and write masks per rendertarget */
 568    PIPE_CAP_INDEP_BLEND_ENABLE,
 569    /** different blend funcs per rendertarget */
 570    PIPE_CAP_INDEP_BLEND_FUNC,
 571    PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
 572    PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
 573    PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
 574    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
 575    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
 576    PIPE_CAP_DEPTH_CLIP_DISABLE,
 577    PIPE_CAP_SHADER_STENCIL_EXPORT,
 578    PIPE_CAP_TGSI_INSTANCEID,
 579    PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
 580    PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
 581    PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
 582    PIPE_CAP_SEAMLESS_CUBE_MAP,
 583    PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
 584    PIPE_CAP_MIN_TEXEL_OFFSET,
 585    PIPE_CAP_MAX_TEXEL_OFFSET,
 586    PIPE_CAP_CONDITIONAL_RENDER,
 587    PIPE_CAP_TEXTURE_BARRIER,
 588    PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS,
 589    PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS,
 590    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
 591    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
 592    PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
 593    PIPE_CAP_VERTEX_COLOR_CLAMPED,
 594    PIPE_CAP_GLSL_FEATURE_LEVEL,
 595    PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
 596    PIPE_CAP_USER_VERTEX_BUFFERS,
 597    PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
 598    PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
 599    PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
 600    PIPE_CAP_COMPUTE,
 601    PIPE_CAP_USER_INDEX_BUFFERS,
 602    PIPE_CAP_USER_CONSTANT_BUFFERS,
 603    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
 604    PIPE_CAP_START_INSTANCE,
 605    PIPE_CAP_QUERY_TIMESTAMP,
 606    PIPE_CAP_TEXTURE_MULTISAMPLE,
 607    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
 608    PIPE_CAP_CUBE_MAP_ARRAY,
 609    PIPE_CAP_TEXTURE_BUFFER_OBJECTS,
 610    PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT,
 611    PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY,
 612    PIPE_CAP_TGSI_TEXCOORD,
 613    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
 614    PIPE_CAP_QUERY_PIPELINE_STATISTICS,
 615    PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
 616    PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
 617    PIPE_CAP_MAX_VIEWPORTS,
 618    PIPE_CAP_ENDIANNESS,
 619    PIPE_CAP_MIXED_FRAMEBUFFER_SIZES,
 620    PIPE_CAP_TGSI_VS_LAYER_VIEWPORT,
 621    PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES,
 622    PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
 623    PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
 624    PIPE_CAP_TEXTURE_GATHER_SM5,
 625    PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
 626    PIPE_CAP_FAKE_SW_MSAA,
 627    PIPE_CAP_TEXTURE_QUERY_LOD,
 628    PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
 629    PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET,
 630    PIPE_CAP_SAMPLE_SHADING,
 631    PIPE_CAP_TEXTURE_GATHER_OFFSETS,
 632    PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
 633    PIPE_CAP_MAX_VERTEX_STREAMS,
 634    PIPE_CAP_DRAW_INDIRECT,
 635    PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
 636    PIPE_CAP_VENDOR_ID,
 637    PIPE_CAP_DEVICE_ID,
 638    PIPE_CAP_ACCELERATED,
 639    PIPE_CAP_VIDEO_MEMORY,
 640    PIPE_CAP_UMA,
 641    PIPE_CAP_CONDITIONAL_RENDER_INVERTED,
 642    PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
 643    PIPE_CAP_SAMPLER_VIEW_TARGET,
 644    PIPE_CAP_CLIP_HALFZ,
 645    PIPE_CAP_VERTEXID_NOBASE,
 646    PIPE_CAP_POLYGON_OFFSET_CLAMP,
 647    PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
 648    PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
 649    PIPE_CAP_DEVICE_RESET_STATUS_QUERY,
 650    PIPE_CAP_MAX_SHADER_PATCH_VARYINGS,
 651    PIPE_CAP_TEXTURE_FLOAT_LINEAR,
 652    PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
 653    PIPE_CAP_DEPTH_BOUNDS_TEST,
 654    PIPE_CAP_TGSI_TXQS,
 655    PIPE_CAP_FORCE_PERSAMPLE_INTERP,
 656    PIPE_CAP_SHAREABLE_SHADERS,
 657    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
 658    PIPE_CAP_CLEAR_TEXTURE,
 659    PIPE_CAP_DRAW_PARAMETERS,
 660    PIPE_CAP_TGSI_PACK_HALF_FLOAT,
 661    PIPE_CAP_MULTI_DRAW_INDIRECT,
 662    PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
 663    PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
 664    PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
 665    PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
 666    PIPE_CAP_INVALIDATE_BUFFER,
 667    PIPE_CAP_GENERATE_MIPMAP,
 668    PIPE_CAP_STRING_MARKER,
 669    PIPE_CAP_SURFACE_REINTERPRET_BLOCKS,
 670    PIPE_CAP_QUERY_BUFFER_OBJECT,
 671    PIPE_CAP_QUERY_MEMORY_INFO,
 672    PIPE_CAP_PCI_GROUP,
 673    PIPE_CAP_PCI_BUS,
 674    PIPE_CAP_PCI_DEVICE,
 675    PIPE_CAP_PCI_FUNCTION,
 676 };
 677
 678 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
 679 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
 680
 681 enum pipe_endian
 682 {
 683    PIPE_ENDIAN_LITTLE = 0,
 684    PIPE_ENDIAN_BIG = 1,
 685 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
 686    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
 687 #elif defined(PIPE_ARCH_BIG_ENDIAN)
 688    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
 689 #endif
 690 };
 691
 692 /**
 693  * Implementation limits which are queried through
 694  * pipe_screen::get_paramf()
 695  */
 696 enum pipe_capf
 697 {
 698    PIPE_CAPF_MAX_LINE_WIDTH,
 699    PIPE_CAPF_MAX_LINE_WIDTH_AA,
 700    PIPE_CAPF_MAX_POINT_WIDTH,
 701    PIPE_CAPF_MAX_POINT_WIDTH_AA,
 702    PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
 703    PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
 704    PIPE_CAPF_GUARD_BAND_LEFT,
 705    PIPE_CAPF_GUARD_BAND_TOP,
 706    PIPE_CAPF_GUARD_BAND_RIGHT,
 707    PIPE_CAPF_GUARD_BAND_BOTTOM
 708 };
 709
 710 /** Shader caps not specific to any single stage */
 711 enum pipe_shader_cap
 712 {
 713    PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
 714    PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
 715    PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
 716    PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
 717    PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
 718    PIPE_SHADER_CAP_MAX_INPUTS,
 719    PIPE_SHADER_CAP_MAX_OUTPUTS,
 720    PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
 721    PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
 722    PIPE_SHADER_CAP_MAX_TEMPS,
 723    PIPE_SHADER_CAP_MAX_PREDS,
 724    /* boolean caps */
 725    PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
 726    PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
 727    PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
 728    PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
 729    PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
 730    PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
 731    PIPE_SHADER_CAP_INTEGERS,
 732    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
 733    PIPE_SHADER_CAP_PREFERRED_IR,
 734    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
 735    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
 736    PIPE_SHADER_CAP_DOUBLES,
 737    PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
 738    PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
 739    PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
 740    PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
 741    PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
 742    PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
 743    PIPE_SHADER_CAP_SUPPORTED_IRS,
 744    PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
 745 };
 746
 747 /**
 748  * Shader intermediate representation.
 749  */
 750 enum pipe_shader_ir
 751 {
 752    PIPE_SHADER_IR_TGSI,
 753    PIPE_SHADER_IR_LLVM,
 754    PIPE_SHADER_IR_NATIVE
 755 };
 756
 757 /**
 758  * Compute-specific implementation capability.  They can be queried
 759  * using pipe_screen::get_compute_param.
 760  */
 761 enum pipe_compute_cap
 762 {
 763    PIPE_COMPUTE_CAP_IR_TARGET,
 764    PIPE_COMPUTE_CAP_GRID_DIMENSION,
 765    PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
 766    PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
 767    PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 768    PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 769    PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
 770    PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
 771    PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
 772    PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 773    PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
 774    PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
 775    PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
 776    PIPE_COMPUTE_CAP_SUBGROUP_SIZE
 777 };
 778
 779 /**
 780  * Composite query types
 781  */
 782
 783 /**
 784  * Query result for PIPE_QUERY_SO_STATISTICS.
 785  */
 786 struct pipe_query_data_so_statistics
 787 {
 788    uint64_t num_primitives_written;
 789    uint64_t primitives_storage_needed;
 790 };
 791
 792 /**
 793  * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
 794  */
 795 struct pipe_query_data_timestamp_disjoint
 796 {
 797    uint64_t frequency;
 798    boolean  disjoint;
 799 };
 800
 801 /**
 802  * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
 803  */
 804 struct pipe_query_data_pipeline_statistics
 805 {
 806    uint64_t ia_vertices;    /**< Num vertices read by the vertex fetcher. */
 807    uint64_t ia_primitives;  /**< Num primitives read by the vertex fetcher. */
 808    uint64_t vs_invocations; /**< Num vertex shader invocations. */
 809    uint64_t gs_invocations; /**< Num geometry shader invocations. */
 810    uint64_t gs_primitives;  /**< Num primitives output by a geometry shader. */
 811    uint64_t c_invocations;  /**< Num primitives sent to the rasterizer. */
 812    uint64_t c_primitives;   /**< Num primitives that were rendered. */
 813    uint64_t ps_invocations; /**< Num pixel shader invocations. */
 814    uint64_t hs_invocations; /**< Num hull shader invocations. */
 815    uint64_t ds_invocations; /**< Num domain shader invocations. */
 816    uint64_t cs_invocations; /**< Num compute shader invocations. */
 817 };
 818
 819 /**
 820  * For batch queries.
 821  */
 822 union pipe_numeric_type_union
 823 {
 824    uint64_t u64;
 825    uint32_t u32;
 826    float f;
 827 };
 828
 829 /**
 830  * Query result (returned by pipe_context::get_query_result).
 831  */
 832 union pipe_query_result
 833 {
 834    /* PIPE_QUERY_OCCLUSION_PREDICATE */
 835    /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
 836    /* PIPE_QUERY_GPU_FINISHED */
 837    boolean b;
 838
 839    /* PIPE_QUERY_OCCLUSION_COUNTER */
 840    /* PIPE_QUERY_TIMESTAMP */
 841    /* PIPE_QUERY_TIME_ELAPSED */
 842    /* PIPE_QUERY_PRIMITIVES_GENERATED */
 843    /* PIPE_QUERY_PRIMITIVES_EMITTED */
 844    /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
 845    /* PIPE_DRIVER_QUERY_TYPE_BYTES */
 846    /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
 847    /* PIPE_DRIVER_QUERY_TYPE_HZ */
 848    uint64_t u64;
 849
 850    /* PIPE_DRIVER_QUERY_TYPE_UINT */
 851    uint32_t u32;
 852
 853    /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
 854    /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
 855    float f;
 856
 857    /* PIPE_QUERY_SO_STATISTICS */
 858    struct pipe_query_data_so_statistics so_statistics;
 859
 860    /* PIPE_QUERY_TIMESTAMP_DISJOINT */
 861    struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
 862
 863    /* PIPE_QUERY_PIPELINE_STATISTICS */
 864    struct pipe_query_data_pipeline_statistics pipeline_statistics;
 865
 866    /* batch queries (variable length) */
 867    union pipe_numeric_type_union batch[1];
 868 };
 869
 870 enum pipe_query_value_type
 871 {
 872    PIPE_QUERY_TYPE_I32,
 873    PIPE_QUERY_TYPE_U32,
 874    PIPE_QUERY_TYPE_I64,
 875    PIPE_QUERY_TYPE_U64,
 876 };
 877
 878 union pipe_color_union
 879 {
 880    float f[4];
 881    int i[4];
 882    unsigned int ui[4];
 883 };
 884
 885 enum pipe_driver_query_type
 886 {
 887    PIPE_DRIVER_QUERY_TYPE_UINT64       = 0,
 888    PIPE_DRIVER_QUERY_TYPE_UINT         = 1,
 889    PIPE_DRIVER_QUERY_TYPE_FLOAT        = 2,
 890    PIPE_DRIVER_QUERY_TYPE_PERCENTAGE   = 3,
 891    PIPE_DRIVER_QUERY_TYPE_BYTES        = 4,
 892    PIPE_DRIVER_QUERY_TYPE_MICROSECONDS = 5,
 893    PIPE_DRIVER_QUERY_TYPE_HZ           = 6,
 894 };
 895
 896 /* Whether an average value per frame or a cumulative value should be
 897  * displayed.
 898  */
 899 enum pipe_driver_query_result_type
 900 {
 901    PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE = 0,
 902    PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE = 1,
 903 };
 904
 905 /**
 906  * Some hardware requires some hardware-specific queries to be submitted
 907  * as batched queries. The corresponding query objects are created using
 908  * create_batch_query, and at most one such query may be active at
 909  * any time.
 910  */
 911 #define PIPE_DRIVER_QUERY_FLAG_BATCH     (1 << 0)
 912
 913 /* Do not list this query in the HUD. */
 914 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
 915
 916 struct pipe_driver_query_info
 917 {
 918    const char *name;
 919    unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
 920    union pipe_numeric_type_union max_value; /* max value that can be returned */
 921    enum pipe_driver_query_type type;
 922    enum pipe_driver_query_result_type result_type;
 923    unsigned group_id;
 924    unsigned flags;
 925 };
 926
 927 struct pipe_driver_query_group_info
 928 {
 929    const char *name;
 930    unsigned max_active_queries;
 931    unsigned num_queries;
 932 };
 933
 934 enum pipe_debug_type
 935 {
 936    PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1,
 937    PIPE_DEBUG_TYPE_ERROR,
 938    PIPE_DEBUG_TYPE_SHADER_INFO,
 939    PIPE_DEBUG_TYPE_PERF_INFO,
 940    PIPE_DEBUG_TYPE_INFO,
 941    PIPE_DEBUG_TYPE_FALLBACK,
 942    PIPE_DEBUG_TYPE_CONFORMANCE,
 943 };
 944
 945
 946 #ifdef __cplusplus
 947 }
 948 #endif
 949
 950 #endif