1 /**************************************************************************
3 * Copyright 2008 VMware, Inc.
4 * Copyright 2009-2010 VMware, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
29 #ifndef P_SHADER_TOKENS_H
30 #define P_SHADER_TOKENS_H
39 unsigned HeaderSize
: 8;
40 unsigned BodySize
: 24;
45 unsigned Processor
: 4; /* PIPE_SHADER_ */
46 unsigned Padding
: 28;
49 enum tgsi_token_type
{
50 TGSI_TOKEN_TYPE_DECLARATION
,
51 TGSI_TOKEN_TYPE_IMMEDIATE
,
52 TGSI_TOKEN_TYPE_INSTRUCTION
,
53 TGSI_TOKEN_TYPE_PROPERTY
,
58 unsigned Type
: 4; /**< TGSI_TOKEN_TYPE_x */
59 unsigned NrTokens
: 8; /**< UINT */
60 unsigned Padding
: 20;
72 TGSI_FILE_SYSTEM_VALUE
,
74 TGSI_FILE_SAMPLER_VIEW
,
79 TGSI_FILE_COUNT
, /**< how many TGSI_FILE_ types */
83 #define TGSI_WRITEMASK_NONE 0x00
84 #define TGSI_WRITEMASK_X 0x01
85 #define TGSI_WRITEMASK_Y 0x02
86 #define TGSI_WRITEMASK_XY 0x03
87 #define TGSI_WRITEMASK_Z 0x04
88 #define TGSI_WRITEMASK_XZ 0x05
89 #define TGSI_WRITEMASK_YZ 0x06
90 #define TGSI_WRITEMASK_XYZ 0x07
91 #define TGSI_WRITEMASK_W 0x08
92 #define TGSI_WRITEMASK_XW 0x09
93 #define TGSI_WRITEMASK_YW 0x0A
94 #define TGSI_WRITEMASK_XYW 0x0B
95 #define TGSI_WRITEMASK_ZW 0x0C
96 #define TGSI_WRITEMASK_XZW 0x0D
97 #define TGSI_WRITEMASK_YZW 0x0E
98 #define TGSI_WRITEMASK_XYZW 0x0F
100 enum tgsi_interpolate_mode
{
101 TGSI_INTERPOLATE_CONSTANT
,
102 TGSI_INTERPOLATE_LINEAR
,
103 TGSI_INTERPOLATE_PERSPECTIVE
,
104 TGSI_INTERPOLATE_COLOR
, /* special color case for smooth/flat */
105 TGSI_INTERPOLATE_COUNT
,
108 enum tgsi_interpolate_loc
{
109 TGSI_INTERPOLATE_LOC_CENTER
,
110 TGSI_INTERPOLATE_LOC_CENTROID
,
111 TGSI_INTERPOLATE_LOC_SAMPLE
,
112 TGSI_INTERPOLATE_LOC_COUNT
,
115 #define TGSI_CYLINDRICAL_WRAP_X (1 << 0)
116 #define TGSI_CYLINDRICAL_WRAP_Y (1 << 1)
117 #define TGSI_CYLINDRICAL_WRAP_Z (1 << 2)
118 #define TGSI_CYLINDRICAL_WRAP_W (1 << 3)
120 enum tgsi_memory_type
{
121 TGSI_MEMORY_TYPE_GLOBAL
, /* OpenCL global */
122 TGSI_MEMORY_TYPE_SHARED
, /* OpenCL local / GLSL shared */
123 TGSI_MEMORY_TYPE_PRIVATE
, /* OpenCL private */
124 TGSI_MEMORY_TYPE_INPUT
, /* OpenCL kernel input params */
125 TGSI_MEMORY_TYPE_COUNT
,
128 struct tgsi_declaration
130 unsigned Type
: 4; /**< TGSI_TOKEN_TYPE_DECLARATION */
131 unsigned NrTokens
: 8; /**< UINT */
132 unsigned File
: 4; /**< one of TGSI_FILE_x */
133 unsigned UsageMask
: 4; /**< bitmask of TGSI_WRITEMASK_x flags */
134 unsigned Dimension
: 1; /**< any extra dimension info? */
135 unsigned Semantic
: 1; /**< BOOL, any semantic info? */
136 unsigned Interpolate
: 1; /**< any interpolation info? */
137 unsigned Invariant
: 1; /**< invariant optimization? */
138 unsigned Local
: 1; /**< optimize as subroutine local variable? */
139 unsigned Array
: 1; /**< extra array info? */
140 unsigned Atomic
: 1; /**< atomic only? for TGSI_FILE_BUFFER */
141 unsigned MemType
: 2; /**< TGSI_MEMORY_TYPE_x for TGSI_FILE_MEMORY */
142 unsigned Padding
: 3;
145 struct tgsi_declaration_range
147 unsigned First
: 16; /**< UINT */
148 unsigned Last
: 16; /**< UINT */
151 struct tgsi_declaration_dimension
153 unsigned Index2D
:16; /**< UINT */
157 struct tgsi_declaration_interp
159 unsigned Interpolate
: 4; /**< one of TGSI_INTERPOLATE_x */
160 unsigned Location
: 2; /**< one of TGSI_INTERPOLATE_LOC_x */
161 unsigned CylindricalWrap
:4; /**< TGSI_CYLINDRICAL_WRAP_x flags */
162 unsigned Padding
: 22;
166 TGSI_SEMANTIC_POSITION
,
168 TGSI_SEMANTIC_BCOLOR
, /**< back-face color */
171 TGSI_SEMANTIC_GENERIC
,
172 TGSI_SEMANTIC_NORMAL
,
174 TGSI_SEMANTIC_EDGEFLAG
,
175 TGSI_SEMANTIC_PRIMID
,
176 TGSI_SEMANTIC_INSTANCEID
, /**< doesn't include start_instance */
177 TGSI_SEMANTIC_VERTEXID
,
178 TGSI_SEMANTIC_STENCIL
,
179 TGSI_SEMANTIC_CLIPDIST
,
180 TGSI_SEMANTIC_CLIPVERTEX
,
181 TGSI_SEMANTIC_GRID_SIZE
, /**< grid size in blocks */
182 TGSI_SEMANTIC_BLOCK_ID
, /**< id of the current block */
183 TGSI_SEMANTIC_BLOCK_SIZE
, /**< block size in threads */
184 TGSI_SEMANTIC_THREAD_ID
, /**< block-relative id of the current thread */
185 TGSI_SEMANTIC_TEXCOORD
, /**< texture or sprite coordinates */
186 TGSI_SEMANTIC_PCOORD
, /**< point sprite coordinate */
187 TGSI_SEMANTIC_VIEWPORT_INDEX
, /**< viewport index */
188 TGSI_SEMANTIC_LAYER
, /**< layer (rendertarget index) */
189 TGSI_SEMANTIC_SAMPLEID
,
190 TGSI_SEMANTIC_SAMPLEPOS
,
191 TGSI_SEMANTIC_SAMPLEMASK
,
192 TGSI_SEMANTIC_INVOCATIONID
,
193 TGSI_SEMANTIC_VERTEXID_NOBASE
,
194 TGSI_SEMANTIC_BASEVERTEX
,
195 TGSI_SEMANTIC_PATCH
, /**< generic per-patch semantic */
196 TGSI_SEMANTIC_TESSCOORD
, /**< coordinate being processed by tess */
197 TGSI_SEMANTIC_TESSOUTER
, /**< outer tessellation levels */
198 TGSI_SEMANTIC_TESSINNER
, /**< inner tessellation levels */
199 TGSI_SEMANTIC_VERTICESIN
, /**< number of input vertices */
200 TGSI_SEMANTIC_HELPER_INVOCATION
, /**< current invocation is helper */
201 TGSI_SEMANTIC_BASEINSTANCE
,
202 TGSI_SEMANTIC_DRAWID
,
203 TGSI_SEMANTIC_WORK_DIM
, /**< opencl get_work_dim value */
204 TGSI_SEMANTIC_SUBGROUP_SIZE
,
205 TGSI_SEMANTIC_SUBGROUP_INVOCATION
,
206 TGSI_SEMANTIC_SUBGROUP_EQ_MASK
,
207 TGSI_SEMANTIC_SUBGROUP_GE_MASK
,
208 TGSI_SEMANTIC_SUBGROUP_GT_MASK
,
209 TGSI_SEMANTIC_SUBGROUP_LE_MASK
,
210 TGSI_SEMANTIC_SUBGROUP_LT_MASK
,
211 TGSI_SEMANTIC_CS_USER_DATA_AMD
,
212 TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL
, /**< from set_tess_state */
213 TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL
, /**< from set_tess_state */
214 TGSI_SEMANTIC_COUNT
, /**< number of semantic values */
217 struct tgsi_declaration_semantic
219 unsigned Name
: 8; /**< one of TGSI_SEMANTIC_x */
220 unsigned Index
: 16; /**< UINT */
221 unsigned StreamX
: 2; /**< vertex stream (for GS output) */
222 unsigned StreamY
: 2;
223 unsigned StreamZ
: 2;
224 unsigned StreamW
: 2;
227 struct tgsi_declaration_image
{
228 unsigned Resource
: 8; /**< one of TGSI_TEXTURE_ */
230 unsigned Writable
: 1;
231 unsigned Format
: 10; /**< one of PIPE_FORMAT_ */
232 unsigned Padding
: 12;
235 enum tgsi_return_type
{
236 TGSI_RETURN_TYPE_UNORM
= 0,
237 TGSI_RETURN_TYPE_SNORM
,
238 TGSI_RETURN_TYPE_SINT
,
239 TGSI_RETURN_TYPE_UINT
,
240 TGSI_RETURN_TYPE_FLOAT
,
241 TGSI_RETURN_TYPE_UNKNOWN
,
242 TGSI_RETURN_TYPE_COUNT
245 struct tgsi_declaration_sampler_view
{
246 unsigned Resource
: 8; /**< one of TGSI_TEXTURE_ */
247 unsigned ReturnTypeX
: 6; /**< one of enum tgsi_return_type */
248 unsigned ReturnTypeY
: 6; /**< one of enum tgsi_return_type */
249 unsigned ReturnTypeZ
: 6; /**< one of enum tgsi_return_type */
250 unsigned ReturnTypeW
: 6; /**< one of enum tgsi_return_type */
253 struct tgsi_declaration_array
{
254 unsigned ArrayID
: 10;
255 unsigned Padding
: 22;
267 struct tgsi_immediate
269 unsigned Type
: 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */
270 unsigned NrTokens
: 14; /**< UINT */
271 unsigned DataType
: 4; /**< one of TGSI_IMM_x */
272 unsigned Padding
: 10;
275 union tgsi_immediate_data
282 enum tgsi_property_name
{
283 TGSI_PROPERTY_GS_INPUT_PRIM
,
284 TGSI_PROPERTY_GS_OUTPUT_PRIM
,
285 TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
,
286 TGSI_PROPERTY_FS_COORD_ORIGIN
,
287 TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
288 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
,
289 TGSI_PROPERTY_FS_DEPTH_LAYOUT
,
290 TGSI_PROPERTY_VS_PROHIBIT_UCPS
,
291 TGSI_PROPERTY_GS_INVOCATIONS
,
292 TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
,
293 TGSI_PROPERTY_TCS_VERTICES_OUT
,
294 TGSI_PROPERTY_TES_PRIM_MODE
,
295 TGSI_PROPERTY_TES_SPACING
,
296 TGSI_PROPERTY_TES_VERTEX_ORDER_CW
,
297 TGSI_PROPERTY_TES_POINT_MODE
,
298 TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
,
299 TGSI_PROPERTY_NUM_CULLDIST_ENABLED
,
300 TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
,
301 TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
,
302 TGSI_PROPERTY_NEXT_SHADER
,
303 TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
304 TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
305 TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
306 TGSI_PROPERTY_MUL_ZERO_WINS
,
307 TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
,
308 TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
,
312 struct tgsi_property
{
313 unsigned Type
: 4; /**< TGSI_TOKEN_TYPE_PROPERTY */
314 unsigned NrTokens
: 8; /**< UINT */
315 unsigned PropertyName
: 8; /**< one of TGSI_PROPERTY */
316 unsigned Padding
: 12;
319 enum tgsi_fs_coord_origin
{
320 TGSI_FS_COORD_ORIGIN_UPPER_LEFT
,
321 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
,
324 enum tgsi_fs_coord_pixcenter
{
325 TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
,
326 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
,
329 enum tgsi_fs_depth_layout
{
330 TGSI_FS_DEPTH_LAYOUT_NONE
,
331 TGSI_FS_DEPTH_LAYOUT_ANY
,
332 TGSI_FS_DEPTH_LAYOUT_GREATER
,
333 TGSI_FS_DEPTH_LAYOUT_LESS
,
334 TGSI_FS_DEPTH_LAYOUT_UNCHANGED
,
337 struct tgsi_property_data
{
343 * For more information on semantics of opcodes and
344 * which APIs are known to use which opcodes, see
345 * gallium/docs/source/tgsi.rst
358 TGSI_OPCODE_DP4
= 10,
359 TGSI_OPCODE_DST
= 11,
360 TGSI_OPCODE_MIN
= 12,
361 TGSI_OPCODE_MAX
= 13,
362 TGSI_OPCODE_SLT
= 14,
363 TGSI_OPCODE_SGE
= 15,
364 TGSI_OPCODE_MAD
= 16,
365 TGSI_OPCODE_TEX_LZ
= 17,
366 TGSI_OPCODE_LRP
= 18,
367 TGSI_OPCODE_FMA
= 19,
368 TGSI_OPCODE_SQRT
= 20,
369 TGSI_OPCODE_LDEXP
= 21,
370 TGSI_OPCODE_F2U64
= 22,
371 TGSI_OPCODE_F2I64
= 23,
372 TGSI_OPCODE_FRC
= 24,
373 TGSI_OPCODE_TXF_LZ
= 25,
374 TGSI_OPCODE_FLR
= 26,
375 TGSI_OPCODE_ROUND
= 27,
376 TGSI_OPCODE_EX2
= 28,
377 TGSI_OPCODE_LG2
= 29,
378 TGSI_OPCODE_POW
= 30,
379 TGSI_OPCODE_DEMOTE
= 31,
380 TGSI_OPCODE_U2I64
= 32,
381 TGSI_OPCODE_CLOCK
= 33,
382 TGSI_OPCODE_I2I64
= 34,
383 TGSI_OPCODE_READ_HELPER
= 35,
384 TGSI_OPCODE_COS
= 36,
385 TGSI_OPCODE_DDX
= 37,
386 TGSI_OPCODE_DDY
= 38,
387 TGSI_OPCODE_KILL
= 39 /* unconditional */,
388 TGSI_OPCODE_PK2H
= 40,
389 TGSI_OPCODE_PK2US
= 41,
390 TGSI_OPCODE_PK4B
= 42,
391 TGSI_OPCODE_PK4UB
= 43,
392 TGSI_OPCODE_D2U64
= 44,
393 TGSI_OPCODE_SEQ
= 45,
394 TGSI_OPCODE_D2I64
= 46,
395 TGSI_OPCODE_SGT
= 47,
396 TGSI_OPCODE_SIN
= 48,
397 TGSI_OPCODE_SLE
= 49,
398 TGSI_OPCODE_SNE
= 50,
399 TGSI_OPCODE_U642D
= 51,
400 TGSI_OPCODE_TEX
= 52,
401 TGSI_OPCODE_TXD
= 53,
402 TGSI_OPCODE_TXP
= 54,
403 TGSI_OPCODE_UP2H
= 55,
404 TGSI_OPCODE_UP2US
= 56,
405 TGSI_OPCODE_UP4B
= 57,
406 TGSI_OPCODE_UP4UB
= 58,
407 TGSI_OPCODE_U642F
= 59,
408 TGSI_OPCODE_I642F
= 60,
409 TGSI_OPCODE_ARR
= 61,
410 TGSI_OPCODE_I642D
= 62,
411 TGSI_OPCODE_CAL
= 63,
412 TGSI_OPCODE_RET
= 64,
413 TGSI_OPCODE_SSG
= 65 /* SGN */,
414 TGSI_OPCODE_CMP
= 66,
416 TGSI_OPCODE_TXB
= 68,
417 TGSI_OPCODE_FBFETCH
= 69,
418 TGSI_OPCODE_DIV
= 70,
419 TGSI_OPCODE_DP2
= 71,
420 TGSI_OPCODE_TXL
= 72,
421 TGSI_OPCODE_BRK
= 73,
423 TGSI_OPCODE_UIF
= 75,
424 TGSI_OPCODE_READ_INVOC
= 76,
425 TGSI_OPCODE_ELSE
= 77,
426 TGSI_OPCODE_ENDIF
= 78,
427 TGSI_OPCODE_DDX_FINE
= 79,
428 TGSI_OPCODE_DDY_FINE
= 80,
430 TGSI_OPCODE_CEIL
= 83,
431 TGSI_OPCODE_I2F
= 84,
432 TGSI_OPCODE_NOT
= 85,
433 TGSI_OPCODE_TRUNC
= 86,
434 TGSI_OPCODE_SHL
= 87,
435 TGSI_OPCODE_BALLOT
= 88,
436 TGSI_OPCODE_AND
= 89,
438 TGSI_OPCODE_MOD
= 91,
439 TGSI_OPCODE_XOR
= 92,
441 TGSI_OPCODE_TXF
= 94,
442 TGSI_OPCODE_TXQ
= 95,
443 TGSI_OPCODE_CONT
= 96,
444 TGSI_OPCODE_EMIT
= 97,
445 TGSI_OPCODE_ENDPRIM
= 98,
446 TGSI_OPCODE_BGNLOOP
= 99,
447 TGSI_OPCODE_BGNSUB
= 100,
448 TGSI_OPCODE_ENDLOOP
= 101,
449 TGSI_OPCODE_ENDSUB
= 102,
450 TGSI_OPCODE_ATOMFADD
= 103,
451 TGSI_OPCODE_TXQS
= 104,
452 TGSI_OPCODE_RESQ
= 105,
453 TGSI_OPCODE_READ_FIRST
= 106,
454 TGSI_OPCODE_NOP
= 107,
456 TGSI_OPCODE_FSEQ
= 108,
457 TGSI_OPCODE_FSGE
= 109,
458 TGSI_OPCODE_FSLT
= 110,
459 TGSI_OPCODE_FSNE
= 111,
461 TGSI_OPCODE_MEMBAR
= 112,
463 TGSI_OPCODE_KILL_IF
= 116 /* conditional kill */,
464 TGSI_OPCODE_END
= 117 /* aka HALT */,
465 TGSI_OPCODE_DFMA
= 118,
466 TGSI_OPCODE_F2I
= 119,
467 TGSI_OPCODE_IDIV
= 120,
468 TGSI_OPCODE_IMAX
= 121,
469 TGSI_OPCODE_IMIN
= 122,
470 TGSI_OPCODE_INEG
= 123,
471 TGSI_OPCODE_ISGE
= 124,
472 TGSI_OPCODE_ISHR
= 125,
473 TGSI_OPCODE_ISLT
= 126,
474 TGSI_OPCODE_F2U
= 127,
475 TGSI_OPCODE_U2F
= 128,
476 TGSI_OPCODE_UADD
= 129,
477 TGSI_OPCODE_UDIV
= 130,
478 TGSI_OPCODE_UMAD
= 131,
479 TGSI_OPCODE_UMAX
= 132,
480 TGSI_OPCODE_UMIN
= 133,
481 TGSI_OPCODE_UMOD
= 134,
482 TGSI_OPCODE_UMUL
= 135,
483 TGSI_OPCODE_USEQ
= 136,
484 TGSI_OPCODE_USGE
= 137,
485 TGSI_OPCODE_USHR
= 138,
486 TGSI_OPCODE_USLT
= 139,
487 TGSI_OPCODE_USNE
= 140,
488 TGSI_OPCODE_SWITCH
= 141,
489 TGSI_OPCODE_CASE
= 142,
490 TGSI_OPCODE_DEFAULT
= 143,
491 TGSI_OPCODE_ENDSWITCH
= 144,
493 /* resource related opcodes */
494 TGSI_OPCODE_SAMPLE
= 145,
495 TGSI_OPCODE_SAMPLE_I
= 146,
496 TGSI_OPCODE_SAMPLE_I_MS
= 147,
497 TGSI_OPCODE_SAMPLE_B
= 148,
498 TGSI_OPCODE_SAMPLE_C
= 149,
499 TGSI_OPCODE_SAMPLE_C_LZ
= 150,
500 TGSI_OPCODE_SAMPLE_D
= 151,
501 TGSI_OPCODE_SAMPLE_L
= 152,
502 TGSI_OPCODE_GATHER4
= 153,
503 TGSI_OPCODE_SVIEWINFO
= 154,
504 TGSI_OPCODE_SAMPLE_POS
= 155,
505 TGSI_OPCODE_SAMPLE_INFO
= 156,
507 TGSI_OPCODE_UARL
= 157,
508 TGSI_OPCODE_UCMP
= 158,
509 TGSI_OPCODE_IABS
= 159,
510 TGSI_OPCODE_ISSG
= 160,
512 TGSI_OPCODE_LOAD
= 161,
513 TGSI_OPCODE_STORE
= 162,
514 TGSI_OPCODE_IMG2HND
= 163,
515 TGSI_OPCODE_SAMP2HND
= 164,
517 TGSI_OPCODE_BARRIER
= 166,
519 TGSI_OPCODE_ATOMUADD
= 167,
520 TGSI_OPCODE_ATOMXCHG
= 168,
521 TGSI_OPCODE_ATOMCAS
= 169,
522 TGSI_OPCODE_ATOMAND
= 170,
523 TGSI_OPCODE_ATOMOR
= 171,
524 TGSI_OPCODE_ATOMXOR
= 172,
525 TGSI_OPCODE_ATOMUMIN
= 173,
526 TGSI_OPCODE_ATOMUMAX
= 174,
527 TGSI_OPCODE_ATOMIMIN
= 175,
528 TGSI_OPCODE_ATOMIMAX
= 176,
530 /* to be used for shadow cube map compares */
531 TGSI_OPCODE_TEX2
= 177,
532 TGSI_OPCODE_TXB2
= 178,
533 TGSI_OPCODE_TXL2
= 179,
535 TGSI_OPCODE_IMUL_HI
= 180,
536 TGSI_OPCODE_UMUL_HI
= 181,
538 TGSI_OPCODE_TG4
= 182,
540 TGSI_OPCODE_LODQ
= 183,
542 TGSI_OPCODE_IBFE
= 184,
543 TGSI_OPCODE_UBFE
= 185,
544 TGSI_OPCODE_BFI
= 186,
545 TGSI_OPCODE_BREV
= 187,
546 TGSI_OPCODE_POPC
= 188,
547 TGSI_OPCODE_LSB
= 189,
548 TGSI_OPCODE_IMSB
= 190,
549 TGSI_OPCODE_UMSB
= 191,
551 TGSI_OPCODE_INTERP_CENTROID
= 192,
552 TGSI_OPCODE_INTERP_SAMPLE
= 193,
553 TGSI_OPCODE_INTERP_OFFSET
= 194,
555 /* sm5 marked opcodes are supported in D3D11 optionally - also DMOV, DMOVC */
556 TGSI_OPCODE_F2D
= 195 /* SM5 */,
557 TGSI_OPCODE_D2F
= 196,
558 TGSI_OPCODE_DABS
= 197,
559 TGSI_OPCODE_DNEG
= 198 /* SM5 */,
560 TGSI_OPCODE_DADD
= 199 /* SM5 */,
561 TGSI_OPCODE_DMUL
= 200 /* SM5 */,
562 TGSI_OPCODE_DMAX
= 201 /* SM5 */,
563 TGSI_OPCODE_DMIN
= 202 /* SM5 */,
564 TGSI_OPCODE_DSLT
= 203 /* SM5 */,
565 TGSI_OPCODE_DSGE
= 204 /* SM5 */,
566 TGSI_OPCODE_DSEQ
= 205 /* SM5 */,
567 TGSI_OPCODE_DSNE
= 206 /* SM5 */,
568 TGSI_OPCODE_DRCP
= 207 /* eg, cayman */,
569 TGSI_OPCODE_DSQRT
= 208 /* eg, cayman also has DRSQ */,
570 TGSI_OPCODE_DMAD
= 209,
571 TGSI_OPCODE_DFRAC
= 210 /* eg, cayman */,
572 TGSI_OPCODE_DLDEXP
= 211 /* eg, cayman */,
573 TGSI_OPCODE_DFRACEXP
= 212 /* eg, cayman */,
574 TGSI_OPCODE_D2I
= 213,
575 TGSI_OPCODE_I2D
= 214,
576 TGSI_OPCODE_D2U
= 215,
577 TGSI_OPCODE_U2D
= 216,
578 TGSI_OPCODE_DRSQ
= 217 /* eg, cayman also has DRSQ */,
579 TGSI_OPCODE_DTRUNC
= 218 /* nvc0 */,
580 TGSI_OPCODE_DCEIL
= 219 /* nvc0 */,
581 TGSI_OPCODE_DFLR
= 220 /* nvc0 */,
582 TGSI_OPCODE_DROUND
= 221 /* nvc0 */,
583 TGSI_OPCODE_DSSG
= 222,
585 TGSI_OPCODE_VOTE_ANY
= 223,
586 TGSI_OPCODE_VOTE_ALL
= 224,
587 TGSI_OPCODE_VOTE_EQ
= 225,
589 TGSI_OPCODE_U64SEQ
= 226,
590 TGSI_OPCODE_U64SNE
= 227,
591 TGSI_OPCODE_I64SLT
= 228,
592 TGSI_OPCODE_U64SLT
= 229,
593 TGSI_OPCODE_I64SGE
= 230,
594 TGSI_OPCODE_U64SGE
= 231,
596 TGSI_OPCODE_I64MIN
= 232,
597 TGSI_OPCODE_U64MIN
= 233,
598 TGSI_OPCODE_I64MAX
= 234,
599 TGSI_OPCODE_U64MAX
= 235,
601 TGSI_OPCODE_I64ABS
= 236,
602 TGSI_OPCODE_I64SSG
= 237,
603 TGSI_OPCODE_I64NEG
= 238,
605 TGSI_OPCODE_U64ADD
= 239,
606 TGSI_OPCODE_U64MUL
= 240,
607 TGSI_OPCODE_U64SHL
= 241,
608 TGSI_OPCODE_I64SHR
= 242,
609 TGSI_OPCODE_U64SHR
= 243,
611 TGSI_OPCODE_I64DIV
= 244,
612 TGSI_OPCODE_U64DIV
= 245,
613 TGSI_OPCODE_I64MOD
= 246,
614 TGSI_OPCODE_U64MOD
= 247,
616 TGSI_OPCODE_DDIV
= 248,
618 TGSI_OPCODE_LOD
= 249,
620 TGSI_OPCODE_ATOMINC_WRAP
= 250,
621 TGSI_OPCODE_ATOMDEC_WRAP
= 251,
623 TGSI_OPCODE_LAST
= 252,
628 * Opcode is the operation code to execute. A given operation defines the
629 * semantics how the source registers (if any) are interpreted and what is
630 * written to the destination registers (if any) as a result of execution.
632 * NumDstRegs and NumSrcRegs is the number of destination and source registers,
633 * respectively. For a given operation code, those numbers are fixed and are
634 * present here only for convenience.
636 * Saturate controls how are final results in destination registers modified.
639 struct tgsi_instruction
641 unsigned Type
: 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */
642 unsigned NrTokens
: 8; /* UINT */
643 unsigned Opcode
: 8; /* TGSI_OPCODE_ */
644 unsigned Saturate
: 1; /* BOOL */
645 unsigned NumDstRegs
: 2; /* UINT */
646 unsigned NumSrcRegs
: 4; /* UINT */
648 unsigned Texture
: 1;
650 unsigned Precise
: 1;
651 unsigned Padding
: 1;
655 * If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows.
657 * If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows.
658 * if texture instruction has a number of offsets,
659 * then tgsi_instruction::Texture::NumOffset of tgsi_texture_offset follow.
661 * Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow.
663 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow.
665 * tgsi_instruction::NrTokens contains the total number of words that make the
666 * instruction, including the instruction word.
676 struct tgsi_instruction_label
678 unsigned Label
: 24; /* UINT */
679 unsigned Padding
: 8;
682 enum tgsi_texture_type
{
689 TGSI_TEXTURE_SHADOW1D
,
690 TGSI_TEXTURE_SHADOW2D
,
691 TGSI_TEXTURE_SHADOWRECT
,
692 TGSI_TEXTURE_1D_ARRAY
,
693 TGSI_TEXTURE_2D_ARRAY
,
694 TGSI_TEXTURE_SHADOW1D_ARRAY
,
695 TGSI_TEXTURE_SHADOW2D_ARRAY
,
696 TGSI_TEXTURE_SHADOWCUBE
,
697 TGSI_TEXTURE_2D_MSAA
,
698 TGSI_TEXTURE_2D_ARRAY_MSAA
,
699 TGSI_TEXTURE_CUBE_ARRAY
,
700 TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
701 TGSI_TEXTURE_UNKNOWN
,
705 struct tgsi_instruction_texture
707 unsigned Texture
: 8; /* TGSI_TEXTURE_ */
708 unsigned NumOffsets
: 4;
709 unsigned ReturnType
: 3; /* TGSI_RETURN_TYPE_x */
710 unsigned Padding
: 17;
713 /* for texture offsets in GLSL and DirectX.
714 * Generally these always come from TGSI_FILE_IMMEDIATE,
715 * however DX11 appears to have the capability to do
716 * non-constant texture offsets.
718 struct tgsi_texture_offset
721 unsigned File
: 4; /**< one of TGSI_FILE_x */
722 unsigned SwizzleX
: 2; /* TGSI_SWIZZLE_x */
723 unsigned SwizzleY
: 2; /* TGSI_SWIZZLE_x */
724 unsigned SwizzleZ
: 2; /* TGSI_SWIZZLE_x */
725 unsigned Padding
: 6;
729 * File specifies the register array to access.
731 * Index specifies the element number of a register in the register file.
733 * If Indirect is TRUE, Index should be offset by the X component of the indirect
734 * register that follows. The register can be now fetched into local storage
735 * for further processing.
737 * If Negate is TRUE, all components of the fetched register are negated.
739 * The fetched register components are swizzled according to SwizzleX, SwizzleY,
740 * SwizzleZ and SwizzleW.
744 struct tgsi_src_register
746 unsigned File
: 4; /* TGSI_FILE_ */
747 unsigned Indirect
: 1; /* BOOL */
748 unsigned Dimension
: 1; /* BOOL */
749 int Index
: 16; /* SINT */
750 unsigned SwizzleX
: 2; /* TGSI_SWIZZLE_ */
751 unsigned SwizzleY
: 2; /* TGSI_SWIZZLE_ */
752 unsigned SwizzleZ
: 2; /* TGSI_SWIZZLE_ */
753 unsigned SwizzleW
: 2; /* TGSI_SWIZZLE_ */
754 unsigned Absolute
: 1; /* BOOL */
755 unsigned Negate
: 1; /* BOOL */
759 * If tgsi_src_register::Indirect is TRUE, tgsi_ind_register follows.
761 * File, Index and Swizzle are handled the same as in tgsi_src_register.
763 * If ArrayID is zero the whole register file might be indirectly addressed,
764 * if not only the Declaration with this ArrayID is accessed by this operand.
768 struct tgsi_ind_register
770 unsigned File
: 4; /* TGSI_FILE_ */
771 int Index
: 16; /* SINT */
772 unsigned Swizzle
: 2; /* TGSI_SWIZZLE_ */
773 unsigned ArrayID
: 10; /* UINT */
777 * If tgsi_src_register::Dimension is TRUE, tgsi_dimension follows.
780 struct tgsi_dimension
782 unsigned Indirect
: 1; /* BOOL */
783 unsigned Dimension
: 1; /* BOOL */
784 unsigned Padding
: 14;
785 int Index
: 16; /* SINT */
788 struct tgsi_dst_register
790 unsigned File
: 4; /* TGSI_FILE_ */
791 unsigned WriteMask
: 4; /* TGSI_WRITEMASK_ */
792 unsigned Indirect
: 1; /* BOOL */
793 unsigned Dimension
: 1; /* BOOL */
794 int Index
: 16; /* SINT */
795 unsigned Padding
: 6;
798 #define TGSI_MEMORY_COHERENT (1 << 0)
799 #define TGSI_MEMORY_RESTRICT (1 << 1)
800 #define TGSI_MEMORY_VOLATILE (1 << 2)
801 /* The "stream" cache policy will minimize memory cache usage if other
802 * memory operations need the cache.
804 #define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3)
807 * Specifies the type of memory access to do for the LOAD/STORE instruction.
809 struct tgsi_instruction_memory
811 unsigned Qualifier
: 4; /* TGSI_MEMORY_ */
812 unsigned Texture
: 8; /* only for images: TGSI_TEXTURE_ */
813 unsigned Format
: 10; /* only for images: PIPE_FORMAT_ */
814 unsigned Padding
: 10;
817 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0)
818 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1)
819 #define TGSI_MEMBAR_SHADER_IMAGE (1 << 2)
820 #define TGSI_MEMBAR_SHARED (1 << 3)
821 #define TGSI_MEMBAR_THREAD_GROUP (1 << 4)
827 #endif /* P_SHADER_TOKENS_H */