2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
41 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
42 #define DEBUG_SPARSE_COMMITS 0
44 struct amdgpu_sparse_backing_chunk
{
48 static struct pb_buffer
*
49 amdgpu_bo_create(struct radeon_winsys
*rws
,
52 enum radeon_bo_domain domain
,
53 enum radeon_bo_flag flags
);
55 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
56 enum radeon_bo_usage usage
)
58 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
59 struct amdgpu_winsys
*ws
= bo
->ws
;
63 if (p_atomic_read(&bo
->num_active_ioctls
))
67 abs_timeout
= os_time_get_absolute_timeout(timeout
);
69 /* Wait if any ioctl is being submitted with this buffer. */
70 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
75 /* We can't use user fences for shared buffers, because user fences
76 * are local to this process only. If we want to wait for all buffer
77 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
79 bool buffer_busy
= true;
82 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
84 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
93 mtx_lock(&ws
->bo_fence_lock
);
95 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
96 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
100 /* Release the idle fences to avoid checking them again later. */
101 for (unsigned i
= 0; i
< idle_fences
; ++i
)
102 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
104 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
105 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
106 bo
->num_fences
-= idle_fences
;
108 buffer_idle
= !bo
->num_fences
;
109 mtx_unlock(&ws
->bo_fence_lock
);
113 bool buffer_idle
= true;
115 mtx_lock(&ws
->bo_fence_lock
);
116 while (bo
->num_fences
&& buffer_idle
) {
117 struct pipe_fence_handle
*fence
= NULL
;
118 bool fence_idle
= false;
120 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
122 /* Wait for the fence. */
123 mtx_unlock(&ws
->bo_fence_lock
);
124 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
128 mtx_lock(&ws
->bo_fence_lock
);
130 /* Release an idle fence to avoid checking it again later, keeping in
131 * mind that the fence array may have been modified by other threads.
133 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
134 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
135 memmove(&bo
->fences
[0], &bo
->fences
[1],
136 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
140 amdgpu_fence_reference(&fence
, NULL
);
142 mtx_unlock(&ws
->bo_fence_lock
);
148 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
149 struct pb_buffer
*buf
)
151 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
154 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
156 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
157 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
164 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
166 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
168 assert(bo
->bo
&& "must not be called for slab entries");
170 if (bo
->ws
->debug_all_bos
) {
171 mtx_lock(&bo
->ws
->global_bo_list_lock
);
172 LIST_DEL(&bo
->u
.real
.global_list_item
);
173 bo
->ws
->num_buffers
--;
174 mtx_unlock(&bo
->ws
->global_bo_list_lock
);
177 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
178 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
179 amdgpu_bo_free(bo
->bo
);
181 amdgpu_bo_remove_fences(bo
);
183 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
184 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
185 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
186 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
188 if (bo
->u
.real
.map_count
>= 1) {
189 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
190 bo
->ws
->mapped_vram
-= bo
->base
.size
;
191 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
192 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
193 bo
->ws
->num_mapped_buffers
--;
199 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
201 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
203 assert(bo
->bo
); /* slab buffers have a separate vtbl */
205 if (bo
->u
.real
.use_reusable_pool
)
206 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
208 amdgpu_bo_destroy(_buf
);
211 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
212 struct radeon_winsys_cs
*rcs
,
213 enum pipe_transfer_usage usage
)
215 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
216 struct amdgpu_winsys_bo
*real
;
217 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
224 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
225 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
226 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
227 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
228 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
231 * Since we are mapping for read, we don't need to wait
232 * if the GPU is using the buffer for read too
233 * (neither one is changing it).
235 * Only check whether the buffer is being used for write. */
236 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
237 RADEON_USAGE_WRITE
)) {
238 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
242 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
243 RADEON_USAGE_WRITE
)) {
247 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
248 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
252 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
253 RADEON_USAGE_READWRITE
)) {
258 uint64_t time
= os_time_get_nano();
260 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
263 * Since we are mapping for read, we don't need to wait
264 * if the GPU is using the buffer for read too
265 * (neither one is changing it).
267 * Only check whether the buffer is being used for write. */
269 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
270 RADEON_USAGE_WRITE
)) {
271 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
273 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
274 if (p_atomic_read(&bo
->num_active_ioctls
))
275 amdgpu_cs_sync_flush(rcs
);
279 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
282 /* Mapping for write. */
284 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
285 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
287 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
288 if (p_atomic_read(&bo
->num_active_ioctls
))
289 amdgpu_cs_sync_flush(rcs
);
293 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
294 RADEON_USAGE_READWRITE
);
297 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
301 /* If the buffer is created from user memory, return the user pointer. */
308 real
= bo
->u
.slab
.real
;
309 offset
= bo
->va
- real
->va
;
312 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
314 /* Clear the cache and try again. */
315 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
316 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
321 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
322 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
323 real
->ws
->mapped_vram
+= real
->base
.size
;
324 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
325 real
->ws
->mapped_gtt
+= real
->base
.size
;
326 real
->ws
->num_mapped_buffers
++;
328 return (uint8_t*)cpu
+ offset
;
331 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
333 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
334 struct amdgpu_winsys_bo
*real
;
341 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
343 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
344 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
345 real
->ws
->mapped_vram
-= real
->base
.size
;
346 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
347 real
->ws
->mapped_gtt
-= real
->base
.size
;
348 real
->ws
->num_mapped_buffers
--;
351 amdgpu_bo_cpu_unmap(real
->bo
);
354 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
355 amdgpu_bo_destroy_or_cache
356 /* other functions are never called */
359 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
361 struct amdgpu_winsys
*ws
= bo
->ws
;
365 if (ws
->debug_all_bos
) {
366 mtx_lock(&ws
->global_bo_list_lock
);
367 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
369 mtx_unlock(&ws
->global_bo_list_lock
);
373 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
377 enum radeon_bo_domain initial_domain
,
379 unsigned pb_cache_bucket
)
381 struct amdgpu_bo_alloc_request request
= {0};
382 amdgpu_bo_handle buf_handle
;
384 struct amdgpu_winsys_bo
*bo
;
385 amdgpu_va_handle va_handle
;
386 unsigned va_gap_size
;
389 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
390 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
395 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
397 request
.alloc_size
= size
;
398 request
.phys_alignment
= alignment
;
400 if (initial_domain
& RADEON_DOMAIN_VRAM
)
401 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
402 if (initial_domain
& RADEON_DOMAIN_GTT
)
403 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
405 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
406 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
407 if (flags
& RADEON_FLAG_GTT_WC
)
408 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
410 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
412 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
413 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
414 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
415 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
419 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
420 if (size
> ws
->info
.pte_fragment_size
)
421 alignment
= MAX2(alignment
, ws
->info
.pte_fragment_size
);
422 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
423 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
427 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
431 pipe_reference_init(&bo
->base
.reference
, 1);
432 bo
->base
.alignment
= alignment
;
433 bo
->base
.usage
= usage
;
434 bo
->base
.size
= size
;
435 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
439 bo
->u
.real
.va_handle
= va_handle
;
440 bo
->initial_domain
= initial_domain
;
441 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
443 if (initial_domain
& RADEON_DOMAIN_VRAM
)
444 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
445 else if (initial_domain
& RADEON_DOMAIN_GTT
)
446 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
448 amdgpu_add_buffer_to_global_list(bo
);
453 amdgpu_va_range_free(va_handle
);
456 amdgpu_bo_free(buf_handle
);
463 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
465 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
467 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
471 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
474 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
476 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
477 bo
= container_of(entry
, bo
, u
.slab
.entry
);
479 return amdgpu_bo_can_reclaim(&bo
->base
);
482 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
484 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
488 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
491 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
492 amdgpu_bo_slab_destroy
493 /* other functions are never called */
496 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
498 unsigned group_index
)
500 struct amdgpu_winsys
*ws
= priv
;
501 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
502 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
503 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
509 unsigned slab_size
= 1 << AMDGPU_SLAB_BO_SIZE_LOG2
;
510 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
511 slab_size
, slab_size
,
516 assert(slab
->buffer
->bo
);
518 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
519 slab
->base
.num_free
= slab
->base
.num_entries
;
520 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
524 LIST_INITHEAD(&slab
->base
.free
);
526 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
528 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
529 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
531 bo
->base
.alignment
= entry_size
;
532 bo
->base
.usage
= slab
->buffer
->base
.usage
;
533 bo
->base
.size
= entry_size
;
534 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
536 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
537 bo
->initial_domain
= domains
;
538 bo
->unique_id
= base_id
+ i
;
539 bo
->u
.slab
.entry
.slab
= &slab
->base
;
540 bo
->u
.slab
.entry
.group_index
= group_index
;
541 bo
->u
.slab
.real
= slab
->buffer
;
543 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
549 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
555 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
557 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
559 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
560 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
563 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
567 #if DEBUG_SPARSE_COMMITS
569 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
571 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
573 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
575 struct amdgpu_sparse_backing
*span_backing
= NULL
;
576 uint32_t span_first_backing_page
= 0;
577 uint32_t span_first_va_page
= 0;
578 uint32_t va_page
= 0;
581 struct amdgpu_sparse_backing
*backing
= 0;
582 uint32_t backing_page
= 0;
584 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
585 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
586 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
590 (backing
!= span_backing
||
591 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
592 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
593 span_first_va_page
, va_page
- 1, span_backing
,
594 span_first_backing_page
,
595 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
600 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
603 if (backing
&& !span_backing
) {
604 span_backing
= backing
;
605 span_first_backing_page
= backing_page
;
606 span_first_va_page
= va_page
;
612 fprintf(stderr
, "Backing:\n");
614 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
615 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
616 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
617 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
623 * Attempt to allocate the given number of backing pages. Fewer pages may be
624 * allocated (depending on the fragmentation of existing backing buffers),
625 * which will be reflected by a change to *pnum_pages.
627 static struct amdgpu_sparse_backing
*
628 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
630 struct amdgpu_sparse_backing
*best_backing
;
632 uint32_t best_num_pages
;
638 /* This is a very simple and inefficient best-fit algorithm. */
639 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
640 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
641 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
642 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
643 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
644 best_backing
= backing
;
646 best_num_pages
= cur_num_pages
;
651 /* Allocate a new backing buffer if necessary. */
653 struct pb_buffer
*buf
;
657 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
661 best_backing
->max_chunks
= 4;
662 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
663 sizeof(*best_backing
->chunks
));
664 if (!best_backing
->chunks
) {
669 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
671 size
= MIN3(bo
->base
.size
/ 16,
673 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
674 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
676 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
678 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
680 FREE(best_backing
->chunks
);
685 /* We might have gotten a bigger buffer than requested via caching. */
686 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
688 best_backing
->bo
= amdgpu_winsys_bo(buf
);
689 best_backing
->num_chunks
= 1;
690 best_backing
->chunks
[0].begin
= 0;
691 best_backing
->chunks
[0].end
= pages
;
693 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
694 bo
->u
.sparse
.num_backing_pages
+= pages
;
697 best_num_pages
= pages
;
700 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
701 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
702 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
704 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
705 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
706 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
707 best_backing
->num_chunks
--;
714 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
715 struct amdgpu_sparse_backing
*backing
)
717 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
719 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
721 mtx_lock(&ws
->bo_fence_lock
);
722 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
723 mtx_unlock(&ws
->bo_fence_lock
);
725 list_del(&backing
->list
);
726 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
727 FREE(backing
->chunks
);
732 * Return a range of pages from the given backing buffer back into the
736 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
737 struct amdgpu_sparse_backing
*backing
,
738 uint32_t start_page
, uint32_t num_pages
)
740 uint32_t end_page
= start_page
+ num_pages
;
742 unsigned high
= backing
->num_chunks
;
744 /* Find the first chunk with begin >= start_page. */
746 unsigned mid
= low
+ (high
- low
) / 2;
748 if (backing
->chunks
[mid
].begin
>= start_page
)
754 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
755 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
757 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
758 backing
->chunks
[low
- 1].end
= end_page
;
760 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
761 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
762 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
763 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
764 backing
->num_chunks
--;
766 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
767 backing
->chunks
[low
].begin
= start_page
;
769 if (backing
->num_chunks
>= backing
->max_chunks
) {
770 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
771 struct amdgpu_sparse_backing_chunk
*new_chunks
=
772 REALLOC(backing
->chunks
,
773 sizeof(*backing
->chunks
) * backing
->max_chunks
,
774 sizeof(*backing
->chunks
) * new_max_chunks
);
778 backing
->max_chunks
= new_max_chunks
;
779 backing
->chunks
= new_chunks
;
782 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
783 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
784 backing
->chunks
[low
].begin
= start_page
;
785 backing
->chunks
[low
].end
= end_page
;
786 backing
->num_chunks
++;
789 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
790 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
791 sparse_free_backing_buffer(bo
, backing
);
796 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
798 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
801 assert(!bo
->bo
&& bo
->sparse
);
803 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
804 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
805 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
807 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
810 while (!list_empty(&bo
->u
.sparse
.backing
)) {
811 struct amdgpu_sparse_backing
*dummy
= NULL
;
812 sparse_free_backing_buffer(bo
,
813 container_of(bo
->u
.sparse
.backing
.next
,
817 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
818 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
819 FREE(bo
->u
.sparse
.commitments
);
823 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
824 amdgpu_bo_sparse_destroy
825 /* other functions are never called */
828 static struct pb_buffer
*
829 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
830 enum radeon_bo_domain domain
,
831 enum radeon_bo_flag flags
)
833 struct amdgpu_winsys_bo
*bo
;
835 uint64_t va_gap_size
;
838 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
839 * that exceed this limit. This is not really a restriction: we don't have
840 * that much virtual address space anyway.
842 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
845 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
849 pipe_reference_init(&bo
->base
.reference
, 1);
850 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
851 bo
->base
.size
= size
;
852 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
854 bo
->initial_domain
= domain
;
855 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
857 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
859 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
860 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
861 sizeof(*bo
->u
.sparse
.commitments
));
862 if (!bo
->u
.sparse
.commitments
)
863 goto error_alloc_commitments
;
865 mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
866 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
868 /* For simplicity, we always map a multiple of the page size. */
869 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
870 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
871 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
872 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
873 0, &bo
->va
, &bo
->u
.sparse
.va_handle
, 0);
877 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
878 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
885 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
887 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
888 FREE(bo
->u
.sparse
.commitments
);
889 error_alloc_commitments
:
895 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
898 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
899 struct amdgpu_sparse_commitment
*comm
;
900 uint32_t va_page
, end_va_page
;
905 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
906 assert(offset
<= bo
->base
.size
);
907 assert(size
<= bo
->base
.size
- offset
);
908 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
910 comm
= bo
->u
.sparse
.commitments
;
911 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
912 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
914 mtx_lock(&bo
->u
.sparse
.commit_lock
);
916 #if DEBUG_SPARSE_COMMITS
917 sparse_dump(bo
, __func__
);
921 while (va_page
< end_va_page
) {
922 uint32_t span_va_page
;
924 /* Skip pages that are already committed. */
925 if (comm
[va_page
].backing
) {
930 /* Determine length of uncommitted span. */
931 span_va_page
= va_page
;
932 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
935 /* Fill the uncommitted span with chunks of backing memory. */
936 while (span_va_page
< va_page
) {
937 struct amdgpu_sparse_backing
*backing
;
938 uint32_t backing_start
, backing_size
;
940 backing_size
= va_page
- span_va_page
;
941 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
947 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
948 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
949 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
950 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
951 AMDGPU_VM_PAGE_READABLE
|
952 AMDGPU_VM_PAGE_WRITEABLE
|
953 AMDGPU_VM_PAGE_EXECUTABLE
,
954 AMDGPU_VA_OP_REPLACE
);
956 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
957 assert(ok
&& "sufficient memory should already be allocated");
963 while (backing_size
) {
964 comm
[span_va_page
].backing
= backing
;
965 comm
[span_va_page
].page
= backing_start
;
973 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
974 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
975 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
976 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
982 while (va_page
< end_va_page
) {
983 struct amdgpu_sparse_backing
*backing
;
984 uint32_t backing_start
;
987 /* Skip pages that are already uncommitted. */
988 if (!comm
[va_page
].backing
) {
993 /* Group contiguous spans of pages. */
994 backing
= comm
[va_page
].backing
;
995 backing_start
= comm
[va_page
].page
;
996 comm
[va_page
].backing
= NULL
;
1001 while (va_page
< end_va_page
&&
1002 comm
[va_page
].backing
== backing
&&
1003 comm
[va_page
].page
== backing_start
+ span_pages
) {
1004 comm
[va_page
].backing
= NULL
;
1009 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1010 /* Couldn't allocate tracking data structures, so we have to leak */
1011 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1018 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1023 static unsigned eg_tile_split(unsigned tile_split
)
1025 switch (tile_split
) {
1026 case 0: tile_split
= 64; break;
1027 case 1: tile_split
= 128; break;
1028 case 2: tile_split
= 256; break;
1029 case 3: tile_split
= 512; break;
1031 case 4: tile_split
= 1024; break;
1032 case 5: tile_split
= 2048; break;
1033 case 6: tile_split
= 4096; break;
1038 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1040 switch (eg_tile_split
) {
1046 case 1024: return 4;
1047 case 2048: return 5;
1048 case 4096: return 6;
1052 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1053 struct radeon_bo_metadata
*md
)
1055 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1056 struct amdgpu_bo_info info
= {0};
1057 uint64_t tiling_flags
;
1060 assert(bo
->bo
&& "must not be called for slab entries");
1062 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1066 tiling_flags
= info
.metadata
.tiling_info
;
1068 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1069 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1071 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1072 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1074 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1075 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1076 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1077 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1079 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1080 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1081 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1082 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1083 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1084 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1085 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1088 md
->size_metadata
= info
.metadata
.size_metadata
;
1089 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1092 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1093 struct radeon_bo_metadata
*md
)
1095 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1096 struct amdgpu_bo_metadata metadata
= {0};
1097 uint64_t tiling_flags
= 0;
1099 assert(bo
->bo
&& "must not be called for slab entries");
1101 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1102 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1104 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1105 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1106 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1107 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1109 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1111 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1112 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1113 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1114 if (md
->u
.legacy
.tile_split
)
1115 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1116 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1117 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1119 if (md
->u
.legacy
.scanout
)
1120 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1122 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1125 metadata
.tiling_info
= tiling_flags
;
1126 metadata
.size_metadata
= md
->size_metadata
;
1127 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1129 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1132 static struct pb_buffer
*
1133 amdgpu_bo_create(struct radeon_winsys
*rws
,
1136 enum radeon_bo_domain domain
,
1137 enum radeon_bo_flag flags
)
1139 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1140 struct amdgpu_winsys_bo
*bo
;
1141 unsigned usage
= 0, pb_cache_bucket
;
1143 /* VRAM implies WC. This is not optional. */
1144 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1146 /* NO_CPU_ACCESS is valid with VRAM only. */
1147 assert(domain
== RADEON_DOMAIN_VRAM
|| !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1149 /* Sub-allocate small buffers from slabs. */
1150 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1151 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1152 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1153 struct pb_slab_entry
*entry
;
1154 int heap
= radeon_get_heap_index(domain
, flags
);
1156 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1159 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1161 /* Clear the cache and try again. */
1162 pb_cache_release_all_buffers(&ws
->bo_cache
);
1164 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1170 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1172 pipe_reference_init(&bo
->base
.reference
, 1);
1178 if (flags
& RADEON_FLAG_SPARSE
) {
1179 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1181 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1183 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1186 /* This flag is irrelevant for the cache. */
1187 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1189 /* Align size to page size. This is the minimum alignment for normal
1190 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1191 * like constant/uniform buffers, can benefit from better and more reuse.
1193 size
= align64(size
, ws
->info
.gart_page_size
);
1194 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1196 int heap
= radeon_get_heap_index(domain
, flags
);
1197 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1198 usage
= 1 << heap
; /* Only set one usage bit for each heap. */
1200 pb_cache_bucket
= radeon_get_pb_cache_bucket_index(heap
);
1201 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
1203 /* Get a buffer from the cache. */
1204 bo
= (struct amdgpu_winsys_bo
*)
1205 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
1210 /* Create a new one. */
1211 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1214 /* Clear the cache and try again. */
1215 pb_slabs_reclaim(&ws
->bo_slabs
);
1216 pb_cache_release_all_buffers(&ws
->bo_cache
);
1217 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1223 bo
->u
.real
.use_reusable_pool
= true;
1227 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1228 struct winsys_handle
*whandle
,
1232 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1233 struct amdgpu_winsys_bo
*bo
;
1234 enum amdgpu_bo_handle_type type
;
1235 struct amdgpu_bo_import_result result
= {0};
1237 amdgpu_va_handle va_handle
;
1238 struct amdgpu_bo_info info
= {0};
1239 enum radeon_bo_domain initial
= 0;
1242 /* Initialize the structure. */
1243 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1248 switch (whandle
->type
) {
1249 case DRM_API_HANDLE_TYPE_SHARED
:
1250 type
= amdgpu_bo_handle_type_gem_flink_name
;
1252 case DRM_API_HANDLE_TYPE_FD
:
1253 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1259 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1263 /* Get initial domains. */
1264 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1268 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1269 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
1273 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1277 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1278 initial
|= RADEON_DOMAIN_VRAM
;
1279 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1280 initial
|= RADEON_DOMAIN_GTT
;
1283 pipe_reference_init(&bo
->base
.reference
, 1);
1284 bo
->base
.alignment
= info
.phys_alignment
;
1285 bo
->bo
= result
.buf_handle
;
1286 bo
->base
.size
= result
.alloc_size
;
1287 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1290 bo
->u
.real
.va_handle
= va_handle
;
1291 bo
->initial_domain
= initial
;
1292 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1293 bo
->is_shared
= true;
1296 *stride
= whandle
->stride
;
1298 *offset
= whandle
->offset
;
1300 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1301 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1302 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1303 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1305 amdgpu_add_buffer_to_global_list(bo
);
1310 amdgpu_va_range_free(va_handle
);
1313 amdgpu_bo_free(result
.buf_handle
);
1320 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1321 unsigned stride
, unsigned offset
,
1322 unsigned slice_size
,
1323 struct winsys_handle
*whandle
)
1325 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1326 enum amdgpu_bo_handle_type type
;
1329 /* Don't allow exports of slab entries and sparse buffers. */
1333 bo
->u
.real
.use_reusable_pool
= false;
1335 switch (whandle
->type
) {
1336 case DRM_API_HANDLE_TYPE_SHARED
:
1337 type
= amdgpu_bo_handle_type_gem_flink_name
;
1339 case DRM_API_HANDLE_TYPE_FD
:
1340 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1342 case DRM_API_HANDLE_TYPE_KMS
:
1343 type
= amdgpu_bo_handle_type_kms
;
1349 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1353 whandle
->stride
= stride
;
1354 whandle
->offset
= offset
;
1355 whandle
->offset
+= slice_size
* whandle
->layer
;
1356 bo
->is_shared
= true;
1360 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1361 void *pointer
, uint64_t size
)
1363 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1364 amdgpu_bo_handle buf_handle
;
1365 struct amdgpu_winsys_bo
*bo
;
1367 amdgpu_va_handle va_handle
;
1369 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1373 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
1376 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1377 size
, 1 << 12, 0, &va
, &va_handle
, 0))
1378 goto error_va_alloc
;
1380 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
1383 /* Initialize it. */
1384 pipe_reference_init(&bo
->base
.reference
, 1);
1385 bo
->bo
= buf_handle
;
1386 bo
->base
.alignment
= 0;
1387 bo
->base
.size
= size
;
1388 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1390 bo
->user_ptr
= pointer
;
1392 bo
->u
.real
.va_handle
= va_handle
;
1393 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1394 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1396 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1398 amdgpu_add_buffer_to_global_list(bo
);
1400 return (struct pb_buffer
*)bo
;
1403 amdgpu_va_range_free(va_handle
);
1406 amdgpu_bo_free(buf_handle
);
1413 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1415 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1418 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1420 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1422 return !bo
->bo
&& !bo
->sparse
;
1425 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1427 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1430 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1432 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1433 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1434 ws
->base
.buffer_map
= amdgpu_bo_map
;
1435 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1436 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1437 ws
->base
.buffer_create
= amdgpu_bo_create
;
1438 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1439 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1440 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1441 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1442 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1443 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1444 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1445 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;