2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
41 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
42 enum radeon_bo_usage usage
)
44 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
45 struct amdgpu_winsys
*ws
= bo
->ws
;
50 if (p_atomic_read(&bo
->num_active_ioctls
))
54 abs_timeout
= os_time_get_absolute_timeout(timeout
);
56 /* Wait if any ioctl is being submitted with this buffer. */
57 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
62 /* We can't use user fences for shared buffers, because user fences
63 * are local to this process only. If we want to wait for all buffer
64 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
66 bool buffer_busy
= true;
69 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
71 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
77 pipe_mutex_lock(ws
->bo_fence_lock
);
78 for (i
= 0; i
< RING_LAST
; i
++)
80 if (amdgpu_fence_wait(bo
->fence
[i
], 0, false)) {
81 /* Release the idle fence to avoid checking it again later. */
82 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
84 pipe_mutex_unlock(ws
->bo_fence_lock
);
88 pipe_mutex_unlock(ws
->bo_fence_lock
);
92 struct pipe_fence_handle
*fence
[RING_LAST
] = {};
93 bool fence_idle
[RING_LAST
] = {};
94 bool buffer_idle
= true;
96 /* Take references to all fences, so that we can wait for them
97 * without the lock. */
98 pipe_mutex_lock(ws
->bo_fence_lock
);
99 for (i
= 0; i
< RING_LAST
; i
++)
100 amdgpu_fence_reference(&fence
[i
], bo
->fence
[i
]);
101 pipe_mutex_unlock(ws
->bo_fence_lock
);
103 /* Now wait for the fences. */
104 for (i
= 0; i
< RING_LAST
; i
++) {
106 if (amdgpu_fence_wait(fence
[i
], abs_timeout
, true))
107 fence_idle
[i
] = true;
113 /* Release idle fences to avoid checking them again later. */
114 pipe_mutex_lock(ws
->bo_fence_lock
);
115 for (i
= 0; i
< RING_LAST
; i
++) {
116 if (fence
[i
] == bo
->fence
[i
] && fence_idle
[i
])
117 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
119 amdgpu_fence_reference(&fence
[i
], NULL
);
121 pipe_mutex_unlock(ws
->bo_fence_lock
);
127 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
128 struct pb_buffer
*buf
)
130 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
133 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
135 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
138 pipe_mutex_lock(bo
->ws
->global_bo_list_lock
);
139 LIST_DEL(&bo
->global_list_item
);
140 bo
->ws
->num_buffers
--;
141 pipe_mutex_unlock(bo
->ws
->global_bo_list_lock
);
143 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
144 amdgpu_va_range_free(bo
->va_handle
);
145 amdgpu_bo_free(bo
->bo
);
147 for (i
= 0; i
< RING_LAST
; i
++)
148 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
150 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
151 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
152 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
153 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
157 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
159 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
161 if (bo
->use_reusable_pool
)
162 pb_cache_add_buffer(&bo
->cache_entry
);
164 amdgpu_bo_destroy(_buf
);
167 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
168 struct radeon_winsys_cs
*rcs
,
169 enum pipe_transfer_usage usage
)
171 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
172 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
176 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
177 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
178 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
179 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
180 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
183 * Since we are mapping for read, we don't need to wait
184 * if the GPU is using the buffer for read too
185 * (neither one is changing it).
187 * Only check whether the buffer is being used for write. */
188 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
189 RADEON_USAGE_WRITE
)) {
190 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
194 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
195 RADEON_USAGE_WRITE
)) {
199 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
200 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
204 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
205 RADEON_USAGE_READWRITE
)) {
210 uint64_t time
= os_time_get_nano();
212 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
215 * Since we are mapping for read, we don't need to wait
216 * if the GPU is using the buffer for read too
217 * (neither one is changing it).
219 * Only check whether the buffer is being used for write. */
220 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
221 RADEON_USAGE_WRITE
)) {
222 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
224 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
225 if (p_atomic_read(&bo
->num_active_ioctls
))
226 amdgpu_cs_sync_flush(rcs
);
228 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
231 /* Mapping for write. */
233 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
234 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
236 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
237 if (p_atomic_read(&bo
->num_active_ioctls
))
238 amdgpu_cs_sync_flush(rcs
);
242 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
243 RADEON_USAGE_READWRITE
);
246 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
250 /* If the buffer is created from user memory, return the user pointer. */
254 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
256 /* Clear the cache and try again. */
257 pb_cache_release_all_buffers(&bo
->ws
->bo_cache
);
258 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
260 return r
? NULL
: cpu
;
263 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
265 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
267 amdgpu_bo_cpu_unmap(bo
->bo
);
270 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
271 amdgpu_bo_destroy_or_cache
272 /* other functions are never called */
275 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
277 struct amdgpu_winsys
*ws
= bo
->ws
;
279 pipe_mutex_lock(ws
->global_bo_list_lock
);
280 LIST_ADDTAIL(&bo
->global_list_item
, &ws
->global_bo_list
);
282 pipe_mutex_unlock(ws
->global_bo_list_lock
);
285 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
289 enum radeon_bo_domain initial_domain
,
292 struct amdgpu_bo_alloc_request request
= {0};
293 amdgpu_bo_handle buf_handle
;
295 struct amdgpu_winsys_bo
*bo
;
296 amdgpu_va_handle va_handle
;
299 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
300 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
305 pb_cache_init_entry(&ws
->bo_cache
, &bo
->cache_entry
, &bo
->base
);
306 request
.alloc_size
= size
;
307 request
.phys_alignment
= alignment
;
309 if (initial_domain
& RADEON_DOMAIN_VRAM
)
310 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
311 if (initial_domain
& RADEON_DOMAIN_GTT
)
312 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
314 if (flags
& RADEON_FLAG_CPU_ACCESS
)
315 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
316 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
317 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
318 if (flags
& RADEON_FLAG_GTT_WC
)
319 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
321 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
323 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
324 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
325 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
326 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
330 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
331 size
, alignment
, 0, &va
, &va_handle
, 0);
335 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
339 pipe_reference_init(&bo
->base
.reference
, 1);
340 bo
->base
.alignment
= alignment
;
341 bo
->base
.usage
= usage
;
342 bo
->base
.size
= size
;
343 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
347 bo
->va_handle
= va_handle
;
348 bo
->initial_domain
= initial_domain
;
349 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
351 if (initial_domain
& RADEON_DOMAIN_VRAM
)
352 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
353 else if (initial_domain
& RADEON_DOMAIN_GTT
)
354 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
356 amdgpu_add_buffer_to_global_list(bo
);
361 amdgpu_va_range_free(va_handle
);
364 amdgpu_bo_free(buf_handle
);
371 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
373 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
375 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
379 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
382 static unsigned eg_tile_split(unsigned tile_split
)
384 switch (tile_split
) {
385 case 0: tile_split
= 64; break;
386 case 1: tile_split
= 128; break;
387 case 2: tile_split
= 256; break;
388 case 3: tile_split
= 512; break;
390 case 4: tile_split
= 1024; break;
391 case 5: tile_split
= 2048; break;
392 case 6: tile_split
= 4096; break;
397 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
399 switch (eg_tile_split
) {
411 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
412 struct radeon_bo_metadata
*md
)
414 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
415 struct amdgpu_bo_info info
= {0};
416 uint32_t tiling_flags
;
419 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
423 tiling_flags
= info
.metadata
.tiling_info
;
425 md
->microtile
= RADEON_LAYOUT_LINEAR
;
426 md
->macrotile
= RADEON_LAYOUT_LINEAR
;
428 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
429 md
->macrotile
= RADEON_LAYOUT_TILED
;
430 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
431 md
->microtile
= RADEON_LAYOUT_TILED
;
433 md
->pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
434 md
->bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
435 md
->bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
436 md
->tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
437 md
->mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
438 md
->num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
439 md
->scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
441 md
->size_metadata
= info
.metadata
.size_metadata
;
442 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
445 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
446 struct radeon_bo_metadata
*md
)
448 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
449 struct amdgpu_bo_metadata metadata
= {0};
450 uint32_t tiling_flags
= 0;
452 if (md
->macrotile
== RADEON_LAYOUT_TILED
)
453 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
454 else if (md
->microtile
== RADEON_LAYOUT_TILED
)
455 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
457 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
459 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->pipe_config
);
460 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->bankw
));
461 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->bankh
));
463 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->tile_split
));
464 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->mtilea
));
465 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->num_banks
)-1);
468 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
470 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
472 metadata
.tiling_info
= tiling_flags
;
473 metadata
.size_metadata
= md
->size_metadata
;
474 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
476 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
479 static struct pb_buffer
*
480 amdgpu_bo_create(struct radeon_winsys
*rws
,
483 enum radeon_bo_domain domain
,
484 enum radeon_bo_flag flags
)
486 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
487 struct amdgpu_winsys_bo
*bo
;
490 /* Align size to page size. This is the minimum alignment for normal
491 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
492 * like constant/uniform buffers, can benefit from better and more reuse.
494 size
= align64(size
, ws
->info
.gart_page_size
);
495 alignment
= align(alignment
, ws
->info
.gart_page_size
);
497 /* Only set one usage bit each for domains and flags, or the cache manager
498 * might consider different sets of domains / flags compatible
500 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
504 assert(flags
< sizeof(usage
) * 8 - 3);
505 usage
|= 1 << (flags
+ 3);
507 /* Get a buffer from the cache. */
508 bo
= (struct amdgpu_winsys_bo
*)
509 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
);
513 /* Create a new one. */
514 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
);
516 /* Clear the cache and try again. */
517 pb_cache_release_all_buffers(&ws
->bo_cache
);
518 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
);
523 bo
->use_reusable_pool
= true;
527 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
528 struct winsys_handle
*whandle
,
532 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
533 struct amdgpu_winsys_bo
*bo
;
534 enum amdgpu_bo_handle_type type
;
535 struct amdgpu_bo_import_result result
= {0};
537 amdgpu_va_handle va_handle
;
538 struct amdgpu_bo_info info
= {0};
539 enum radeon_bo_domain initial
= 0;
542 /* Initialize the structure. */
543 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
548 switch (whandle
->type
) {
549 case DRM_API_HANDLE_TYPE_SHARED
:
550 type
= amdgpu_bo_handle_type_gem_flink_name
;
552 case DRM_API_HANDLE_TYPE_FD
:
553 type
= amdgpu_bo_handle_type_dma_buf_fd
;
559 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
563 /* Get initial domains. */
564 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
568 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
569 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
573 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
577 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
578 initial
|= RADEON_DOMAIN_VRAM
;
579 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
580 initial
|= RADEON_DOMAIN_GTT
;
583 pipe_reference_init(&bo
->base
.reference
, 1);
584 bo
->base
.alignment
= info
.phys_alignment
;
585 bo
->bo
= result
.buf_handle
;
586 bo
->base
.size
= result
.alloc_size
;
587 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
590 bo
->va_handle
= va_handle
;
591 bo
->initial_domain
= initial
;
592 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
593 bo
->is_shared
= true;
596 *stride
= whandle
->stride
;
598 *offset
= whandle
->offset
;
600 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
601 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
602 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
603 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
605 amdgpu_add_buffer_to_global_list(bo
);
610 amdgpu_va_range_free(va_handle
);
613 amdgpu_bo_free(result
.buf_handle
);
620 static boolean
amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
621 unsigned stride
, unsigned offset
,
623 struct winsys_handle
*whandle
)
625 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
626 enum amdgpu_bo_handle_type type
;
629 bo
->use_reusable_pool
= false;
631 switch (whandle
->type
) {
632 case DRM_API_HANDLE_TYPE_SHARED
:
633 type
= amdgpu_bo_handle_type_gem_flink_name
;
635 case DRM_API_HANDLE_TYPE_FD
:
636 type
= amdgpu_bo_handle_type_dma_buf_fd
;
638 case DRM_API_HANDLE_TYPE_KMS
:
639 type
= amdgpu_bo_handle_type_kms
;
645 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
649 whandle
->stride
= stride
;
650 whandle
->offset
= offset
;
651 whandle
->offset
+= slice_size
* whandle
->layer
;
652 bo
->is_shared
= true;
656 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
657 void *pointer
, uint64_t size
)
659 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
660 amdgpu_bo_handle buf_handle
;
661 struct amdgpu_winsys_bo
*bo
;
663 amdgpu_va_handle va_handle
;
665 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
669 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
672 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
673 size
, 1 << 12, 0, &va
, &va_handle
, 0))
676 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
680 pipe_reference_init(&bo
->base
.reference
, 1);
682 bo
->base
.alignment
= 0;
683 bo
->base
.size
= size
;
684 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
686 bo
->user_ptr
= pointer
;
688 bo
->va_handle
= va_handle
;
689 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
690 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
692 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
694 amdgpu_add_buffer_to_global_list(bo
);
696 return (struct pb_buffer
*)bo
;
699 amdgpu_va_range_free(va_handle
);
702 amdgpu_bo_free(buf_handle
);
709 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
711 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
714 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
716 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
719 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
721 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
722 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
723 ws
->base
.buffer_map
= amdgpu_bo_map
;
724 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
725 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
726 ws
->base
.buffer_create
= amdgpu_bo_create
;
727 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
728 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
729 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
730 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
731 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
732 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;