2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
31 #include "util/u_hash_table.h"
32 #include "state_tracker/drm_driver.h"
33 #include <amdgpu_drm.h>
38 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
39 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
42 #ifndef AMDGPU_VA_RANGE_HIGH
43 #define AMDGPU_VA_RANGE_HIGH 0x2
46 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
47 #define DEBUG_SPARSE_COMMITS 0
49 struct amdgpu_sparse_backing_chunk
{
53 static struct pb_buffer
*
54 amdgpu_bo_create(struct radeon_winsys
*rws
,
57 enum radeon_bo_domain domain
,
58 enum radeon_bo_flag flags
);
60 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
61 enum radeon_bo_usage usage
)
63 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
64 struct amdgpu_winsys
*ws
= bo
->ws
;
68 if (p_atomic_read(&bo
->num_active_ioctls
))
72 abs_timeout
= os_time_get_absolute_timeout(timeout
);
74 /* Wait if any ioctl is being submitted with this buffer. */
75 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
80 /* We can't use user fences for shared buffers, because user fences
81 * are local to this process only. If we want to wait for all buffer
82 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
84 bool buffer_busy
= true;
87 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
89 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
98 simple_mtx_lock(&ws
->bo_fence_lock
);
100 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
101 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
105 /* Release the idle fences to avoid checking them again later. */
106 for (unsigned i
= 0; i
< idle_fences
; ++i
)
107 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
109 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
110 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
111 bo
->num_fences
-= idle_fences
;
113 buffer_idle
= !bo
->num_fences
;
114 simple_mtx_unlock(&ws
->bo_fence_lock
);
118 bool buffer_idle
= true;
120 simple_mtx_lock(&ws
->bo_fence_lock
);
121 while (bo
->num_fences
&& buffer_idle
) {
122 struct pipe_fence_handle
*fence
= NULL
;
123 bool fence_idle
= false;
125 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
127 /* Wait for the fence. */
128 simple_mtx_unlock(&ws
->bo_fence_lock
);
129 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
133 simple_mtx_lock(&ws
->bo_fence_lock
);
135 /* Release an idle fence to avoid checking it again later, keeping in
136 * mind that the fence array may have been modified by other threads.
138 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
139 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
140 memmove(&bo
->fences
[0], &bo
->fences
[1],
141 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
145 amdgpu_fence_reference(&fence
, NULL
);
147 simple_mtx_unlock(&ws
->bo_fence_lock
);
153 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
154 struct pb_buffer
*buf
)
156 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
159 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
161 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
162 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
169 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
171 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
172 struct amdgpu_winsys
*ws
= bo
->ws
;
174 assert(bo
->bo
&& "must not be called for slab entries");
176 if (ws
->debug_all_bos
) {
177 simple_mtx_lock(&ws
->global_bo_list_lock
);
178 LIST_DEL(&bo
->u
.real
.global_list_item
);
180 simple_mtx_unlock(&ws
->global_bo_list_lock
);
183 simple_mtx_lock(&ws
->bo_export_table_lock
);
184 util_hash_table_remove(ws
->bo_export_table
, bo
->bo
);
185 simple_mtx_unlock(&ws
->bo_export_table_lock
);
187 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
188 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
189 amdgpu_bo_free(bo
->bo
);
191 amdgpu_bo_remove_fences(bo
);
193 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
194 ws
->allocated_vram
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
195 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
196 ws
->allocated_gtt
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
198 if (bo
->u
.real
.map_count
>= 1) {
199 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
200 ws
->mapped_vram
-= bo
->base
.size
;
201 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
202 ws
->mapped_gtt
-= bo
->base
.size
;
203 ws
->num_mapped_buffers
--;
209 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
211 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
213 assert(bo
->bo
); /* slab buffers have a separate vtbl */
215 if (bo
->u
.real
.use_reusable_pool
)
216 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
218 amdgpu_bo_destroy(_buf
);
221 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
222 struct radeon_cmdbuf
*rcs
,
223 enum pipe_transfer_usage usage
)
225 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
226 struct amdgpu_winsys_bo
*real
;
227 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
234 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
235 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
236 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
237 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
238 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
241 * Since we are mapping for read, we don't need to wait
242 * if the GPU is using the buffer for read too
243 * (neither one is changing it).
245 * Only check whether the buffer is being used for write. */
246 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
247 RADEON_USAGE_WRITE
)) {
248 cs
->flush_cs(cs
->flush_data
,
249 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
253 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
254 RADEON_USAGE_WRITE
)) {
258 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
259 cs
->flush_cs(cs
->flush_data
,
260 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
264 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
265 RADEON_USAGE_READWRITE
)) {
270 uint64_t time
= os_time_get_nano();
272 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
275 * Since we are mapping for read, we don't need to wait
276 * if the GPU is using the buffer for read too
277 * (neither one is changing it).
279 * Only check whether the buffer is being used for write. */
281 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
282 RADEON_USAGE_WRITE
)) {
283 cs
->flush_cs(cs
->flush_data
,
284 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
286 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
287 if (p_atomic_read(&bo
->num_active_ioctls
))
288 amdgpu_cs_sync_flush(rcs
);
292 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
295 /* Mapping for write. */
297 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
298 cs
->flush_cs(cs
->flush_data
,
299 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
301 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
302 if (p_atomic_read(&bo
->num_active_ioctls
))
303 amdgpu_cs_sync_flush(rcs
);
307 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
308 RADEON_USAGE_READWRITE
);
311 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
315 /* If the buffer is created from user memory, return the user pointer. */
322 real
= bo
->u
.slab
.real
;
323 offset
= bo
->va
- real
->va
;
326 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
328 /* Clear the cache and try again. */
329 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
330 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
335 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
336 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
337 real
->ws
->mapped_vram
+= real
->base
.size
;
338 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
339 real
->ws
->mapped_gtt
+= real
->base
.size
;
340 real
->ws
->num_mapped_buffers
++;
342 return (uint8_t*)cpu
+ offset
;
345 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
347 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
348 struct amdgpu_winsys_bo
*real
;
355 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
357 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
358 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
359 real
->ws
->mapped_vram
-= real
->base
.size
;
360 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
361 real
->ws
->mapped_gtt
-= real
->base
.size
;
362 real
->ws
->num_mapped_buffers
--;
365 amdgpu_bo_cpu_unmap(real
->bo
);
368 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
369 amdgpu_bo_destroy_or_cache
370 /* other functions are never called */
373 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
375 struct amdgpu_winsys
*ws
= bo
->ws
;
379 if (ws
->debug_all_bos
) {
380 simple_mtx_lock(&ws
->global_bo_list_lock
);
381 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
383 simple_mtx_unlock(&ws
->global_bo_list_lock
);
387 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
390 enum radeon_bo_domain initial_domain
,
394 struct amdgpu_bo_alloc_request request
= {0};
395 amdgpu_bo_handle buf_handle
;
397 struct amdgpu_winsys_bo
*bo
;
398 amdgpu_va_handle va_handle
;
399 unsigned va_gap_size
;
402 /* VRAM or GTT must be specified, but not both at the same time. */
403 assert(util_bitcount(initial_domain
& RADEON_DOMAIN_VRAM_GTT
) == 1);
405 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
411 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
414 request
.alloc_size
= size
;
415 request
.phys_alignment
= alignment
;
417 if (initial_domain
& RADEON_DOMAIN_VRAM
)
418 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
419 if (initial_domain
& RADEON_DOMAIN_GTT
)
420 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
422 /* Since VRAM and GTT have almost the same performance on APUs, we could
423 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
424 * shared with the OS, allow VRAM placements too. The idea is not to use
425 * VRAM usefully, but to use it so that it's not unused and wasted.
427 if (!ws
->info
.has_dedicated_vram
)
428 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
430 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
431 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
432 if (flags
& RADEON_FLAG_GTT_WC
)
433 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
434 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
435 ws
->info
.has_local_buffers
)
436 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
437 if (ws
->zero_all_vram_allocs
&&
438 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
439 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
441 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
443 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
444 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
445 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
446 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
450 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
451 if (size
> ws
->info
.pte_fragment_size
)
452 alignment
= MAX2(alignment
, ws
->info
.pte_fragment_size
);
453 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
454 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
,
455 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
456 AMDGPU_VA_RANGE_HIGH
);
460 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
461 AMDGPU_VM_PAGE_EXECUTABLE
;
463 if (!(flags
& RADEON_FLAG_READ_ONLY
))
464 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
466 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
471 pipe_reference_init(&bo
->base
.reference
, 1);
472 bo
->base
.alignment
= alignment
;
474 bo
->base
.size
= size
;
475 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
479 bo
->u
.real
.va_handle
= va_handle
;
480 bo
->initial_domain
= initial_domain
;
481 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
482 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
484 if (initial_domain
& RADEON_DOMAIN_VRAM
)
485 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
486 else if (initial_domain
& RADEON_DOMAIN_GTT
)
487 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
489 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
491 amdgpu_add_buffer_to_global_list(bo
);
496 amdgpu_va_range_free(va_handle
);
499 amdgpu_bo_free(buf_handle
);
506 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
508 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
510 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
514 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
517 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
519 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
520 bo
= container_of(entry
, bo
, u
.slab
.entry
);
522 return amdgpu_bo_can_reclaim(&bo
->base
);
525 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
527 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
531 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
534 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
535 amdgpu_bo_slab_destroy
536 /* other functions are never called */
539 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
541 unsigned group_index
)
543 struct amdgpu_winsys
*ws
= priv
;
544 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
545 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
546 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
552 unsigned slab_size
= 1 << AMDGPU_SLAB_BO_SIZE_LOG2
;
553 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
554 slab_size
, slab_size
,
559 assert(slab
->buffer
->bo
);
561 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
562 slab
->base
.num_free
= slab
->base
.num_entries
;
563 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
567 LIST_INITHEAD(&slab
->base
.free
);
569 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
571 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
572 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
574 bo
->base
.alignment
= entry_size
;
575 bo
->base
.usage
= slab
->buffer
->base
.usage
;
576 bo
->base
.size
= entry_size
;
577 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
579 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
580 bo
->initial_domain
= domains
;
581 bo
->unique_id
= base_id
+ i
;
582 bo
->u
.slab
.entry
.slab
= &slab
->base
;
583 bo
->u
.slab
.entry
.group_index
= group_index
;
584 bo
->u
.slab
.real
= slab
->buffer
;
586 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
592 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
598 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
600 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
602 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
603 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
606 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
610 #if DEBUG_SPARSE_COMMITS
612 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
614 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
616 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
618 struct amdgpu_sparse_backing
*span_backing
= NULL
;
619 uint32_t span_first_backing_page
= 0;
620 uint32_t span_first_va_page
= 0;
621 uint32_t va_page
= 0;
624 struct amdgpu_sparse_backing
*backing
= 0;
625 uint32_t backing_page
= 0;
627 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
628 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
629 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
633 (backing
!= span_backing
||
634 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
635 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
636 span_first_va_page
, va_page
- 1, span_backing
,
637 span_first_backing_page
,
638 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
643 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
646 if (backing
&& !span_backing
) {
647 span_backing
= backing
;
648 span_first_backing_page
= backing_page
;
649 span_first_va_page
= va_page
;
655 fprintf(stderr
, "Backing:\n");
657 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
658 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
659 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
660 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
666 * Attempt to allocate the given number of backing pages. Fewer pages may be
667 * allocated (depending on the fragmentation of existing backing buffers),
668 * which will be reflected by a change to *pnum_pages.
670 static struct amdgpu_sparse_backing
*
671 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
673 struct amdgpu_sparse_backing
*best_backing
;
675 uint32_t best_num_pages
;
681 /* This is a very simple and inefficient best-fit algorithm. */
682 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
683 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
684 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
685 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
686 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
687 best_backing
= backing
;
689 best_num_pages
= cur_num_pages
;
694 /* Allocate a new backing buffer if necessary. */
696 struct pb_buffer
*buf
;
700 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
704 best_backing
->max_chunks
= 4;
705 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
706 sizeof(*best_backing
->chunks
));
707 if (!best_backing
->chunks
) {
712 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
714 size
= MIN3(bo
->base
.size
/ 16,
716 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
717 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
719 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
721 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
723 FREE(best_backing
->chunks
);
728 /* We might have gotten a bigger buffer than requested via caching. */
729 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
731 best_backing
->bo
= amdgpu_winsys_bo(buf
);
732 best_backing
->num_chunks
= 1;
733 best_backing
->chunks
[0].begin
= 0;
734 best_backing
->chunks
[0].end
= pages
;
736 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
737 bo
->u
.sparse
.num_backing_pages
+= pages
;
740 best_num_pages
= pages
;
743 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
744 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
745 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
747 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
748 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
749 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
750 best_backing
->num_chunks
--;
757 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
758 struct amdgpu_sparse_backing
*backing
)
760 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
762 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
764 simple_mtx_lock(&ws
->bo_fence_lock
);
765 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
766 simple_mtx_unlock(&ws
->bo_fence_lock
);
768 list_del(&backing
->list
);
769 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
770 FREE(backing
->chunks
);
775 * Return a range of pages from the given backing buffer back into the
779 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
780 struct amdgpu_sparse_backing
*backing
,
781 uint32_t start_page
, uint32_t num_pages
)
783 uint32_t end_page
= start_page
+ num_pages
;
785 unsigned high
= backing
->num_chunks
;
787 /* Find the first chunk with begin >= start_page. */
789 unsigned mid
= low
+ (high
- low
) / 2;
791 if (backing
->chunks
[mid
].begin
>= start_page
)
797 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
798 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
800 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
801 backing
->chunks
[low
- 1].end
= end_page
;
803 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
804 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
805 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
806 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
807 backing
->num_chunks
--;
809 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
810 backing
->chunks
[low
].begin
= start_page
;
812 if (backing
->num_chunks
>= backing
->max_chunks
) {
813 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
814 struct amdgpu_sparse_backing_chunk
*new_chunks
=
815 REALLOC(backing
->chunks
,
816 sizeof(*backing
->chunks
) * backing
->max_chunks
,
817 sizeof(*backing
->chunks
) * new_max_chunks
);
821 backing
->max_chunks
= new_max_chunks
;
822 backing
->chunks
= new_chunks
;
825 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
826 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
827 backing
->chunks
[low
].begin
= start_page
;
828 backing
->chunks
[low
].end
= end_page
;
829 backing
->num_chunks
++;
832 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
833 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
834 sparse_free_backing_buffer(bo
, backing
);
839 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
841 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
844 assert(!bo
->bo
&& bo
->sparse
);
846 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
847 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
848 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
850 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
853 while (!list_empty(&bo
->u
.sparse
.backing
)) {
854 struct amdgpu_sparse_backing
*dummy
= NULL
;
855 sparse_free_backing_buffer(bo
,
856 container_of(bo
->u
.sparse
.backing
.next
,
860 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
861 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
862 FREE(bo
->u
.sparse
.commitments
);
866 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
867 amdgpu_bo_sparse_destroy
868 /* other functions are never called */
871 static struct pb_buffer
*
872 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
873 enum radeon_bo_domain domain
,
874 enum radeon_bo_flag flags
)
876 struct amdgpu_winsys_bo
*bo
;
878 uint64_t va_gap_size
;
881 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
882 * that exceed this limit. This is not really a restriction: we don't have
883 * that much virtual address space anyway.
885 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
888 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
892 pipe_reference_init(&bo
->base
.reference
, 1);
893 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
894 bo
->base
.size
= size
;
895 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
897 bo
->initial_domain
= domain
;
898 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
900 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
902 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
903 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
904 sizeof(*bo
->u
.sparse
.commitments
));
905 if (!bo
->u
.sparse
.commitments
)
906 goto error_alloc_commitments
;
908 simple_mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
909 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
911 /* For simplicity, we always map a multiple of the page size. */
912 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
913 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
914 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
915 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
916 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
917 AMDGPU_VA_RANGE_HIGH
);
921 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
922 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
929 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
931 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
932 FREE(bo
->u
.sparse
.commitments
);
933 error_alloc_commitments
:
939 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
942 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
943 struct amdgpu_sparse_commitment
*comm
;
944 uint32_t va_page
, end_va_page
;
949 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
950 assert(offset
<= bo
->base
.size
);
951 assert(size
<= bo
->base
.size
- offset
);
952 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
954 comm
= bo
->u
.sparse
.commitments
;
955 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
956 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
958 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
960 #if DEBUG_SPARSE_COMMITS
961 sparse_dump(bo
, __func__
);
965 while (va_page
< end_va_page
) {
966 uint32_t span_va_page
;
968 /* Skip pages that are already committed. */
969 if (comm
[va_page
].backing
) {
974 /* Determine length of uncommitted span. */
975 span_va_page
= va_page
;
976 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
979 /* Fill the uncommitted span with chunks of backing memory. */
980 while (span_va_page
< va_page
) {
981 struct amdgpu_sparse_backing
*backing
;
982 uint32_t backing_start
, backing_size
;
984 backing_size
= va_page
- span_va_page
;
985 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
991 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
992 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
993 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
994 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
995 AMDGPU_VM_PAGE_READABLE
|
996 AMDGPU_VM_PAGE_WRITEABLE
|
997 AMDGPU_VM_PAGE_EXECUTABLE
,
998 AMDGPU_VA_OP_REPLACE
);
1000 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
1001 assert(ok
&& "sufficient memory should already be allocated");
1007 while (backing_size
) {
1008 comm
[span_va_page
].backing
= backing
;
1009 comm
[span_va_page
].page
= backing_start
;
1017 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1018 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1019 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1020 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1026 while (va_page
< end_va_page
) {
1027 struct amdgpu_sparse_backing
*backing
;
1028 uint32_t backing_start
;
1029 uint32_t span_pages
;
1031 /* Skip pages that are already uncommitted. */
1032 if (!comm
[va_page
].backing
) {
1037 /* Group contiguous spans of pages. */
1038 backing
= comm
[va_page
].backing
;
1039 backing_start
= comm
[va_page
].page
;
1040 comm
[va_page
].backing
= NULL
;
1045 while (va_page
< end_va_page
&&
1046 comm
[va_page
].backing
== backing
&&
1047 comm
[va_page
].page
== backing_start
+ span_pages
) {
1048 comm
[va_page
].backing
= NULL
;
1053 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1054 /* Couldn't allocate tracking data structures, so we have to leak */
1055 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1062 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1067 static unsigned eg_tile_split(unsigned tile_split
)
1069 switch (tile_split
) {
1070 case 0: tile_split
= 64; break;
1071 case 1: tile_split
= 128; break;
1072 case 2: tile_split
= 256; break;
1073 case 3: tile_split
= 512; break;
1075 case 4: tile_split
= 1024; break;
1076 case 5: tile_split
= 2048; break;
1077 case 6: tile_split
= 4096; break;
1082 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1084 switch (eg_tile_split
) {
1090 case 1024: return 4;
1091 case 2048: return 5;
1092 case 4096: return 6;
1096 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1097 struct radeon_bo_metadata
*md
)
1099 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1100 struct amdgpu_bo_info info
= {0};
1101 uint64_t tiling_flags
;
1104 assert(bo
->bo
&& "must not be called for slab entries");
1106 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1110 tiling_flags
= info
.metadata
.tiling_info
;
1112 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1113 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1115 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1116 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1118 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1119 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1120 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1121 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1123 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1124 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1125 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1126 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1127 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1128 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1129 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1132 md
->size_metadata
= info
.metadata
.size_metadata
;
1133 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1136 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1137 struct radeon_bo_metadata
*md
)
1139 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1140 struct amdgpu_bo_metadata metadata
= {0};
1141 uint64_t tiling_flags
= 0;
1143 assert(bo
->bo
&& "must not be called for slab entries");
1145 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1146 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1148 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1149 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1150 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1151 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1153 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1155 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1156 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1157 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1158 if (md
->u
.legacy
.tile_split
)
1159 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1160 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1161 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1163 if (md
->u
.legacy
.scanout
)
1164 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1166 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1169 metadata
.tiling_info
= tiling_flags
;
1170 metadata
.size_metadata
= md
->size_metadata
;
1171 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1173 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1176 static struct pb_buffer
*
1177 amdgpu_bo_create(struct radeon_winsys
*rws
,
1180 enum radeon_bo_domain domain
,
1181 enum radeon_bo_flag flags
)
1183 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1184 struct amdgpu_winsys_bo
*bo
;
1187 /* VRAM implies WC. This is not optional. */
1188 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1190 /* NO_CPU_ACCESS is valid with VRAM only. */
1191 assert(domain
== RADEON_DOMAIN_VRAM
|| !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1193 /* Sparse buffers must have NO_CPU_ACCESS set. */
1194 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1196 /* Sub-allocate small buffers from slabs. */
1197 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1198 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1199 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1200 struct pb_slab_entry
*entry
;
1201 int heap
= radeon_get_heap_index(domain
, flags
);
1203 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1206 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1208 /* Clear the cache and try again. */
1209 pb_cache_release_all_buffers(&ws
->bo_cache
);
1211 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1217 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1219 pipe_reference_init(&bo
->base
.reference
, 1);
1225 if (flags
& RADEON_FLAG_SPARSE
) {
1226 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1228 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1231 /* This flag is irrelevant for the cache. */
1232 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1234 /* Align size to page size. This is the minimum alignment for normal
1235 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1236 * like constant/uniform buffers, can benefit from better and more reuse.
1238 size
= align64(size
, ws
->info
.gart_page_size
);
1239 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1241 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1243 if (use_reusable_pool
) {
1244 heap
= radeon_get_heap_index(domain
, flags
);
1245 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1247 /* Get a buffer from the cache. */
1248 bo
= (struct amdgpu_winsys_bo
*)
1249 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1254 /* Create a new one. */
1255 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1257 /* Clear the cache and try again. */
1258 pb_slabs_reclaim(&ws
->bo_slabs
);
1259 pb_cache_release_all_buffers(&ws
->bo_cache
);
1260 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1265 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1269 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1270 struct winsys_handle
*whandle
,
1274 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1275 struct amdgpu_winsys_bo
*bo
= NULL
;
1276 enum amdgpu_bo_handle_type type
;
1277 struct amdgpu_bo_import_result result
= {0};
1279 amdgpu_va_handle va_handle
= NULL
;
1280 struct amdgpu_bo_info info
= {0};
1281 enum radeon_bo_domain initial
= 0;
1284 switch (whandle
->type
) {
1285 case WINSYS_HANDLE_TYPE_SHARED
:
1286 type
= amdgpu_bo_handle_type_gem_flink_name
;
1288 case WINSYS_HANDLE_TYPE_FD
:
1289 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1296 *stride
= whandle
->stride
;
1298 *offset
= whandle
->offset
;
1300 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1304 simple_mtx_lock(&ws
->bo_export_table_lock
);
1305 bo
= util_hash_table_get(ws
->bo_export_table
, result
.buf_handle
);
1307 /* If the amdgpu_winsys_bo instance already exists, bump the reference
1308 * counter and return it.
1311 p_atomic_inc(&bo
->base
.reference
.count
);
1312 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1314 /* Release the buffer handle, because we don't need it anymore.
1315 * This function is returning an existing buffer, which has its own
1318 amdgpu_bo_free(result
.buf_handle
);
1322 /* Get initial domains. */
1323 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1327 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1328 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
,
1329 AMDGPU_VA_RANGE_HIGH
);
1333 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1337 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1341 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1342 initial
|= RADEON_DOMAIN_VRAM
;
1343 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1344 initial
|= RADEON_DOMAIN_GTT
;
1346 /* Initialize the structure. */
1347 pipe_reference_init(&bo
->base
.reference
, 1);
1348 bo
->base
.alignment
= info
.phys_alignment
;
1349 bo
->bo
= result
.buf_handle
;
1350 bo
->base
.size
= result
.alloc_size
;
1351 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1354 bo
->u
.real
.va_handle
= va_handle
;
1355 bo
->initial_domain
= initial
;
1356 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1357 bo
->is_shared
= true;
1359 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1360 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1361 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1362 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1364 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1366 amdgpu_add_buffer_to_global_list(bo
);
1368 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1369 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1374 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1378 amdgpu_va_range_free(va_handle
);
1379 amdgpu_bo_free(result
.buf_handle
);
1383 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1384 unsigned stride
, unsigned offset
,
1385 unsigned slice_size
,
1386 struct winsys_handle
*whandle
)
1388 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1389 struct amdgpu_winsys
*ws
= bo
->ws
;
1390 enum amdgpu_bo_handle_type type
;
1393 /* Don't allow exports of slab entries and sparse buffers. */
1397 bo
->u
.real
.use_reusable_pool
= false;
1399 switch (whandle
->type
) {
1400 case WINSYS_HANDLE_TYPE_SHARED
:
1401 type
= amdgpu_bo_handle_type_gem_flink_name
;
1403 case WINSYS_HANDLE_TYPE_FD
:
1404 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1406 case WINSYS_HANDLE_TYPE_KMS
:
1407 type
= amdgpu_bo_handle_type_kms
;
1413 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1417 simple_mtx_lock(&ws
->bo_export_table_lock
);
1418 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1419 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1421 whandle
->stride
= stride
;
1422 whandle
->offset
= offset
;
1423 whandle
->offset
+= slice_size
* whandle
->layer
;
1424 bo
->is_shared
= true;
1428 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1429 void *pointer
, uint64_t size
)
1431 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1432 amdgpu_bo_handle buf_handle
;
1433 struct amdgpu_winsys_bo
*bo
;
1435 amdgpu_va_handle va_handle
;
1436 /* Avoid failure when the size is not page aligned */
1437 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1439 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1443 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1444 aligned_size
, &buf_handle
))
1447 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1448 aligned_size
, 1 << 12, 0, &va
, &va_handle
,
1449 AMDGPU_VA_RANGE_HIGH
))
1450 goto error_va_alloc
;
1452 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1455 /* Initialize it. */
1456 pipe_reference_init(&bo
->base
.reference
, 1);
1457 bo
->bo
= buf_handle
;
1458 bo
->base
.alignment
= 0;
1459 bo
->base
.size
= size
;
1460 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1462 bo
->user_ptr
= pointer
;
1464 bo
->u
.real
.va_handle
= va_handle
;
1465 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1466 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1468 ws
->allocated_gtt
+= aligned_size
;
1470 amdgpu_add_buffer_to_global_list(bo
);
1472 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1474 return (struct pb_buffer
*)bo
;
1477 amdgpu_va_range_free(va_handle
);
1480 amdgpu_bo_free(buf_handle
);
1487 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1489 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1492 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1494 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1496 return !bo
->bo
&& !bo
->sparse
;
1499 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1501 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1504 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1506 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1507 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1508 ws
->base
.buffer_map
= amdgpu_bo_map
;
1509 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1510 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1511 ws
->base
.buffer_create
= amdgpu_bo_create
;
1512 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1513 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1514 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1515 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1516 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1517 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1518 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1519 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;