2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
31 #include "state_tracker/drm_driver.h"
32 #include <amdgpu_drm.h>
37 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
38 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
41 #ifndef AMDGPU_VA_RANGE_HIGH
42 #define AMDGPU_VA_RANGE_HIGH 0x2
45 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
46 #define DEBUG_SPARSE_COMMITS 0
48 struct amdgpu_sparse_backing_chunk
{
52 static struct pb_buffer
*
53 amdgpu_bo_create(struct radeon_winsys
*rws
,
56 enum radeon_bo_domain domain
,
57 enum radeon_bo_flag flags
);
59 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
60 enum radeon_bo_usage usage
)
62 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
63 struct amdgpu_winsys
*ws
= bo
->ws
;
67 if (p_atomic_read(&bo
->num_active_ioctls
))
71 abs_timeout
= os_time_get_absolute_timeout(timeout
);
73 /* Wait if any ioctl is being submitted with this buffer. */
74 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
79 /* We can't use user fences for shared buffers, because user fences
80 * are local to this process only. If we want to wait for all buffer
81 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
83 bool buffer_busy
= true;
86 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
88 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
97 simple_mtx_lock(&ws
->bo_fence_lock
);
99 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
100 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
104 /* Release the idle fences to avoid checking them again later. */
105 for (unsigned i
= 0; i
< idle_fences
; ++i
)
106 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
108 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
109 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
110 bo
->num_fences
-= idle_fences
;
112 buffer_idle
= !bo
->num_fences
;
113 simple_mtx_unlock(&ws
->bo_fence_lock
);
117 bool buffer_idle
= true;
119 simple_mtx_lock(&ws
->bo_fence_lock
);
120 while (bo
->num_fences
&& buffer_idle
) {
121 struct pipe_fence_handle
*fence
= NULL
;
122 bool fence_idle
= false;
124 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
126 /* Wait for the fence. */
127 simple_mtx_unlock(&ws
->bo_fence_lock
);
128 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
132 simple_mtx_lock(&ws
->bo_fence_lock
);
134 /* Release an idle fence to avoid checking it again later, keeping in
135 * mind that the fence array may have been modified by other threads.
137 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
138 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
139 memmove(&bo
->fences
[0], &bo
->fences
[1],
140 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
144 amdgpu_fence_reference(&fence
, NULL
);
146 simple_mtx_unlock(&ws
->bo_fence_lock
);
152 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
153 struct pb_buffer
*buf
)
155 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
158 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
160 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
161 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
168 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
170 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
172 assert(bo
->bo
&& "must not be called for slab entries");
174 if (bo
->ws
->debug_all_bos
) {
175 simple_mtx_lock(&bo
->ws
->global_bo_list_lock
);
176 LIST_DEL(&bo
->u
.real
.global_list_item
);
177 bo
->ws
->num_buffers
--;
178 simple_mtx_unlock(&bo
->ws
->global_bo_list_lock
);
181 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
182 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
183 amdgpu_bo_free(bo
->bo
);
185 amdgpu_bo_remove_fences(bo
);
187 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
188 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
189 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
190 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
192 if (bo
->u
.real
.map_count
>= 1) {
193 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
194 bo
->ws
->mapped_vram
-= bo
->base
.size
;
195 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
196 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
197 bo
->ws
->num_mapped_buffers
--;
203 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
205 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
207 assert(bo
->bo
); /* slab buffers have a separate vtbl */
209 if (bo
->u
.real
.use_reusable_pool
)
210 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
212 amdgpu_bo_destroy(_buf
);
215 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
216 struct radeon_cmdbuf
*rcs
,
217 enum pipe_transfer_usage usage
)
219 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
220 struct amdgpu_winsys_bo
*real
;
221 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
228 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
229 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
230 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
231 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
232 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
235 * Since we are mapping for read, we don't need to wait
236 * if the GPU is using the buffer for read too
237 * (neither one is changing it).
239 * Only check whether the buffer is being used for write. */
240 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
241 RADEON_USAGE_WRITE
)) {
242 cs
->flush_cs(cs
->flush_data
,
243 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
247 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
248 RADEON_USAGE_WRITE
)) {
252 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
253 cs
->flush_cs(cs
->flush_data
,
254 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
258 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
259 RADEON_USAGE_READWRITE
)) {
264 uint64_t time
= os_time_get_nano();
266 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
269 * Since we are mapping for read, we don't need to wait
270 * if the GPU is using the buffer for read too
271 * (neither one is changing it).
273 * Only check whether the buffer is being used for write. */
275 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
276 RADEON_USAGE_WRITE
)) {
277 cs
->flush_cs(cs
->flush_data
,
278 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
280 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
281 if (p_atomic_read(&bo
->num_active_ioctls
))
282 amdgpu_cs_sync_flush(rcs
);
286 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
289 /* Mapping for write. */
291 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
292 cs
->flush_cs(cs
->flush_data
,
293 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
295 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
296 if (p_atomic_read(&bo
->num_active_ioctls
))
297 amdgpu_cs_sync_flush(rcs
);
301 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
302 RADEON_USAGE_READWRITE
);
305 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
309 /* If the buffer is created from user memory, return the user pointer. */
316 real
= bo
->u
.slab
.real
;
317 offset
= bo
->va
- real
->va
;
320 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
322 /* Clear the cache and try again. */
323 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
324 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
329 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
330 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
331 real
->ws
->mapped_vram
+= real
->base
.size
;
332 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
333 real
->ws
->mapped_gtt
+= real
->base
.size
;
334 real
->ws
->num_mapped_buffers
++;
336 return (uint8_t*)cpu
+ offset
;
339 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
341 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
342 struct amdgpu_winsys_bo
*real
;
349 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
351 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
352 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
353 real
->ws
->mapped_vram
-= real
->base
.size
;
354 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
355 real
->ws
->mapped_gtt
-= real
->base
.size
;
356 real
->ws
->num_mapped_buffers
--;
359 amdgpu_bo_cpu_unmap(real
->bo
);
362 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
363 amdgpu_bo_destroy_or_cache
364 /* other functions are never called */
367 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
369 struct amdgpu_winsys
*ws
= bo
->ws
;
373 if (ws
->debug_all_bos
) {
374 simple_mtx_lock(&ws
->global_bo_list_lock
);
375 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
377 simple_mtx_unlock(&ws
->global_bo_list_lock
);
381 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
384 enum radeon_bo_domain initial_domain
,
388 struct amdgpu_bo_alloc_request request
= {0};
389 amdgpu_bo_handle buf_handle
;
391 struct amdgpu_winsys_bo
*bo
;
392 amdgpu_va_handle va_handle
;
393 unsigned va_gap_size
;
396 /* VRAM or GTT must be specified, but not both at the same time. */
397 assert(util_bitcount(initial_domain
& RADEON_DOMAIN_VRAM_GTT
) == 1);
399 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
405 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
408 request
.alloc_size
= size
;
409 request
.phys_alignment
= alignment
;
411 if (initial_domain
& RADEON_DOMAIN_VRAM
)
412 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
413 if (initial_domain
& RADEON_DOMAIN_GTT
)
414 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
416 /* Since VRAM and GTT have almost the same performance on APUs, we could
417 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
418 * shared with the OS, allow VRAM placements too. The idea is not to use
419 * VRAM usefully, but to use it so that it's not unused and wasted.
421 if (!ws
->info
.has_dedicated_vram
)
422 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
424 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
425 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
426 if (flags
& RADEON_FLAG_GTT_WC
)
427 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
428 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
429 ws
->info
.has_local_buffers
)
430 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
431 if (ws
->zero_all_vram_allocs
&&
432 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
433 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
435 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
437 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
438 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
439 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
440 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
444 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
445 if (size
> ws
->info
.pte_fragment_size
)
446 alignment
= MAX2(alignment
, ws
->info
.pte_fragment_size
);
447 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
448 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
,
449 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
450 AMDGPU_VA_RANGE_HIGH
);
454 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
455 AMDGPU_VM_PAGE_EXECUTABLE
;
457 if (!(flags
& RADEON_FLAG_READ_ONLY
))
458 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
460 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
465 pipe_reference_init(&bo
->base
.reference
, 1);
466 bo
->base
.alignment
= alignment
;
468 bo
->base
.size
= size
;
469 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
473 bo
->u
.real
.va_handle
= va_handle
;
474 bo
->initial_domain
= initial_domain
;
475 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
476 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
478 if (initial_domain
& RADEON_DOMAIN_VRAM
)
479 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
480 else if (initial_domain
& RADEON_DOMAIN_GTT
)
481 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
483 amdgpu_add_buffer_to_global_list(bo
);
488 amdgpu_va_range_free(va_handle
);
491 amdgpu_bo_free(buf_handle
);
498 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
500 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
502 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
506 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
509 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
511 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
512 bo
= container_of(entry
, bo
, u
.slab
.entry
);
514 return amdgpu_bo_can_reclaim(&bo
->base
);
517 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
519 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
523 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
526 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
527 amdgpu_bo_slab_destroy
528 /* other functions are never called */
531 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
533 unsigned group_index
)
535 struct amdgpu_winsys
*ws
= priv
;
536 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
537 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
538 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
544 unsigned slab_size
= 1 << AMDGPU_SLAB_BO_SIZE_LOG2
;
545 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
546 slab_size
, slab_size
,
551 assert(slab
->buffer
->bo
);
553 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
554 slab
->base
.num_free
= slab
->base
.num_entries
;
555 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
559 LIST_INITHEAD(&slab
->base
.free
);
561 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
563 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
564 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
566 bo
->base
.alignment
= entry_size
;
567 bo
->base
.usage
= slab
->buffer
->base
.usage
;
568 bo
->base
.size
= entry_size
;
569 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
571 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
572 bo
->initial_domain
= domains
;
573 bo
->unique_id
= base_id
+ i
;
574 bo
->u
.slab
.entry
.slab
= &slab
->base
;
575 bo
->u
.slab
.entry
.group_index
= group_index
;
576 bo
->u
.slab
.real
= slab
->buffer
;
578 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
584 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
590 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
592 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
594 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
595 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
598 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
602 #if DEBUG_SPARSE_COMMITS
604 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
606 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
608 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
610 struct amdgpu_sparse_backing
*span_backing
= NULL
;
611 uint32_t span_first_backing_page
= 0;
612 uint32_t span_first_va_page
= 0;
613 uint32_t va_page
= 0;
616 struct amdgpu_sparse_backing
*backing
= 0;
617 uint32_t backing_page
= 0;
619 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
620 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
621 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
625 (backing
!= span_backing
||
626 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
627 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
628 span_first_va_page
, va_page
- 1, span_backing
,
629 span_first_backing_page
,
630 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
635 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
638 if (backing
&& !span_backing
) {
639 span_backing
= backing
;
640 span_first_backing_page
= backing_page
;
641 span_first_va_page
= va_page
;
647 fprintf(stderr
, "Backing:\n");
649 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
650 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
651 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
652 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
658 * Attempt to allocate the given number of backing pages. Fewer pages may be
659 * allocated (depending on the fragmentation of existing backing buffers),
660 * which will be reflected by a change to *pnum_pages.
662 static struct amdgpu_sparse_backing
*
663 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
665 struct amdgpu_sparse_backing
*best_backing
;
667 uint32_t best_num_pages
;
673 /* This is a very simple and inefficient best-fit algorithm. */
674 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
675 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
676 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
677 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
678 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
679 best_backing
= backing
;
681 best_num_pages
= cur_num_pages
;
686 /* Allocate a new backing buffer if necessary. */
688 struct pb_buffer
*buf
;
692 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
696 best_backing
->max_chunks
= 4;
697 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
698 sizeof(*best_backing
->chunks
));
699 if (!best_backing
->chunks
) {
704 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
706 size
= MIN3(bo
->base
.size
/ 16,
708 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
709 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
711 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
713 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
715 FREE(best_backing
->chunks
);
720 /* We might have gotten a bigger buffer than requested via caching. */
721 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
723 best_backing
->bo
= amdgpu_winsys_bo(buf
);
724 best_backing
->num_chunks
= 1;
725 best_backing
->chunks
[0].begin
= 0;
726 best_backing
->chunks
[0].end
= pages
;
728 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
729 bo
->u
.sparse
.num_backing_pages
+= pages
;
732 best_num_pages
= pages
;
735 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
736 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
737 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
739 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
740 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
741 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
742 best_backing
->num_chunks
--;
749 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
750 struct amdgpu_sparse_backing
*backing
)
752 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
754 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
756 simple_mtx_lock(&ws
->bo_fence_lock
);
757 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
758 simple_mtx_unlock(&ws
->bo_fence_lock
);
760 list_del(&backing
->list
);
761 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
762 FREE(backing
->chunks
);
767 * Return a range of pages from the given backing buffer back into the
771 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
772 struct amdgpu_sparse_backing
*backing
,
773 uint32_t start_page
, uint32_t num_pages
)
775 uint32_t end_page
= start_page
+ num_pages
;
777 unsigned high
= backing
->num_chunks
;
779 /* Find the first chunk with begin >= start_page. */
781 unsigned mid
= low
+ (high
- low
) / 2;
783 if (backing
->chunks
[mid
].begin
>= start_page
)
789 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
790 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
792 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
793 backing
->chunks
[low
- 1].end
= end_page
;
795 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
796 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
797 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
798 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
799 backing
->num_chunks
--;
801 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
802 backing
->chunks
[low
].begin
= start_page
;
804 if (backing
->num_chunks
>= backing
->max_chunks
) {
805 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
806 struct amdgpu_sparse_backing_chunk
*new_chunks
=
807 REALLOC(backing
->chunks
,
808 sizeof(*backing
->chunks
) * backing
->max_chunks
,
809 sizeof(*backing
->chunks
) * new_max_chunks
);
813 backing
->max_chunks
= new_max_chunks
;
814 backing
->chunks
= new_chunks
;
817 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
818 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
819 backing
->chunks
[low
].begin
= start_page
;
820 backing
->chunks
[low
].end
= end_page
;
821 backing
->num_chunks
++;
824 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
825 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
826 sparse_free_backing_buffer(bo
, backing
);
831 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
833 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
836 assert(!bo
->bo
&& bo
->sparse
);
838 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
839 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
840 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
842 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
845 while (!list_empty(&bo
->u
.sparse
.backing
)) {
846 struct amdgpu_sparse_backing
*dummy
= NULL
;
847 sparse_free_backing_buffer(bo
,
848 container_of(bo
->u
.sparse
.backing
.next
,
852 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
853 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
854 FREE(bo
->u
.sparse
.commitments
);
858 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
859 amdgpu_bo_sparse_destroy
860 /* other functions are never called */
863 static struct pb_buffer
*
864 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
865 enum radeon_bo_domain domain
,
866 enum radeon_bo_flag flags
)
868 struct amdgpu_winsys_bo
*bo
;
870 uint64_t va_gap_size
;
873 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
874 * that exceed this limit. This is not really a restriction: we don't have
875 * that much virtual address space anyway.
877 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
880 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
884 pipe_reference_init(&bo
->base
.reference
, 1);
885 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
886 bo
->base
.size
= size
;
887 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
889 bo
->initial_domain
= domain
;
890 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
892 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
894 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
895 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
896 sizeof(*bo
->u
.sparse
.commitments
));
897 if (!bo
->u
.sparse
.commitments
)
898 goto error_alloc_commitments
;
900 simple_mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
901 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
903 /* For simplicity, we always map a multiple of the page size. */
904 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
905 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
906 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
907 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
908 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
909 AMDGPU_VA_RANGE_HIGH
);
913 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
914 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
921 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
923 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
924 FREE(bo
->u
.sparse
.commitments
);
925 error_alloc_commitments
:
931 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
934 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
935 struct amdgpu_sparse_commitment
*comm
;
936 uint32_t va_page
, end_va_page
;
941 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
942 assert(offset
<= bo
->base
.size
);
943 assert(size
<= bo
->base
.size
- offset
);
944 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
946 comm
= bo
->u
.sparse
.commitments
;
947 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
948 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
950 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
952 #if DEBUG_SPARSE_COMMITS
953 sparse_dump(bo
, __func__
);
957 while (va_page
< end_va_page
) {
958 uint32_t span_va_page
;
960 /* Skip pages that are already committed. */
961 if (comm
[va_page
].backing
) {
966 /* Determine length of uncommitted span. */
967 span_va_page
= va_page
;
968 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
971 /* Fill the uncommitted span with chunks of backing memory. */
972 while (span_va_page
< va_page
) {
973 struct amdgpu_sparse_backing
*backing
;
974 uint32_t backing_start
, backing_size
;
976 backing_size
= va_page
- span_va_page
;
977 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
983 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
984 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
985 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
986 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
987 AMDGPU_VM_PAGE_READABLE
|
988 AMDGPU_VM_PAGE_WRITEABLE
|
989 AMDGPU_VM_PAGE_EXECUTABLE
,
990 AMDGPU_VA_OP_REPLACE
);
992 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
993 assert(ok
&& "sufficient memory should already be allocated");
999 while (backing_size
) {
1000 comm
[span_va_page
].backing
= backing
;
1001 comm
[span_va_page
].page
= backing_start
;
1009 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1010 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1011 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1012 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1018 while (va_page
< end_va_page
) {
1019 struct amdgpu_sparse_backing
*backing
;
1020 uint32_t backing_start
;
1021 uint32_t span_pages
;
1023 /* Skip pages that are already uncommitted. */
1024 if (!comm
[va_page
].backing
) {
1029 /* Group contiguous spans of pages. */
1030 backing
= comm
[va_page
].backing
;
1031 backing_start
= comm
[va_page
].page
;
1032 comm
[va_page
].backing
= NULL
;
1037 while (va_page
< end_va_page
&&
1038 comm
[va_page
].backing
== backing
&&
1039 comm
[va_page
].page
== backing_start
+ span_pages
) {
1040 comm
[va_page
].backing
= NULL
;
1045 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1046 /* Couldn't allocate tracking data structures, so we have to leak */
1047 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1054 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1059 static unsigned eg_tile_split(unsigned tile_split
)
1061 switch (tile_split
) {
1062 case 0: tile_split
= 64; break;
1063 case 1: tile_split
= 128; break;
1064 case 2: tile_split
= 256; break;
1065 case 3: tile_split
= 512; break;
1067 case 4: tile_split
= 1024; break;
1068 case 5: tile_split
= 2048; break;
1069 case 6: tile_split
= 4096; break;
1074 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1076 switch (eg_tile_split
) {
1082 case 1024: return 4;
1083 case 2048: return 5;
1084 case 4096: return 6;
1088 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1089 struct radeon_bo_metadata
*md
)
1091 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1092 struct amdgpu_bo_info info
= {0};
1093 uint64_t tiling_flags
;
1096 assert(bo
->bo
&& "must not be called for slab entries");
1098 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1102 tiling_flags
= info
.metadata
.tiling_info
;
1104 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1105 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1107 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1108 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1110 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1111 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1112 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1113 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1115 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1116 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1117 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1118 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1119 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1120 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1121 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1124 md
->size_metadata
= info
.metadata
.size_metadata
;
1125 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1128 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1129 struct radeon_bo_metadata
*md
)
1131 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1132 struct amdgpu_bo_metadata metadata
= {0};
1133 uint64_t tiling_flags
= 0;
1135 assert(bo
->bo
&& "must not be called for slab entries");
1137 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1138 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1140 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1141 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1142 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1143 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1145 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1147 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1148 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1149 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1150 if (md
->u
.legacy
.tile_split
)
1151 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1152 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1153 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1155 if (md
->u
.legacy
.scanout
)
1156 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1158 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1161 metadata
.tiling_info
= tiling_flags
;
1162 metadata
.size_metadata
= md
->size_metadata
;
1163 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1165 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1168 static struct pb_buffer
*
1169 amdgpu_bo_create(struct radeon_winsys
*rws
,
1172 enum radeon_bo_domain domain
,
1173 enum radeon_bo_flag flags
)
1175 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1176 struct amdgpu_winsys_bo
*bo
;
1179 /* VRAM implies WC. This is not optional. */
1180 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1182 /* NO_CPU_ACCESS is valid with VRAM only. */
1183 assert(domain
== RADEON_DOMAIN_VRAM
|| !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1185 /* Sparse buffers must have NO_CPU_ACCESS set. */
1186 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1188 /* Sub-allocate small buffers from slabs. */
1189 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1190 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1191 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1192 struct pb_slab_entry
*entry
;
1193 int heap
= radeon_get_heap_index(domain
, flags
);
1195 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1198 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1200 /* Clear the cache and try again. */
1201 pb_cache_release_all_buffers(&ws
->bo_cache
);
1203 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1209 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1211 pipe_reference_init(&bo
->base
.reference
, 1);
1217 if (flags
& RADEON_FLAG_SPARSE
) {
1218 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1220 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1223 /* This flag is irrelevant for the cache. */
1224 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1226 /* Align size to page size. This is the minimum alignment for normal
1227 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1228 * like constant/uniform buffers, can benefit from better and more reuse.
1230 size
= align64(size
, ws
->info
.gart_page_size
);
1231 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1233 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1235 if (use_reusable_pool
) {
1236 heap
= radeon_get_heap_index(domain
, flags
);
1237 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1239 /* Get a buffer from the cache. */
1240 bo
= (struct amdgpu_winsys_bo
*)
1241 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1246 /* Create a new one. */
1247 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1249 /* Clear the cache and try again. */
1250 pb_slabs_reclaim(&ws
->bo_slabs
);
1251 pb_cache_release_all_buffers(&ws
->bo_cache
);
1252 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1257 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1261 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1262 struct winsys_handle
*whandle
,
1266 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1267 struct amdgpu_winsys_bo
*bo
;
1268 enum amdgpu_bo_handle_type type
;
1269 struct amdgpu_bo_import_result result
= {0};
1271 amdgpu_va_handle va_handle
;
1272 struct amdgpu_bo_info info
= {0};
1273 enum radeon_bo_domain initial
= 0;
1276 /* Initialize the structure. */
1277 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1282 switch (whandle
->type
) {
1283 case WINSYS_HANDLE_TYPE_SHARED
:
1284 type
= amdgpu_bo_handle_type_gem_flink_name
;
1286 case WINSYS_HANDLE_TYPE_FD
:
1287 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1293 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1297 /* Get initial domains. */
1298 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1302 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1303 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
,
1304 AMDGPU_VA_RANGE_HIGH
);
1308 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1312 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1313 initial
|= RADEON_DOMAIN_VRAM
;
1314 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1315 initial
|= RADEON_DOMAIN_GTT
;
1318 pipe_reference_init(&bo
->base
.reference
, 1);
1319 bo
->base
.alignment
= info
.phys_alignment
;
1320 bo
->bo
= result
.buf_handle
;
1321 bo
->base
.size
= result
.alloc_size
;
1322 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1325 bo
->u
.real
.va_handle
= va_handle
;
1326 bo
->initial_domain
= initial
;
1327 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1328 bo
->is_shared
= true;
1331 *stride
= whandle
->stride
;
1333 *offset
= whandle
->offset
;
1335 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1336 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1337 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1338 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1340 amdgpu_add_buffer_to_global_list(bo
);
1345 amdgpu_va_range_free(va_handle
);
1348 amdgpu_bo_free(result
.buf_handle
);
1355 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1356 unsigned stride
, unsigned offset
,
1357 unsigned slice_size
,
1358 struct winsys_handle
*whandle
)
1360 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1361 enum amdgpu_bo_handle_type type
;
1364 /* Don't allow exports of slab entries and sparse buffers. */
1368 bo
->u
.real
.use_reusable_pool
= false;
1370 switch (whandle
->type
) {
1371 case WINSYS_HANDLE_TYPE_SHARED
:
1372 type
= amdgpu_bo_handle_type_gem_flink_name
;
1374 case WINSYS_HANDLE_TYPE_FD
:
1375 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1377 case WINSYS_HANDLE_TYPE_KMS
:
1378 type
= amdgpu_bo_handle_type_kms
;
1384 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1388 whandle
->stride
= stride
;
1389 whandle
->offset
= offset
;
1390 whandle
->offset
+= slice_size
* whandle
->layer
;
1391 bo
->is_shared
= true;
1395 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1396 void *pointer
, uint64_t size
)
1398 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1399 amdgpu_bo_handle buf_handle
;
1400 struct amdgpu_winsys_bo
*bo
;
1402 amdgpu_va_handle va_handle
;
1403 /* Avoid failure when the size is not page aligned */
1404 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1406 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1410 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1411 aligned_size
, &buf_handle
))
1414 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1415 aligned_size
, 1 << 12, 0, &va
, &va_handle
,
1416 AMDGPU_VA_RANGE_HIGH
))
1417 goto error_va_alloc
;
1419 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1422 /* Initialize it. */
1423 pipe_reference_init(&bo
->base
.reference
, 1);
1424 bo
->bo
= buf_handle
;
1425 bo
->base
.alignment
= 0;
1426 bo
->base
.size
= size
;
1427 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1429 bo
->user_ptr
= pointer
;
1431 bo
->u
.real
.va_handle
= va_handle
;
1432 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1433 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1435 ws
->allocated_gtt
+= aligned_size
;
1437 amdgpu_add_buffer_to_global_list(bo
);
1439 return (struct pb_buffer
*)bo
;
1442 amdgpu_va_range_free(va_handle
);
1445 amdgpu_bo_free(buf_handle
);
1452 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1454 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1457 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1459 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1461 return !bo
->bo
&& !bo
->sparse
;
1464 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1466 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1469 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1471 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1472 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1473 ws
->base
.buffer_map
= amdgpu_bo_map
;
1474 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1475 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1476 ws
->base
.buffer_create
= amdgpu_bo_create
;
1477 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1478 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1479 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1480 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1481 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1482 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1483 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1484 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;