2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
31 #include "util/u_hash_table.h"
32 #include "state_tracker/drm_driver.h"
33 #include <amdgpu_drm.h>
38 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
39 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
42 #ifndef AMDGPU_VA_RANGE_HIGH
43 #define AMDGPU_VA_RANGE_HIGH 0x2
46 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
47 #define DEBUG_SPARSE_COMMITS 0
49 struct amdgpu_sparse_backing_chunk
{
53 static void amdgpu_bo_unmap(struct pb_buffer
*buf
);
55 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
56 enum radeon_bo_usage usage
)
58 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
59 struct amdgpu_winsys
*ws
= bo
->ws
;
63 if (p_atomic_read(&bo
->num_active_ioctls
))
67 abs_timeout
= os_time_get_absolute_timeout(timeout
);
69 /* Wait if any ioctl is being submitted with this buffer. */
70 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
75 /* We can't use user fences for shared buffers, because user fences
76 * are local to this process only. If we want to wait for all buffer
77 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
79 bool buffer_busy
= true;
82 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
84 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
93 simple_mtx_lock(&ws
->bo_fence_lock
);
95 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
96 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
100 /* Release the idle fences to avoid checking them again later. */
101 for (unsigned i
= 0; i
< idle_fences
; ++i
)
102 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
104 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
105 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
106 bo
->num_fences
-= idle_fences
;
108 buffer_idle
= !bo
->num_fences
;
109 simple_mtx_unlock(&ws
->bo_fence_lock
);
113 bool buffer_idle
= true;
115 simple_mtx_lock(&ws
->bo_fence_lock
);
116 while (bo
->num_fences
&& buffer_idle
) {
117 struct pipe_fence_handle
*fence
= NULL
;
118 bool fence_idle
= false;
120 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
122 /* Wait for the fence. */
123 simple_mtx_unlock(&ws
->bo_fence_lock
);
124 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
128 simple_mtx_lock(&ws
->bo_fence_lock
);
130 /* Release an idle fence to avoid checking it again later, keeping in
131 * mind that the fence array may have been modified by other threads.
133 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
134 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
135 memmove(&bo
->fences
[0], &bo
->fences
[1],
136 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
140 amdgpu_fence_reference(&fence
, NULL
);
142 simple_mtx_unlock(&ws
->bo_fence_lock
);
148 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
149 struct pb_buffer
*buf
)
151 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
154 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
156 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
157 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
164 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
166 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
167 struct amdgpu_winsys
*ws
= bo
->ws
;
169 assert(bo
->bo
&& "must not be called for slab entries");
171 if (!bo
->is_user_ptr
&& bo
->cpu_ptr
) {
173 amdgpu_bo_unmap(&bo
->base
);
175 assert(bo
->is_user_ptr
|| bo
->u
.real
.map_count
== 0);
177 if (ws
->debug_all_bos
) {
178 simple_mtx_lock(&ws
->global_bo_list_lock
);
179 LIST_DEL(&bo
->u
.real
.global_list_item
);
181 simple_mtx_unlock(&ws
->global_bo_list_lock
);
184 simple_mtx_lock(&ws
->bo_export_table_lock
);
185 util_hash_table_remove(ws
->bo_export_table
, bo
->bo
);
186 simple_mtx_unlock(&ws
->bo_export_table_lock
);
188 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
189 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
190 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
192 amdgpu_bo_free(bo
->bo
);
194 amdgpu_bo_remove_fences(bo
);
196 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
197 ws
->allocated_vram
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
198 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
199 ws
->allocated_gtt
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
201 simple_mtx_destroy(&bo
->lock
);
205 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
207 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
209 assert(bo
->bo
); /* slab buffers have a separate vtbl */
211 if (bo
->u
.real
.use_reusable_pool
)
212 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
214 amdgpu_bo_destroy(_buf
);
217 static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys
*ws
)
219 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++)
220 pb_slabs_reclaim(&ws
->bo_slabs
[i
]);
222 pb_cache_release_all_buffers(&ws
->bo_cache
);
225 static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo
*bo
, void **cpu
)
227 assert(!bo
->sparse
&& bo
->bo
&& !bo
->is_user_ptr
);
228 int r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
230 /* Clean up buffer managers and try again. */
231 amdgpu_clean_up_buffer_managers(bo
->ws
);
232 r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
237 if (p_atomic_inc_return(&bo
->u
.real
.map_count
) == 1) {
238 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
239 bo
->ws
->mapped_vram
+= bo
->base
.size
;
240 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
241 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
242 bo
->ws
->num_mapped_buffers
++;
248 void *amdgpu_bo_map(struct pb_buffer
*buf
,
249 struct radeon_cmdbuf
*rcs
,
250 enum pipe_transfer_usage usage
)
252 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
253 struct amdgpu_winsys_bo
*real
;
254 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
258 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
259 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
260 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
261 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
262 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
265 * Since we are mapping for read, we don't need to wait
266 * if the GPU is using the buffer for read too
267 * (neither one is changing it).
269 * Only check whether the buffer is being used for write. */
270 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
271 RADEON_USAGE_WRITE
)) {
272 cs
->flush_cs(cs
->flush_data
,
273 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
277 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
278 RADEON_USAGE_WRITE
)) {
282 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
283 cs
->flush_cs(cs
->flush_data
,
284 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
288 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
289 RADEON_USAGE_READWRITE
)) {
294 uint64_t time
= os_time_get_nano();
296 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
299 * Since we are mapping for read, we don't need to wait
300 * if the GPU is using the buffer for read too
301 * (neither one is changing it).
303 * Only check whether the buffer is being used for write. */
305 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
306 RADEON_USAGE_WRITE
)) {
307 cs
->flush_cs(cs
->flush_data
,
308 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
310 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
311 if (p_atomic_read(&bo
->num_active_ioctls
))
312 amdgpu_cs_sync_flush(rcs
);
316 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
319 /* Mapping for write. */
321 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
322 cs
->flush_cs(cs
->flush_data
,
323 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
325 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
326 if (p_atomic_read(&bo
->num_active_ioctls
))
327 amdgpu_cs_sync_flush(rcs
);
331 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
332 RADEON_USAGE_READWRITE
);
335 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
339 /* Buffer synchronization has been checked, now actually map the buffer. */
346 real
= bo
->u
.slab
.real
;
347 offset
= bo
->va
- real
->va
;
350 if (usage
& RADEON_TRANSFER_TEMPORARY
) {
351 if (real
->is_user_ptr
) {
354 if (!amdgpu_bo_do_map(real
, &cpu
))
358 cpu
= p_atomic_read(&real
->cpu_ptr
);
360 simple_mtx_lock(&real
->lock
);
361 /* Must re-check due to the possibility of a race. Re-check need not
362 * be atomic thanks to the lock. */
365 if (!amdgpu_bo_do_map(real
, &cpu
)) {
366 simple_mtx_unlock(&real
->lock
);
369 p_atomic_set(&real
->cpu_ptr
, cpu
);
371 simple_mtx_unlock(&real
->lock
);
375 return (uint8_t*)cpu
+ offset
;
378 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
380 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
381 struct amdgpu_winsys_bo
*real
;
388 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
389 assert(real
->u
.real
.map_count
!= 0 && "too many unmaps");
390 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
391 assert(!real
->cpu_ptr
&&
392 "too many unmaps or forgot RADEON_TRANSFER_TEMPORARY flag");
394 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
395 real
->ws
->mapped_vram
-= real
->base
.size
;
396 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
397 real
->ws
->mapped_gtt
-= real
->base
.size
;
398 real
->ws
->num_mapped_buffers
--;
401 amdgpu_bo_cpu_unmap(real
->bo
);
404 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
405 amdgpu_bo_destroy_or_cache
406 /* other functions are never called */
409 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
411 struct amdgpu_winsys
*ws
= bo
->ws
;
415 if (ws
->debug_all_bos
) {
416 simple_mtx_lock(&ws
->global_bo_list_lock
);
417 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
419 simple_mtx_unlock(&ws
->global_bo_list_lock
);
423 static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys
*ws
,
424 uint64_t size
, unsigned alignment
)
426 uint64_t vm_alignment
= alignment
;
428 /* Increase the VM alignment for faster address translation. */
429 if (size
>= ws
->info
.pte_fragment_size
)
430 vm_alignment
= MAX2(vm_alignment
, ws
->info
.pte_fragment_size
);
432 /* Gfx9: Increase the VM alignment to the most significant bit set
433 * in the size for faster address translation.
435 if (ws
->info
.chip_class
>= GFX9
) {
436 unsigned msb
= util_last_bit64(size
); /* 0 = no bit is set */
437 uint64_t msb_alignment
= msb
? 1ull << (msb
- 1) : 0;
439 vm_alignment
= MAX2(vm_alignment
, msb_alignment
);
444 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
447 enum radeon_bo_domain initial_domain
,
451 struct amdgpu_bo_alloc_request request
= {0};
452 amdgpu_bo_handle buf_handle
;
454 struct amdgpu_winsys_bo
*bo
;
455 amdgpu_va_handle va_handle
;
458 /* VRAM or GTT must be specified, but not both at the same time. */
459 assert(util_bitcount(initial_domain
& (RADEON_DOMAIN_VRAM_GTT
|
461 RADEON_DOMAIN_OA
)) == 1);
463 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
469 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
472 request
.alloc_size
= size
;
473 request
.phys_alignment
= alignment
;
475 if (initial_domain
& RADEON_DOMAIN_VRAM
) {
476 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
478 /* Since VRAM and GTT have almost the same performance on APUs, we could
479 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
480 * shared with the OS, allow VRAM placements too. The idea is not to use
481 * VRAM usefully, but to use it so that it's not unused and wasted.
483 if (!ws
->info
.has_dedicated_vram
)
484 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
487 if (initial_domain
& RADEON_DOMAIN_GTT
)
488 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
489 if (initial_domain
& RADEON_DOMAIN_GDS
)
490 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GDS
;
491 if (initial_domain
& RADEON_DOMAIN_OA
)
492 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_OA
;
494 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
495 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
496 if (flags
& RADEON_FLAG_GTT_WC
)
497 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
498 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
499 ws
->info
.has_local_buffers
)
500 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
501 if (ws
->zero_all_vram_allocs
&&
502 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
503 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
505 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
507 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
508 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
509 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
510 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
514 if (initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
515 unsigned va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
517 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
519 amdgpu_get_optimal_vm_alignment(ws
, size
, alignment
),
521 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
522 AMDGPU_VA_RANGE_HIGH
);
526 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
527 AMDGPU_VM_PAGE_EXECUTABLE
;
529 if (!(flags
& RADEON_FLAG_READ_ONLY
))
530 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
532 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
538 simple_mtx_init(&bo
->lock
, mtx_plain
);
539 pipe_reference_init(&bo
->base
.reference
, 1);
540 bo
->base
.alignment
= alignment
;
542 bo
->base
.size
= size
;
543 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
547 bo
->u
.real
.va_handle
= va_handle
;
548 bo
->initial_domain
= initial_domain
;
549 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
550 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
552 if (initial_domain
& RADEON_DOMAIN_VRAM
)
553 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
554 else if (initial_domain
& RADEON_DOMAIN_GTT
)
555 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
557 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
559 amdgpu_add_buffer_to_global_list(bo
);
564 amdgpu_va_range_free(va_handle
);
567 amdgpu_bo_free(buf_handle
);
574 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
576 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
578 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
582 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
585 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
587 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
588 bo
= container_of(entry
, bo
, u
.slab
.entry
);
590 return amdgpu_bo_can_reclaim(&bo
->base
);
593 static struct pb_slabs
*get_slabs(struct amdgpu_winsys
*ws
, uint64_t size
)
595 /* Find the correct slab allocator for the given size. */
596 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
597 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
599 if (size
<= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1))
607 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
609 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
613 pb_slab_free(get_slabs(bo
->ws
, bo
->base
.size
), &bo
->u
.slab
.entry
);
616 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
617 amdgpu_bo_slab_destroy
618 /* other functions are never called */
621 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
623 unsigned group_index
)
625 struct amdgpu_winsys
*ws
= priv
;
626 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
627 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
628 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
630 unsigned slab_size
= 0;
635 /* Determine the slab buffer size. */
636 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
637 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
638 unsigned max_entry_size
= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1);
640 if (entry_size
<= max_entry_size
) {
641 /* The slab size is twice the size of the largest possible entry. */
642 slab_size
= max_entry_size
* 2;
644 /* The largest slab should have the same size as the PTE fragment
645 * size to get faster address translation.
647 if (i
== NUM_SLAB_ALLOCATORS
- 1 &&
648 slab_size
< ws
->info
.pte_fragment_size
)
649 slab_size
= ws
->info
.pte_fragment_size
;
653 assert(slab_size
!= 0);
655 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(ws
,
656 slab_size
, slab_size
,
661 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
662 slab
->base
.num_free
= slab
->base
.num_entries
;
663 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
667 LIST_INITHEAD(&slab
->base
.free
);
669 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
671 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
672 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
674 simple_mtx_init(&bo
->lock
, mtx_plain
);
675 bo
->base
.alignment
= entry_size
;
676 bo
->base
.usage
= slab
->buffer
->base
.usage
;
677 bo
->base
.size
= entry_size
;
678 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
680 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
681 bo
->initial_domain
= domains
;
682 bo
->unique_id
= base_id
+ i
;
683 bo
->u
.slab
.entry
.slab
= &slab
->base
;
684 bo
->u
.slab
.entry
.group_index
= group_index
;
686 if (slab
->buffer
->bo
) {
687 /* The slab is not suballocated. */
688 bo
->u
.slab
.real
= slab
->buffer
;
690 /* The slab is allocated out of a bigger slab. */
691 bo
->u
.slab
.real
= slab
->buffer
->u
.slab
.real
;
692 assert(bo
->u
.slab
.real
->bo
);
695 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
701 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
707 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
709 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
711 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
712 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
713 simple_mtx_destroy(&slab
->entries
[i
].lock
);
717 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
721 #if DEBUG_SPARSE_COMMITS
723 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
725 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
727 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
729 struct amdgpu_sparse_backing
*span_backing
= NULL
;
730 uint32_t span_first_backing_page
= 0;
731 uint32_t span_first_va_page
= 0;
732 uint32_t va_page
= 0;
735 struct amdgpu_sparse_backing
*backing
= 0;
736 uint32_t backing_page
= 0;
738 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
739 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
740 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
744 (backing
!= span_backing
||
745 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
746 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
747 span_first_va_page
, va_page
- 1, span_backing
,
748 span_first_backing_page
,
749 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
754 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
757 if (backing
&& !span_backing
) {
758 span_backing
= backing
;
759 span_first_backing_page
= backing_page
;
760 span_first_va_page
= va_page
;
766 fprintf(stderr
, "Backing:\n");
768 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
769 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
770 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
771 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
777 * Attempt to allocate the given number of backing pages. Fewer pages may be
778 * allocated (depending on the fragmentation of existing backing buffers),
779 * which will be reflected by a change to *pnum_pages.
781 static struct amdgpu_sparse_backing
*
782 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
784 struct amdgpu_sparse_backing
*best_backing
;
786 uint32_t best_num_pages
;
792 /* This is a very simple and inefficient best-fit algorithm. */
793 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
794 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
795 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
796 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
797 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
798 best_backing
= backing
;
800 best_num_pages
= cur_num_pages
;
805 /* Allocate a new backing buffer if necessary. */
807 struct pb_buffer
*buf
;
811 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
815 best_backing
->max_chunks
= 4;
816 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
817 sizeof(*best_backing
->chunks
));
818 if (!best_backing
->chunks
) {
823 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
825 size
= MIN3(bo
->base
.size
/ 16,
827 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
828 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
830 buf
= amdgpu_bo_create(bo
->ws
, size
, RADEON_SPARSE_PAGE_SIZE
,
832 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
834 FREE(best_backing
->chunks
);
839 /* We might have gotten a bigger buffer than requested via caching. */
840 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
842 best_backing
->bo
= amdgpu_winsys_bo(buf
);
843 best_backing
->num_chunks
= 1;
844 best_backing
->chunks
[0].begin
= 0;
845 best_backing
->chunks
[0].end
= pages
;
847 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
848 bo
->u
.sparse
.num_backing_pages
+= pages
;
851 best_num_pages
= pages
;
854 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
855 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
856 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
858 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
859 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
860 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
861 best_backing
->num_chunks
--;
868 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
869 struct amdgpu_sparse_backing
*backing
)
871 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
873 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
875 simple_mtx_lock(&ws
->bo_fence_lock
);
876 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
877 simple_mtx_unlock(&ws
->bo_fence_lock
);
879 list_del(&backing
->list
);
880 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
881 FREE(backing
->chunks
);
886 * Return a range of pages from the given backing buffer back into the
890 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
891 struct amdgpu_sparse_backing
*backing
,
892 uint32_t start_page
, uint32_t num_pages
)
894 uint32_t end_page
= start_page
+ num_pages
;
896 unsigned high
= backing
->num_chunks
;
898 /* Find the first chunk with begin >= start_page. */
900 unsigned mid
= low
+ (high
- low
) / 2;
902 if (backing
->chunks
[mid
].begin
>= start_page
)
908 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
909 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
911 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
912 backing
->chunks
[low
- 1].end
= end_page
;
914 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
915 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
916 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
917 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
918 backing
->num_chunks
--;
920 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
921 backing
->chunks
[low
].begin
= start_page
;
923 if (backing
->num_chunks
>= backing
->max_chunks
) {
924 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
925 struct amdgpu_sparse_backing_chunk
*new_chunks
=
926 REALLOC(backing
->chunks
,
927 sizeof(*backing
->chunks
) * backing
->max_chunks
,
928 sizeof(*backing
->chunks
) * new_max_chunks
);
932 backing
->max_chunks
= new_max_chunks
;
933 backing
->chunks
= new_chunks
;
936 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
937 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
938 backing
->chunks
[low
].begin
= start_page
;
939 backing
->chunks
[low
].end
= end_page
;
940 backing
->num_chunks
++;
943 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
944 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
945 sparse_free_backing_buffer(bo
, backing
);
950 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
952 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
955 assert(!bo
->bo
&& bo
->sparse
);
957 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
958 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
959 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
961 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
964 while (!list_empty(&bo
->u
.sparse
.backing
)) {
965 struct amdgpu_sparse_backing
*dummy
= NULL
;
966 sparse_free_backing_buffer(bo
,
967 container_of(bo
->u
.sparse
.backing
.next
,
971 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
972 FREE(bo
->u
.sparse
.commitments
);
973 simple_mtx_destroy(&bo
->lock
);
977 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
978 amdgpu_bo_sparse_destroy
979 /* other functions are never called */
982 static struct pb_buffer
*
983 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
984 enum radeon_bo_domain domain
,
985 enum radeon_bo_flag flags
)
987 struct amdgpu_winsys_bo
*bo
;
989 uint64_t va_gap_size
;
992 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
993 * that exceed this limit. This is not really a restriction: we don't have
994 * that much virtual address space anyway.
996 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
999 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1003 simple_mtx_init(&bo
->lock
, mtx_plain
);
1004 pipe_reference_init(&bo
->base
.reference
, 1);
1005 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
1006 bo
->base
.size
= size
;
1007 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
1009 bo
->initial_domain
= domain
;
1010 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1012 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
1014 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1015 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
1016 sizeof(*bo
->u
.sparse
.commitments
));
1017 if (!bo
->u
.sparse
.commitments
)
1018 goto error_alloc_commitments
;
1020 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
1022 /* For simplicity, we always map a multiple of the page size. */
1023 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
1024 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
1025 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1026 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
1027 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
1028 AMDGPU_VA_RANGE_HIGH
);
1030 goto error_va_alloc
;
1032 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
1033 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
1040 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
1042 FREE(bo
->u
.sparse
.commitments
);
1043 error_alloc_commitments
:
1044 simple_mtx_destroy(&bo
->lock
);
1050 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
1053 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
1054 struct amdgpu_sparse_commitment
*comm
;
1055 uint32_t va_page
, end_va_page
;
1060 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
1061 assert(offset
<= bo
->base
.size
);
1062 assert(size
<= bo
->base
.size
- offset
);
1063 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
1065 comm
= bo
->u
.sparse
.commitments
;
1066 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
1067 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1069 simple_mtx_lock(&bo
->lock
);
1071 #if DEBUG_SPARSE_COMMITS
1072 sparse_dump(bo
, __func__
);
1076 while (va_page
< end_va_page
) {
1077 uint32_t span_va_page
;
1079 /* Skip pages that are already committed. */
1080 if (comm
[va_page
].backing
) {
1085 /* Determine length of uncommitted span. */
1086 span_va_page
= va_page
;
1087 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
1090 /* Fill the uncommitted span with chunks of backing memory. */
1091 while (span_va_page
< va_page
) {
1092 struct amdgpu_sparse_backing
*backing
;
1093 uint32_t backing_start
, backing_size
;
1095 backing_size
= va_page
- span_va_page
;
1096 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
1102 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
1103 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
1104 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
1105 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
1106 AMDGPU_VM_PAGE_READABLE
|
1107 AMDGPU_VM_PAGE_WRITEABLE
|
1108 AMDGPU_VM_PAGE_EXECUTABLE
,
1109 AMDGPU_VA_OP_REPLACE
);
1111 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
1112 assert(ok
&& "sufficient memory should already be allocated");
1118 while (backing_size
) {
1119 comm
[span_va_page
].backing
= backing
;
1120 comm
[span_va_page
].page
= backing_start
;
1128 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1129 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1130 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1131 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1137 while (va_page
< end_va_page
) {
1138 struct amdgpu_sparse_backing
*backing
;
1139 uint32_t backing_start
;
1140 uint32_t span_pages
;
1142 /* Skip pages that are already uncommitted. */
1143 if (!comm
[va_page
].backing
) {
1148 /* Group contiguous spans of pages. */
1149 backing
= comm
[va_page
].backing
;
1150 backing_start
= comm
[va_page
].page
;
1151 comm
[va_page
].backing
= NULL
;
1156 while (va_page
< end_va_page
&&
1157 comm
[va_page
].backing
== backing
&&
1158 comm
[va_page
].page
== backing_start
+ span_pages
) {
1159 comm
[va_page
].backing
= NULL
;
1164 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1165 /* Couldn't allocate tracking data structures, so we have to leak */
1166 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1173 simple_mtx_unlock(&bo
->lock
);
1178 static unsigned eg_tile_split(unsigned tile_split
)
1180 switch (tile_split
) {
1181 case 0: tile_split
= 64; break;
1182 case 1: tile_split
= 128; break;
1183 case 2: tile_split
= 256; break;
1184 case 3: tile_split
= 512; break;
1186 case 4: tile_split
= 1024; break;
1187 case 5: tile_split
= 2048; break;
1188 case 6: tile_split
= 4096; break;
1193 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1195 switch (eg_tile_split
) {
1201 case 1024: return 4;
1202 case 2048: return 5;
1203 case 4096: return 6;
1207 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1208 struct radeon_bo_metadata
*md
)
1210 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1211 struct amdgpu_bo_info info
= {0};
1212 uint64_t tiling_flags
;
1215 assert(bo
->bo
&& "must not be called for slab entries");
1217 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1221 tiling_flags
= info
.metadata
.tiling_info
;
1223 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1224 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1226 md
->u
.gfx9
.dcc_offset_256B
= AMDGPU_TILING_GET(tiling_flags
, DCC_OFFSET_256B
);
1227 md
->u
.gfx9
.dcc_pitch_max
= AMDGPU_TILING_GET(tiling_flags
, DCC_PITCH_MAX
);
1228 md
->u
.gfx9
.dcc_independent_64B
= AMDGPU_TILING_GET(tiling_flags
, DCC_INDEPENDENT_64B
);
1230 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1231 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1233 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1234 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1235 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1236 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1238 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1239 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1240 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1241 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1242 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1243 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1244 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1247 md
->size_metadata
= info
.metadata
.size_metadata
;
1248 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1251 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1252 struct radeon_bo_metadata
*md
)
1254 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1255 struct amdgpu_bo_metadata metadata
= {0};
1256 uint64_t tiling_flags
= 0;
1258 assert(bo
->bo
&& "must not be called for slab entries");
1260 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1261 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1263 tiling_flags
|= AMDGPU_TILING_SET(DCC_OFFSET_256B
, md
->u
.gfx9
.dcc_offset_256B
);
1264 tiling_flags
|= AMDGPU_TILING_SET(DCC_PITCH_MAX
, md
->u
.gfx9
.dcc_pitch_max
);
1265 tiling_flags
|= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B
, md
->u
.gfx9
.dcc_independent_64B
);
1267 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1268 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1269 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1270 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1272 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1274 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1275 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1276 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1277 if (md
->u
.legacy
.tile_split
)
1278 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1279 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1280 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1282 if (md
->u
.legacy
.scanout
)
1283 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1285 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1288 metadata
.tiling_info
= tiling_flags
;
1289 metadata
.size_metadata
= md
->size_metadata
;
1290 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1292 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1296 amdgpu_bo_create(struct amdgpu_winsys
*ws
,
1299 enum radeon_bo_domain domain
,
1300 enum radeon_bo_flag flags
)
1302 struct amdgpu_winsys_bo
*bo
;
1305 if (domain
& (RADEON_DOMAIN_GDS
| RADEON_DOMAIN_OA
))
1306 flags
|= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_SUBALLOC
;
1308 /* VRAM implies WC. This is not optional. */
1309 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1311 /* NO_CPU_ACCESS is not valid with GTT. */
1312 assert(!(domain
& RADEON_DOMAIN_GTT
) || !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1314 /* Sparse buffers must have NO_CPU_ACCESS set. */
1315 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1317 struct pb_slabs
*last_slab
= &ws
->bo_slabs
[NUM_SLAB_ALLOCATORS
- 1];
1318 unsigned max_slab_entry_size
= 1 << (last_slab
->min_order
+ last_slab
->num_orders
- 1);
1320 /* Sub-allocate small buffers from slabs. */
1321 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1322 size
<= max_slab_entry_size
&&
1323 /* The alignment must be at most the size of the smallest slab entry or
1324 * the next power of two. */
1325 alignment
<= MAX2(1 << ws
->bo_slabs
[0].min_order
, util_next_power_of_two(size
))) {
1326 struct pb_slab_entry
*entry
;
1327 int heap
= radeon_get_heap_index(domain
, flags
);
1329 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1332 struct pb_slabs
*slabs
= get_slabs(ws
, size
);
1333 entry
= pb_slab_alloc(slabs
, size
, heap
);
1335 /* Clean up buffer managers and try again. */
1336 amdgpu_clean_up_buffer_managers(ws
);
1338 entry
= pb_slab_alloc(slabs
, size
, heap
);
1344 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1346 pipe_reference_init(&bo
->base
.reference
, 1);
1352 if (flags
& RADEON_FLAG_SPARSE
) {
1353 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1355 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1358 /* This flag is irrelevant for the cache. */
1359 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1361 /* Align size to page size. This is the minimum alignment for normal
1362 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1363 * like constant/uniform buffers, can benefit from better and more reuse.
1365 if (domain
& RADEON_DOMAIN_VRAM_GTT
) {
1366 size
= align64(size
, ws
->info
.gart_page_size
);
1367 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1370 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1372 if (use_reusable_pool
) {
1373 heap
= radeon_get_heap_index(domain
, flags
);
1374 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1376 /* Get a buffer from the cache. */
1377 bo
= (struct amdgpu_winsys_bo
*)
1378 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1383 /* Create a new one. */
1384 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1386 /* Clean up buffer managers and try again. */
1387 amdgpu_clean_up_buffer_managers(ws
);
1389 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1394 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1398 static struct pb_buffer
*
1399 amdgpu_buffer_create(struct radeon_winsys
*ws
,
1402 enum radeon_bo_domain domain
,
1403 enum radeon_bo_flag flags
)
1405 return amdgpu_bo_create(amdgpu_winsys(ws
), size
, alignment
, domain
,
1409 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1410 struct winsys_handle
*whandle
,
1411 unsigned vm_alignment
,
1415 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1416 struct amdgpu_winsys_bo
*bo
= NULL
;
1417 enum amdgpu_bo_handle_type type
;
1418 struct amdgpu_bo_import_result result
= {0};
1420 amdgpu_va_handle va_handle
= NULL
;
1421 struct amdgpu_bo_info info
= {0};
1422 enum radeon_bo_domain initial
= 0;
1425 switch (whandle
->type
) {
1426 case WINSYS_HANDLE_TYPE_SHARED
:
1427 type
= amdgpu_bo_handle_type_gem_flink_name
;
1429 case WINSYS_HANDLE_TYPE_FD
:
1430 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1437 *stride
= whandle
->stride
;
1439 *offset
= whandle
->offset
;
1441 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1445 simple_mtx_lock(&ws
->bo_export_table_lock
);
1446 bo
= util_hash_table_get(ws
->bo_export_table
, result
.buf_handle
);
1448 /* If the amdgpu_winsys_bo instance already exists, bump the reference
1449 * counter and return it.
1452 p_atomic_inc(&bo
->base
.reference
.count
);
1453 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1455 /* Release the buffer handle, because we don't need it anymore.
1456 * This function is returning an existing buffer, which has its own
1459 amdgpu_bo_free(result
.buf_handle
);
1463 /* Get initial domains. */
1464 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1468 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1470 amdgpu_get_optimal_vm_alignment(ws
, result
.alloc_size
,
1472 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
);
1476 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1480 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1484 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1485 initial
|= RADEON_DOMAIN_VRAM
;
1486 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1487 initial
|= RADEON_DOMAIN_GTT
;
1489 /* Initialize the structure. */
1490 simple_mtx_init(&bo
->lock
, mtx_plain
);
1491 pipe_reference_init(&bo
->base
.reference
, 1);
1492 bo
->base
.alignment
= info
.phys_alignment
;
1493 bo
->bo
= result
.buf_handle
;
1494 bo
->base
.size
= result
.alloc_size
;
1495 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1498 bo
->u
.real
.va_handle
= va_handle
;
1499 bo
->initial_domain
= initial
;
1500 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1501 bo
->is_shared
= true;
1503 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1504 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1505 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1506 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1508 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1510 amdgpu_add_buffer_to_global_list(bo
);
1512 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1513 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1518 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1522 amdgpu_va_range_free(va_handle
);
1523 amdgpu_bo_free(result
.buf_handle
);
1527 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1528 unsigned stride
, unsigned offset
,
1529 unsigned slice_size
,
1530 struct winsys_handle
*whandle
)
1532 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1533 struct amdgpu_winsys
*ws
= bo
->ws
;
1534 enum amdgpu_bo_handle_type type
;
1537 /* Don't allow exports of slab entries and sparse buffers. */
1541 bo
->u
.real
.use_reusable_pool
= false;
1543 switch (whandle
->type
) {
1544 case WINSYS_HANDLE_TYPE_SHARED
:
1545 type
= amdgpu_bo_handle_type_gem_flink_name
;
1547 case WINSYS_HANDLE_TYPE_FD
:
1548 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1550 case WINSYS_HANDLE_TYPE_KMS
:
1551 type
= amdgpu_bo_handle_type_kms
;
1557 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1561 simple_mtx_lock(&ws
->bo_export_table_lock
);
1562 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1563 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1565 whandle
->stride
= stride
;
1566 whandle
->offset
= offset
;
1567 whandle
->offset
+= slice_size
* whandle
->layer
;
1568 bo
->is_shared
= true;
1572 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1573 void *pointer
, uint64_t size
)
1575 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1576 amdgpu_bo_handle buf_handle
;
1577 struct amdgpu_winsys_bo
*bo
;
1579 amdgpu_va_handle va_handle
;
1580 /* Avoid failure when the size is not page aligned */
1581 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1583 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1587 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1588 aligned_size
, &buf_handle
))
1591 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1593 amdgpu_get_optimal_vm_alignment(ws
, aligned_size
,
1594 ws
->info
.gart_page_size
),
1595 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
))
1596 goto error_va_alloc
;
1598 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1601 /* Initialize it. */
1602 bo
->is_user_ptr
= true;
1603 pipe_reference_init(&bo
->base
.reference
, 1);
1604 simple_mtx_init(&bo
->lock
, mtx_plain
);
1605 bo
->bo
= buf_handle
;
1606 bo
->base
.alignment
= 0;
1607 bo
->base
.size
= size
;
1608 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1610 bo
->cpu_ptr
= pointer
;
1612 bo
->u
.real
.va_handle
= va_handle
;
1613 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1614 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1616 ws
->allocated_gtt
+= aligned_size
;
1618 amdgpu_add_buffer_to_global_list(bo
);
1620 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1622 return (struct pb_buffer
*)bo
;
1625 amdgpu_va_range_free(va_handle
);
1628 amdgpu_bo_free(buf_handle
);
1635 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1637 return ((struct amdgpu_winsys_bo
*)buf
)->is_user_ptr
;
1640 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1642 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1644 return !bo
->bo
&& !bo
->sparse
;
1647 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1649 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1652 void amdgpu_bo_init_functions(struct amdgpu_screen_winsys
*ws
)
1654 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1655 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1656 ws
->base
.buffer_map
= amdgpu_bo_map
;
1657 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1658 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1659 ws
->base
.buffer_create
= amdgpu_buffer_create
;
1660 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1661 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1662 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1663 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1664 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1665 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1666 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1667 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;