2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
37 #include "amd/common/sid.h"
39 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
43 static struct pipe_fence_handle
*
44 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
45 unsigned ip_instance
, unsigned ring
)
47 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
49 fence
->reference
.count
= 1;
52 fence
->fence
.context
= ctx
->ctx
;
53 fence
->fence
.ip_type
= ip_type
;
54 fence
->fence
.ip_instance
= ip_instance
;
55 fence
->fence
.ring
= ring
;
56 fence
->submission_in_progress
= true;
57 p_atomic_inc(&ctx
->refcount
);
58 return (struct pipe_fence_handle
*)fence
;
61 static struct pipe_fence_handle
*
62 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
64 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
65 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
70 pipe_reference_init(&fence
->reference
, 1);
72 /* fence->ctx == NULL means that the fence is syncobj-based. */
74 /* Convert sync_file into syncobj. */
75 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
81 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
83 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
87 return (struct pipe_fence_handle
*)fence
;
90 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
91 struct pipe_fence_handle
*pfence
)
93 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
94 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
96 if (amdgpu_fence_is_syncobj(fence
)) {
99 /* Convert syncobj into sync_file. */
100 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
104 os_wait_until_zero(&fence
->submission_in_progress
, PIPE_TIMEOUT_INFINITE
);
106 /* Convert the amdgpu fence into a fence FD. */
108 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
109 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
116 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
118 uint64_t *user_fence_cpu_address
)
120 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
122 rfence
->fence
.fence
= seq_no
;
123 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
124 rfence
->submission_in_progress
= false;
127 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
129 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
131 rfence
->signalled
= true;
132 rfence
->submission_in_progress
= false;
135 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
138 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
141 uint64_t *user_fence_cpu
;
144 if (rfence
->signalled
)
147 /* Handle syncobjs. */
148 if (amdgpu_fence_is_syncobj(rfence
)) {
149 /* Absolute timeouts are only be used by BO fences, which aren't
150 * backed by syncobjs.
154 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
158 rfence
->signalled
= true;
163 abs_timeout
= timeout
;
165 abs_timeout
= os_time_get_absolute_timeout(timeout
);
167 /* The fence might not have a number assigned if its IB is being
168 * submitted in the other thread right now. Wait until the submission
170 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
174 user_fence_cpu
= rfence
->user_fence_cpu_address
;
175 if (user_fence_cpu
) {
176 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
177 rfence
->signalled
= true;
181 /* No timeout, just query: no need for the ioctl. */
182 if (!absolute
&& !timeout
)
186 /* Now use the libdrm query. */
187 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
189 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
192 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
197 /* This variable can only transition from false to true, so it doesn't
198 * matter if threads race for it. */
199 rfence
->signalled
= true;
205 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
206 struct pipe_fence_handle
*fence
,
209 return amdgpu_fence_wait(fence
, timeout
, false);
212 static struct pipe_fence_handle
*
213 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
215 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
216 struct pipe_fence_handle
*fence
= NULL
;
218 if (debug_get_option_noop())
221 if (cs
->next_fence
) {
222 amdgpu_fence_reference(&fence
, cs
->next_fence
);
226 fence
= amdgpu_fence_create(cs
->ctx
,
227 cs
->csc
->ib
[IB_MAIN
].ip_type
,
228 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
229 cs
->csc
->ib
[IB_MAIN
].ring
);
233 amdgpu_fence_reference(&cs
->next_fence
, fence
);
239 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
241 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
243 struct amdgpu_bo_alloc_request alloc_buffer
= {};
244 amdgpu_bo_handle buf_handle
;
249 ctx
->ws
= amdgpu_winsys(ws
);
251 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
253 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
255 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
259 if (ctx
->ws
->reserve_vmid
) {
260 r
= amdgpu_vm_reserve_vmid(ctx
->ctx
, 0);
262 fprintf(stderr
, "amdgpu: amdgpu_vm_reserve_vmid failed. (%i)\n", r
);
267 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
268 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
269 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
271 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
273 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
274 goto error_user_fence_alloc
;
277 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
279 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
280 goto error_user_fence_map
;
283 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
284 ctx
->user_fence_bo
= buf_handle
;
286 return (struct radeon_winsys_ctx
*)ctx
;
288 error_user_fence_map
:
289 amdgpu_bo_free(buf_handle
);
290 error_user_fence_alloc
:
291 amdgpu_cs_ctx_free(ctx
->ctx
);
297 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
299 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
302 static enum pipe_reset_status
303 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
305 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
306 uint32_t result
, hangs
;
309 /* Return a failure due to a rejected command submission. */
310 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
311 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
312 PIPE_INNOCENT_CONTEXT_RESET
;
315 /* Return a failure due to a GPU hang. */
316 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
318 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
319 return PIPE_NO_RESET
;
323 case AMDGPU_CTX_GUILTY_RESET
:
324 return PIPE_GUILTY_CONTEXT_RESET
;
325 case AMDGPU_CTX_INNOCENT_RESET
:
326 return PIPE_INNOCENT_CONTEXT_RESET
;
327 case AMDGPU_CTX_UNKNOWN_RESET
:
328 return PIPE_UNKNOWN_CONTEXT_RESET
;
329 case AMDGPU_CTX_NO_RESET
:
331 return PIPE_NO_RESET
;
335 /* COMMAND SUBMISSION */
337 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
339 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
340 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
341 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
;
344 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
346 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
347 cs
->ring_type
== RING_GFX
;
350 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
352 if (ring_type
== RING_GFX
)
353 return 4; /* for chaining */
358 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
360 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
361 int i
= cs
->buffer_indices_hashlist
[hash
];
362 struct amdgpu_cs_buffer
*buffers
;
366 buffers
= cs
->real_buffers
;
367 num_buffers
= cs
->num_real_buffers
;
368 } else if (!bo
->sparse
) {
369 buffers
= cs
->slab_buffers
;
370 num_buffers
= cs
->num_slab_buffers
;
372 buffers
= cs
->sparse_buffers
;
373 num_buffers
= cs
->num_sparse_buffers
;
376 /* not found or found */
377 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
380 /* Hash collision, look for the BO in the list of buffers linearly. */
381 for (i
= num_buffers
- 1; i
>= 0; i
--) {
382 if (buffers
[i
].bo
== bo
) {
383 /* Put this buffer in the hash list.
384 * This will prevent additional hash collisions if there are
385 * several consecutive lookup_buffer calls for the same buffer.
387 * Example: Assuming buffers A,B,C collide in the hash list,
388 * the following sequence of buffers:
389 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
390 * will collide here: ^ and here: ^,
391 * meaning that we should get very few collisions in the end. */
392 cs
->buffer_indices_hashlist
[hash
] = i
;
400 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
402 struct amdgpu_cs_buffer
*buffer
;
405 /* New buffer, check if the backing array is large enough. */
406 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
408 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
409 struct amdgpu_cs_buffer
*new_buffers
;
411 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
414 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
419 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
421 FREE(cs
->real_buffers
);
423 cs
->max_real_buffers
= new_max
;
424 cs
->real_buffers
= new_buffers
;
427 idx
= cs
->num_real_buffers
;
428 buffer
= &cs
->real_buffers
[idx
];
430 memset(buffer
, 0, sizeof(*buffer
));
431 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
432 p_atomic_inc(&bo
->num_cs_references
);
433 cs
->num_real_buffers
++;
439 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
441 struct amdgpu_cs_context
*cs
= acs
->csc
;
443 int idx
= amdgpu_lookup_buffer(cs
, bo
);
448 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
450 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
451 cs
->buffer_indices_hashlist
[hash
] = idx
;
453 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
454 acs
->main
.base
.used_vram
+= bo
->base
.size
;
455 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
456 acs
->main
.base
.used_gart
+= bo
->base
.size
;
461 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
462 struct amdgpu_winsys_bo
*bo
)
464 struct amdgpu_cs_context
*cs
= acs
->csc
;
465 struct amdgpu_cs_buffer
*buffer
;
467 int idx
= amdgpu_lookup_buffer(cs
, bo
);
473 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
477 /* New buffer, check if the backing array is large enough. */
478 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
480 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
481 struct amdgpu_cs_buffer
*new_buffers
;
483 new_buffers
= REALLOC(cs
->slab_buffers
,
484 cs
->max_slab_buffers
* sizeof(*new_buffers
),
485 new_max
* sizeof(*new_buffers
));
487 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
491 cs
->max_slab_buffers
= new_max
;
492 cs
->slab_buffers
= new_buffers
;
495 idx
= cs
->num_slab_buffers
;
496 buffer
= &cs
->slab_buffers
[idx
];
498 memset(buffer
, 0, sizeof(*buffer
));
499 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
500 buffer
->u
.slab
.real_idx
= real_idx
;
501 p_atomic_inc(&bo
->num_cs_references
);
502 cs
->num_slab_buffers
++;
504 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
505 cs
->buffer_indices_hashlist
[hash
] = idx
;
510 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
511 struct amdgpu_winsys_bo
*bo
)
513 struct amdgpu_cs_context
*cs
= acs
->csc
;
514 struct amdgpu_cs_buffer
*buffer
;
516 int idx
= amdgpu_lookup_buffer(cs
, bo
);
521 /* New buffer, check if the backing array is large enough. */
522 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
524 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
525 struct amdgpu_cs_buffer
*new_buffers
;
527 new_buffers
= REALLOC(cs
->sparse_buffers
,
528 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
529 new_max
* sizeof(*new_buffers
));
531 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
535 cs
->max_sparse_buffers
= new_max
;
536 cs
->sparse_buffers
= new_buffers
;
539 idx
= cs
->num_sparse_buffers
;
540 buffer
= &cs
->sparse_buffers
[idx
];
542 memset(buffer
, 0, sizeof(*buffer
));
543 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
544 p_atomic_inc(&bo
->num_cs_references
);
545 cs
->num_sparse_buffers
++;
547 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
548 cs
->buffer_indices_hashlist
[hash
] = idx
;
550 /* We delay adding the backing buffers until we really have to. However,
551 * we cannot delay accounting for memory use.
553 mtx_lock(&bo
->u
.sparse
.commit_lock
);
555 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
556 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
557 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
558 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
559 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
562 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
567 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
568 struct pb_buffer
*buf
,
569 enum radeon_bo_usage usage
,
570 enum radeon_bo_domain domains
,
571 enum radeon_bo_priority priority
)
573 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
574 * the buffer placement during command submission.
576 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
577 struct amdgpu_cs_context
*cs
= acs
->csc
;
578 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
579 struct amdgpu_cs_buffer
*buffer
;
582 /* Fast exit for no-op calls.
583 * This is very effective with suballocators and linear uploaders that
584 * are outside of the winsys.
586 if (bo
== cs
->last_added_bo
&&
587 (usage
& cs
->last_added_bo_usage
) == usage
&&
588 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
589 return cs
->last_added_bo_index
;
593 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
597 buffer
= &cs
->slab_buffers
[index
];
598 buffer
->usage
|= usage
;
600 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
601 index
= buffer
->u
.slab
.real_idx
;
603 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
608 buffer
= &cs
->real_buffers
[index
];
610 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
614 buffer
= &cs
->sparse_buffers
[index
];
617 buffer
->u
.real
.priority_usage
|= 1ull << priority
;
618 buffer
->usage
|= usage
;
620 cs
->last_added_bo
= bo
;
621 cs
->last_added_bo_index
= index
;
622 cs
->last_added_bo_usage
= buffer
->usage
;
623 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
627 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
628 enum ring_type ring_type
)
630 struct pb_buffer
*pb
;
632 unsigned buffer_size
;
634 /* Always create a buffer that is at least as large as the maximum seen IB
635 * size, aligned to a power of two (and multiplied by 4 to reduce internal
636 * fragmentation if chaining is not available). Limit to 512k dwords, which
637 * is the largest power of two that fits into the size field of the
638 * INDIRECT_BUFFER packet.
640 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
641 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
643 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
645 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
647 switch (ib
->ib_type
) {
649 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
652 unreachable("unhandled IB type");
655 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
656 ws
->info
.gart_page_size
,
658 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
659 (ring_type
== RING_GFX
||
660 ring_type
== RING_COMPUTE
||
661 ring_type
== RING_DMA
?
662 RADEON_FLAG_GTT_WC
: 0));
666 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
668 pb_reference(&pb
, NULL
);
672 pb_reference(&ib
->big_ib_buffer
, pb
);
673 pb_reference(&pb
, NULL
);
675 ib
->ib_mapped
= mapped
;
676 ib
->used_ib_space
= 0;
681 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
685 /* Smaller submits means the GPU gets busy sooner and there is less
686 * waiting for buffers and fences. Proof:
687 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
691 unreachable("bad ib_type");
695 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
696 enum ib_type ib_type
)
698 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
699 /* Small IBs are better than big IBs, because the GPU goes idle quicker
700 * and there is less waiting for buffers and fences. Proof:
701 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
703 struct amdgpu_ib
*ib
= NULL
;
704 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
705 unsigned ib_size
= 0;
710 ib_size
= 4 * 1024 * 4;
713 unreachable("unhandled IB type");
716 if (!amdgpu_cs_has_chaining(cs
)) {
717 ib_size
= MAX2(ib_size
,
718 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
719 amdgpu_ib_max_submit_dwords(ib_type
)));
722 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
724 ib
->base
.prev_dw
= 0;
725 ib
->base
.num_prev
= 0;
726 ib
->base
.current
.cdw
= 0;
727 ib
->base
.current
.buf
= NULL
;
729 /* Allocate a new buffer for IBs if the current buffer is all used. */
730 if (!ib
->big_ib_buffer
||
731 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
732 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
736 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
738 /* ib_bytes is in dwords and the conversion to bytes will be done before
740 ib
->ptr_ib_size
= &info
->ib_bytes
;
741 ib
->ptr_ib_size_inside_ib
= false;
743 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
744 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
746 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
748 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
749 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
753 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
755 if (ib
->ptr_ib_size_inside_ib
) {
756 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
757 S_3F2_CHAIN(1) | S_3F2_VALID(1);
759 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
763 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
765 amdgpu_set_ib_size(ib
);
766 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
767 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
770 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
771 enum ring_type ring_type
)
775 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
779 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
783 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
787 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
791 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
796 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_GFX
;
800 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
801 cs
->last_added_bo
= NULL
;
805 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
809 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
810 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
811 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
813 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
814 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
815 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
817 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
818 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
819 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
821 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
822 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
824 cs
->num_real_buffers
= 0;
825 cs
->num_slab_buffers
= 0;
826 cs
->num_sparse_buffers
= 0;
827 cs
->num_fence_dependencies
= 0;
828 amdgpu_fence_reference(&cs
->fence
, NULL
);
830 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
831 cs
->last_added_bo
= NULL
;
834 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
836 amdgpu_cs_context_cleanup(cs
);
838 FREE(cs
->real_buffers
);
840 FREE(cs
->slab_buffers
);
841 FREE(cs
->sparse_buffers
);
842 FREE(cs
->fence_dependencies
);
846 static struct radeon_winsys_cs
*
847 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
848 enum ring_type ring_type
,
849 void (*flush
)(void *ctx
, unsigned flags
,
850 struct pipe_fence_handle
**fence
),
853 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
854 struct amdgpu_cs
*cs
;
856 cs
= CALLOC_STRUCT(amdgpu_cs
);
861 util_queue_fence_init(&cs
->flush_completed
);
864 cs
->flush_cs
= flush
;
865 cs
->flush_data
= flush_ctx
;
866 cs
->ring_type
= ring_type
;
868 struct amdgpu_cs_fence_info fence_info
;
869 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
870 fence_info
.offset
= cs
->ring_type
;
871 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
873 cs
->main
.ib_type
= IB_MAIN
;
875 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
880 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
881 amdgpu_destroy_cs_context(&cs
->csc1
);
886 /* Set the first submission context as current. */
890 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
891 amdgpu_destroy_cs_context(&cs
->csc2
);
892 amdgpu_destroy_cs_context(&cs
->csc1
);
897 p_atomic_inc(&ctx
->ws
->num_cs
);
898 return &cs
->main
.base
;
901 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
906 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
908 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
909 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
910 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
912 uint32_t *new_ptr_ib_size
;
914 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
916 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
919 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
921 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
924 if (!amdgpu_cs_has_chaining(cs
))
927 /* Allocate a new chunk */
928 if (rcs
->num_prev
>= rcs
->max_prev
) {
929 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
930 struct radeon_winsys_cs_chunk
*new_prev
;
932 new_prev
= REALLOC(rcs
->prev
,
933 sizeof(*new_prev
) * rcs
->max_prev
,
934 sizeof(*new_prev
) * new_max_prev
);
938 rcs
->prev
= new_prev
;
939 rcs
->max_prev
= new_max_prev
;
942 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
945 assert(ib
->used_ib_space
== 0);
946 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
948 /* This space was originally reserved. */
949 rcs
->current
.max_dw
+= 4;
950 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
952 /* Pad with NOPs and add INDIRECT_BUFFER packet */
953 while ((rcs
->current
.cdw
& 7) != 4)
954 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
956 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
957 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
958 radeon_emit(rcs
, va
);
959 radeon_emit(rcs
, va
>> 32);
960 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
962 assert((rcs
->current
.cdw
& 7) == 0);
963 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
965 amdgpu_set_ib_size(ib
);
966 ib
->ptr_ib_size
= new_ptr_ib_size
;
967 ib
->ptr_ib_size_inside_ib
= true;
969 /* Hook up the new chunk */
970 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
971 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
972 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
975 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
976 ib
->base
.current
.cdw
= 0;
978 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
979 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
981 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
982 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
987 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
988 struct radeon_bo_list_item
*list
)
990 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
994 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
995 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
996 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
997 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1000 return cs
->num_real_buffers
;
1003 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
1005 unsigned idx
= cs
->num_fence_dependencies
++;
1007 if (idx
>= cs
->max_fence_dependencies
) {
1009 const unsigned increment
= 8;
1011 cs
->max_fence_dependencies
= idx
+ increment
;
1012 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1013 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1014 /* Clear the newly-allocated elements. */
1015 memset(cs
->fence_dependencies
+ idx
, 0,
1016 increment
* sizeof(cs
->fence_dependencies
[0]));
1021 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1022 struct amdgpu_fence
*fence
)
1024 struct amdgpu_cs_context
*cs
= acs
->csc
;
1026 if (!amdgpu_fence_is_syncobj(fence
) &&
1027 fence
->ctx
== acs
->ctx
&&
1028 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1029 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1030 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1033 return amdgpu_fence_wait((void *)fence
, 0, false);
1036 static void amdgpu_cs_add_fence_dependency(struct radeon_winsys_cs
*rws
,
1037 struct pipe_fence_handle
*pfence
)
1039 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1040 struct amdgpu_cs_context
*cs
= acs
->csc
;
1041 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1043 if (is_noop_fence_dependency(acs
, fence
))
1046 unsigned idx
= add_fence_dependency_entry(cs
);
1047 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1048 (struct pipe_fence_handle
*)fence
);
1051 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1052 struct amdgpu_cs_buffer
*buffer
)
1054 struct amdgpu_cs_context
*cs
= acs
->csc
;
1055 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1056 unsigned new_num_fences
= 0;
1058 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1059 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1061 if (is_noop_fence_dependency(acs
, bo_fence
))
1064 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1067 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1070 unsigned idx
= add_fence_dependency_entry(cs
);
1071 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1072 (struct pipe_fence_handle
*)bo_fence
);
1075 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1076 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1078 bo
->num_fences
= new_num_fences
;
1081 /* Add the given list of fences to the buffer's fence list.
1083 * Must be called with the winsys bo_fence_lock held.
1085 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1086 unsigned num_fences
,
1087 struct pipe_fence_handle
**fences
)
1089 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1090 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1091 struct pipe_fence_handle
**new_fences
=
1093 bo
->num_fences
* sizeof(*new_fences
),
1094 new_max_fences
* sizeof(*new_fences
));
1095 if (likely(new_fences
)) {
1096 bo
->fences
= new_fences
;
1097 bo
->max_fences
= new_max_fences
;
1101 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1102 if (!bo
->num_fences
)
1105 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1106 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1108 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1114 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1115 bo
->fences
[bo
->num_fences
] = NULL
;
1116 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1121 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1122 struct pipe_fence_handle
*fence
,
1123 unsigned num_buffers
,
1124 struct amdgpu_cs_buffer
*buffers
)
1126 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1127 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1128 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1130 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1131 p_atomic_inc(&bo
->num_active_ioctls
);
1132 amdgpu_add_fences(bo
, 1, &fence
);
1136 /* Since the kernel driver doesn't synchronize execution between different
1137 * rings automatically, we have to add fence dependencies manually.
1139 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1141 struct amdgpu_cs_context
*cs
= acs
->csc
;
1143 cs
->num_fence_dependencies
= 0;
1145 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1146 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1147 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1150 /* Add backing of sparse buffers to the buffer list.
1152 * This is done late, during submission, to keep the buffer list short before
1153 * submit, and to avoid managing fences for the backing buffers.
1155 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1157 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1158 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1159 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1161 mtx_lock(&bo
->u
.sparse
.commit_lock
);
1163 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1164 /* We can directly add the buffer here, because we know that each
1165 * backing buffer occurs only once.
1167 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1169 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1170 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1174 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1175 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1176 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1179 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1185 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1187 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1188 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1189 struct amdgpu_cs_context
*cs
= acs
->cst
;
1191 amdgpu_bo_list_handle bo_list
= NULL
;
1192 uint64_t seq_no
= 0;
1193 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1195 /* Create the buffer list.
1196 * Use a buffer list containing all allocated buffers if requested.
1198 if (ws
->debug_all_bos
) {
1199 struct amdgpu_winsys_bo
*bo
;
1200 amdgpu_bo_handle
*handles
;
1203 mtx_lock(&ws
->global_bo_list_lock
);
1205 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1207 mtx_unlock(&ws
->global_bo_list_lock
);
1208 amdgpu_cs_context_cleanup(cs
);
1209 cs
->error_code
= -ENOMEM
;
1213 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1214 assert(num
< ws
->num_buffers
);
1215 handles
[num
++] = bo
->bo
;
1218 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1219 handles
, NULL
, &bo_list
);
1221 mtx_unlock(&ws
->global_bo_list_lock
);
1223 unsigned num_handles
;
1225 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1230 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1234 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1235 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1237 if (!cs
->handles
|| !cs
->flags
) {
1238 cs
->max_real_submit
= 0;
1245 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1246 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1248 if (buffer
->bo
->is_local
)
1251 assert(buffer
->u
.real
.priority_usage
!= 0);
1253 cs
->handles
[num_handles
] = buffer
->bo
->bo
;
1254 cs
->flags
[num_handles
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1258 if (acs
->ring_type
== RING_GFX
)
1259 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1262 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1263 cs
->handles
, cs
->flags
, &bo_list
);
1271 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1272 amdgpu_fence_signalled(cs
->fence
);
1277 if (acs
->ctx
->num_rejected_cs
) {
1280 struct drm_amdgpu_cs_chunk chunks
[4];
1281 unsigned num_chunks
= 0;
1283 /* Convert from dwords to bytes. */
1284 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1287 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1288 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1289 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1293 if (has_user_fence
) {
1294 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1295 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1296 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1301 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1302 unsigned num_syncobj_dependencies
= 0;
1304 if (num_dependencies
) {
1305 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1306 alloca(num_dependencies
* sizeof(*dep_chunk
));
1309 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1310 struct amdgpu_fence
*fence
=
1311 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1313 if (amdgpu_fence_is_syncobj(fence
)) {
1314 num_syncobj_dependencies
++;
1318 assert(!fence
->submission_in_progress
);
1319 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1322 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1323 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1324 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1328 /* Syncobj dependencies. */
1329 if (num_syncobj_dependencies
) {
1330 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1331 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1334 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1335 struct amdgpu_fence
*fence
=
1336 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1338 if (!amdgpu_fence_is_syncobj(fence
))
1341 assert(!fence
->submission_in_progress
);
1342 sem_chunk
[num
++].handle
= fence
->syncobj
;
1345 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1346 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1347 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1351 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1353 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1354 num_chunks
, chunks
, &seq_no
);
1360 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1361 else if (r
== -ECANCELED
)
1362 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1364 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1365 "see dmesg for more information (%i).\n", r
);
1367 amdgpu_fence_signalled(cs
->fence
);
1369 acs
->ctx
->num_rejected_cs
++;
1370 ws
->num_total_rejected_cs
++;
1373 uint64_t *user_fence
= NULL
;
1376 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1377 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1382 amdgpu_bo_list_destroy(bo_list
);
1385 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1386 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1387 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1388 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1389 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1390 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1392 amdgpu_cs_context_cleanup(cs
);
1395 /* Make sure the previous submission is completed. */
1396 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1398 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1400 /* Wait for any pending ioctl of this CS to complete. */
1401 util_queue_fence_wait(&cs
->flush_completed
);
1404 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1406 struct pipe_fence_handle
**fence
)
1408 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1409 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1412 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1414 switch (cs
->ring_type
) {
1416 /* pad DMA ring to 8 DWs */
1417 if (ws
->info
.chip_class
<= SI
) {
1418 while (rcs
->current
.cdw
& 7)
1419 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1421 while (rcs
->current
.cdw
& 7)
1422 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1426 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1427 if (ws
->info
.gfx_ib_pad_with_type2
) {
1428 while (rcs
->current
.cdw
& 7)
1429 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1431 while (rcs
->current
.cdw
& 7)
1432 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1434 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1437 while (rcs
->current
.cdw
& 15)
1438 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1441 while (rcs
->current
.cdw
& 15)
1442 radeon_emit(rcs
, 0x81ff); /* nop packet */
1448 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1449 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1452 /* If the CS is not empty or overflowed.... */
1453 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1454 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1455 !debug_get_option_noop())) {
1456 struct amdgpu_cs_context
*cur
= cs
->csc
;
1459 amdgpu_ib_finalize(&cs
->main
);
1461 /* Create a fence. */
1462 amdgpu_fence_reference(&cur
->fence
, NULL
);
1463 if (cs
->next_fence
) {
1464 /* just move the reference */
1465 cur
->fence
= cs
->next_fence
;
1466 cs
->next_fence
= NULL
;
1468 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1469 cur
->ib
[IB_MAIN
].ip_type
,
1470 cur
->ib
[IB_MAIN
].ip_instance
,
1471 cur
->ib
[IB_MAIN
].ring
);
1474 amdgpu_fence_reference(fence
, cur
->fence
);
1476 amdgpu_cs_sync_flush(rcs
);
1480 * This fence must be held until the submission is queued to ensure
1481 * that the order of fence dependency updates matches the order of
1484 mtx_lock(&ws
->bo_fence_lock
);
1485 amdgpu_add_fence_dependencies_bo_lists(cs
);
1487 /* Swap command streams. "cst" is going to be submitted. */
1492 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1493 amdgpu_cs_submit_ib
, NULL
);
1494 /* The submission has been queued, unlock the fence now. */
1495 mtx_unlock(&ws
->bo_fence_lock
);
1497 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1498 amdgpu_cs_sync_flush(rcs
);
1499 error_code
= cur
->error_code
;
1502 amdgpu_cs_context_cleanup(cs
->csc
);
1505 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1507 cs
->main
.base
.used_gart
= 0;
1508 cs
->main
.base
.used_vram
= 0;
1510 if (cs
->ring_type
== RING_GFX
)
1512 else if (cs
->ring_type
== RING_DMA
)
1518 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1520 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1522 amdgpu_cs_sync_flush(rcs
);
1523 util_queue_fence_destroy(&cs
->flush_completed
);
1524 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1525 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1526 FREE(cs
->main
.base
.prev
);
1527 amdgpu_destroy_cs_context(&cs
->csc1
);
1528 amdgpu_destroy_cs_context(&cs
->csc2
);
1529 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1533 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1534 struct pb_buffer
*_buf
,
1535 enum radeon_bo_usage usage
)
1537 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1538 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1540 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1543 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1545 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1546 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1547 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1548 ws
->base
.cs_create
= amdgpu_cs_create
;
1549 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1550 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1551 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1552 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1553 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1554 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1555 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1556 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1557 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1558 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1559 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1560 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1561 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1562 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;