2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 util_queue_fence_init(&fence
->submitted
);
54 util_queue_fence_reset(&fence
->submitted
);
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static struct pipe_fence_handle
*
60 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
62 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
63 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
69 pipe_reference_init(&fence
->reference
, 1);
72 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
78 util_queue_fence_init(&fence
->submitted
);
80 assert(amdgpu_fence_is_syncobj(fence
));
81 return (struct pipe_fence_handle
*)fence
;
84 static struct pipe_fence_handle
*
85 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
87 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
88 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
93 pipe_reference_init(&fence
->reference
, 1);
95 /* fence->ctx == NULL means that the fence is syncobj-based. */
97 /* Convert sync_file into syncobj. */
98 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
104 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
106 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
111 util_queue_fence_init(&fence
->submitted
);
113 return (struct pipe_fence_handle
*)fence
;
116 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
117 struct pipe_fence_handle
*pfence
)
119 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
120 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
122 if (amdgpu_fence_is_syncobj(fence
)) {
125 /* Convert syncobj into sync_file. */
126 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
130 util_queue_fence_wait(&fence
->submitted
);
132 /* Convert the amdgpu fence into a fence FD. */
134 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
135 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
142 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
144 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
148 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
154 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
159 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
163 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
165 uint64_t *user_fence_cpu_address
)
167 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
169 afence
->fence
.fence
= seq_no
;
170 afence
->user_fence_cpu_address
= user_fence_cpu_address
;
171 util_queue_fence_signal(&afence
->submitted
);
174 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
176 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
178 afence
->signalled
= true;
179 util_queue_fence_signal(&afence
->submitted
);
182 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
185 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
188 uint64_t *user_fence_cpu
;
191 if (afence
->signalled
)
194 /* Handle syncobjs. */
195 if (amdgpu_fence_is_syncobj(afence
)) {
196 /* Absolute timeouts are only be used by BO fences, which aren't
197 * backed by syncobjs.
201 if (amdgpu_cs_syncobj_wait(afence
->ws
->dev
, &afence
->syncobj
, 1,
205 afence
->signalled
= true;
210 abs_timeout
= timeout
;
212 abs_timeout
= os_time_get_absolute_timeout(timeout
);
214 /* The fence might not have a number assigned if its IB is being
215 * submitted in the other thread right now. Wait until the submission
217 if (!util_queue_fence_wait_timeout(&afence
->submitted
, abs_timeout
))
220 user_fence_cpu
= afence
->user_fence_cpu_address
;
221 if (user_fence_cpu
) {
222 if (*user_fence_cpu
>= afence
->fence
.fence
) {
223 afence
->signalled
= true;
227 /* No timeout, just query: no need for the ioctl. */
228 if (!absolute
&& !timeout
)
232 /* Now use the libdrm query. */
233 r
= amdgpu_cs_query_fence_status(&afence
->fence
,
235 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
238 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
243 /* This variable can only transition from false to true, so it doesn't
244 * matter if threads race for it. */
245 afence
->signalled
= true;
251 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
252 struct pipe_fence_handle
*fence
,
255 return amdgpu_fence_wait(fence
, timeout
, false);
258 static struct pipe_fence_handle
*
259 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
261 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
262 struct pipe_fence_handle
*fence
= NULL
;
264 if (debug_get_option_noop())
267 if (cs
->next_fence
) {
268 amdgpu_fence_reference(&fence
, cs
->next_fence
);
272 fence
= amdgpu_fence_create(cs
->ctx
,
273 cs
->csc
->ib
[IB_MAIN
].ip_type
,
274 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
275 cs
->csc
->ib
[IB_MAIN
].ring
);
279 amdgpu_fence_reference(&cs
->next_fence
, fence
);
285 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
287 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
289 struct amdgpu_bo_alloc_request alloc_buffer
= {};
290 amdgpu_bo_handle buf_handle
;
295 ctx
->ws
= amdgpu_winsys(ws
);
297 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
299 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
301 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
305 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
306 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
307 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
309 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
311 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
312 goto error_user_fence_alloc
;
315 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
317 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
318 goto error_user_fence_map
;
321 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
322 ctx
->user_fence_bo
= buf_handle
;
324 return (struct radeon_winsys_ctx
*)ctx
;
326 error_user_fence_map
:
327 amdgpu_bo_free(buf_handle
);
328 error_user_fence_alloc
:
329 amdgpu_cs_ctx_free(ctx
->ctx
);
335 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
337 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
340 static enum pipe_reset_status
341 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
343 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
346 /* Return a failure due to a GPU hang. */
347 if (ctx
->ws
->info
.drm_minor
>= 24) {
350 r
= amdgpu_cs_query_reset_state2(ctx
->ctx
, &flags
);
352 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
353 return PIPE_NO_RESET
;
356 if (flags
& AMDGPU_CTX_QUERY2_FLAGS_RESET
) {
357 if (flags
& AMDGPU_CTX_QUERY2_FLAGS_GUILTY
)
358 return PIPE_GUILTY_CONTEXT_RESET
;
360 return PIPE_INNOCENT_CONTEXT_RESET
;
363 uint32_t result
, hangs
;
365 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
367 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
368 return PIPE_NO_RESET
;
372 case AMDGPU_CTX_GUILTY_RESET
:
373 return PIPE_GUILTY_CONTEXT_RESET
;
374 case AMDGPU_CTX_INNOCENT_RESET
:
375 return PIPE_INNOCENT_CONTEXT_RESET
;
376 case AMDGPU_CTX_UNKNOWN_RESET
:
377 return PIPE_UNKNOWN_CONTEXT_RESET
;
381 /* Return a failure due to a rejected command submission. */
382 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
383 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
384 PIPE_INNOCENT_CONTEXT_RESET
;
386 return PIPE_NO_RESET
;
389 /* COMMAND SUBMISSION */
391 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
393 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
394 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
395 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
396 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
397 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
&&
398 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_JPEG
;
401 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
403 return cs
->ctx
->ws
->info
.chip_class
>= GFX7
&&
404 (cs
->ring_type
== RING_GFX
|| cs
->ring_type
== RING_COMPUTE
);
407 static unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs
*cs
)
409 if (amdgpu_cs_has_chaining(cs
))
410 return 4; /* for chaining */
415 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
417 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
418 int i
= cs
->buffer_indices_hashlist
[hash
];
419 struct amdgpu_cs_buffer
*buffers
;
423 buffers
= cs
->real_buffers
;
424 num_buffers
= cs
->num_real_buffers
;
425 } else if (!bo
->sparse
) {
426 buffers
= cs
->slab_buffers
;
427 num_buffers
= cs
->num_slab_buffers
;
429 buffers
= cs
->sparse_buffers
;
430 num_buffers
= cs
->num_sparse_buffers
;
433 /* not found or found */
434 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
437 /* Hash collision, look for the BO in the list of buffers linearly. */
438 for (i
= num_buffers
- 1; i
>= 0; i
--) {
439 if (buffers
[i
].bo
== bo
) {
440 /* Put this buffer in the hash list.
441 * This will prevent additional hash collisions if there are
442 * several consecutive lookup_buffer calls for the same buffer.
444 * Example: Assuming buffers A,B,C collide in the hash list,
445 * the following sequence of buffers:
446 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
447 * will collide here: ^ and here: ^,
448 * meaning that we should get very few collisions in the end. */
449 cs
->buffer_indices_hashlist
[hash
] = i
;
457 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
459 struct amdgpu_cs_buffer
*buffer
;
462 /* New buffer, check if the backing array is large enough. */
463 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
465 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
466 struct amdgpu_cs_buffer
*new_buffers
;
468 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
471 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
476 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
478 FREE(cs
->real_buffers
);
480 cs
->max_real_buffers
= new_max
;
481 cs
->real_buffers
= new_buffers
;
484 idx
= cs
->num_real_buffers
;
485 buffer
= &cs
->real_buffers
[idx
];
487 memset(buffer
, 0, sizeof(*buffer
));
488 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
489 p_atomic_inc(&bo
->num_cs_references
);
490 cs
->num_real_buffers
++;
496 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
498 struct amdgpu_cs_context
*cs
= acs
->csc
;
500 int idx
= amdgpu_lookup_buffer(cs
, bo
);
505 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
507 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
508 cs
->buffer_indices_hashlist
[hash
] = idx
;
510 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
511 acs
->main
.base
.used_vram
+= bo
->base
.size
;
512 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
513 acs
->main
.base
.used_gart
+= bo
->base
.size
;
518 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
519 struct amdgpu_winsys_bo
*bo
)
521 struct amdgpu_cs_context
*cs
= acs
->csc
;
522 struct amdgpu_cs_buffer
*buffer
;
524 int idx
= amdgpu_lookup_buffer(cs
, bo
);
530 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
534 /* New buffer, check if the backing array is large enough. */
535 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
537 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
538 struct amdgpu_cs_buffer
*new_buffers
;
540 new_buffers
= REALLOC(cs
->slab_buffers
,
541 cs
->max_slab_buffers
* sizeof(*new_buffers
),
542 new_max
* sizeof(*new_buffers
));
544 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
548 cs
->max_slab_buffers
= new_max
;
549 cs
->slab_buffers
= new_buffers
;
552 idx
= cs
->num_slab_buffers
;
553 buffer
= &cs
->slab_buffers
[idx
];
555 memset(buffer
, 0, sizeof(*buffer
));
556 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
557 buffer
->u
.slab
.real_idx
= real_idx
;
558 p_atomic_inc(&bo
->num_cs_references
);
559 cs
->num_slab_buffers
++;
561 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
562 cs
->buffer_indices_hashlist
[hash
] = idx
;
567 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
568 struct amdgpu_winsys_bo
*bo
)
570 struct amdgpu_cs_context
*cs
= acs
->csc
;
571 struct amdgpu_cs_buffer
*buffer
;
573 int idx
= amdgpu_lookup_buffer(cs
, bo
);
578 /* New buffer, check if the backing array is large enough. */
579 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
581 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
582 struct amdgpu_cs_buffer
*new_buffers
;
584 new_buffers
= REALLOC(cs
->sparse_buffers
,
585 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
586 new_max
* sizeof(*new_buffers
));
588 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
592 cs
->max_sparse_buffers
= new_max
;
593 cs
->sparse_buffers
= new_buffers
;
596 idx
= cs
->num_sparse_buffers
;
597 buffer
= &cs
->sparse_buffers
[idx
];
599 memset(buffer
, 0, sizeof(*buffer
));
600 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
601 p_atomic_inc(&bo
->num_cs_references
);
602 cs
->num_sparse_buffers
++;
604 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
605 cs
->buffer_indices_hashlist
[hash
] = idx
;
607 /* We delay adding the backing buffers until we really have to. However,
608 * we cannot delay accounting for memory use.
610 simple_mtx_lock(&bo
->lock
);
612 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
613 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
614 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
615 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
616 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
619 simple_mtx_unlock(&bo
->lock
);
624 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
625 struct pb_buffer
*buf
,
626 enum radeon_bo_usage usage
,
627 enum radeon_bo_domain domains
,
628 enum radeon_bo_priority priority
)
630 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
631 * the buffer placement during command submission.
633 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
634 struct amdgpu_cs_context
*cs
= acs
->csc
;
635 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
636 struct amdgpu_cs_buffer
*buffer
;
639 /* Fast exit for no-op calls.
640 * This is very effective with suballocators and linear uploaders that
641 * are outside of the winsys.
643 if (bo
== cs
->last_added_bo
&&
644 (usage
& cs
->last_added_bo_usage
) == usage
&&
645 (1u << priority
) & cs
->last_added_bo_priority_usage
)
646 return cs
->last_added_bo_index
;
650 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
654 buffer
= &cs
->slab_buffers
[index
];
655 buffer
->usage
|= usage
;
657 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
658 index
= buffer
->u
.slab
.real_idx
;
660 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
665 buffer
= &cs
->real_buffers
[index
];
667 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
671 buffer
= &cs
->sparse_buffers
[index
];
674 buffer
->u
.real
.priority_usage
|= 1u << priority
;
675 buffer
->usage
|= usage
;
677 cs
->last_added_bo
= bo
;
678 cs
->last_added_bo_index
= index
;
679 cs
->last_added_bo_usage
= buffer
->usage
;
680 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
684 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
,
685 struct amdgpu_ib
*ib
,
686 enum ring_type ring_type
)
688 struct pb_buffer
*pb
;
690 unsigned buffer_size
;
692 /* Always create a buffer that is at least as large as the maximum seen IB
693 * size, aligned to a power of two (and multiplied by 4 to reduce internal
694 * fragmentation if chaining is not available). Limit to 512k dwords, which
695 * is the largest power of two that fits into the size field of the
696 * INDIRECT_BUFFER packet.
698 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
699 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
701 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
703 const unsigned min_size
= MAX2(ib
->max_check_space_size
, 8 * 1024 * 4);
704 const unsigned max_size
= 512 * 1024 * 4;
706 buffer_size
= MIN2(buffer_size
, max_size
);
707 buffer_size
= MAX2(buffer_size
, min_size
); /* min_size is more important */
709 pb
= amdgpu_bo_create(ws
, buffer_size
,
710 ws
->info
.gart_page_size
,
712 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
713 (ring_type
== RING_GFX
||
714 ring_type
== RING_COMPUTE
||
715 ring_type
== RING_DMA
?
716 RADEON_FLAG_32BIT
| RADEON_FLAG_GTT_WC
: 0));
720 mapped
= amdgpu_bo_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
722 pb_reference(&pb
, NULL
);
726 pb_reference(&ib
->big_ib_buffer
, pb
);
727 pb_reference(&pb
, NULL
);
729 ib
->ib_mapped
= mapped
;
730 ib
->used_ib_space
= 0;
735 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
737 /* The maximum IB size including all chained IBs. */
740 /* Smaller submits means the GPU gets busy sooner and there is less
741 * waiting for buffers and fences. Proof:
742 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
745 case IB_PARALLEL_COMPUTE
:
746 /* Always chain this IB. */
749 unreachable("bad ib_type");
753 static bool amdgpu_get_new_ib(struct amdgpu_winsys
*ws
, struct amdgpu_cs
*cs
,
754 enum ib_type ib_type
)
756 /* Small IBs are better than big IBs, because the GPU goes idle quicker
757 * and there is less waiting for buffers and fences. Proof:
758 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
760 struct amdgpu_ib
*ib
= NULL
;
761 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
762 /* This is the minimum size of a contiguous IB. */
763 unsigned ib_size
= 4 * 1024 * 4;
766 case IB_PARALLEL_COMPUTE
:
767 ib
= &cs
->compute_ib
;
773 unreachable("unhandled IB type");
776 /* Always allocate at least the size of the biggest cs_check_space call,
777 * because precisely the last call might have requested this size.
779 ib_size
= MAX2(ib_size
, ib
->max_check_space_size
);
781 if (!amdgpu_cs_has_chaining(cs
)) {
782 ib_size
= MAX2(ib_size
,
783 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
784 amdgpu_ib_max_submit_dwords(ib_type
)));
787 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
789 ib
->base
.prev_dw
= 0;
790 ib
->base
.num_prev
= 0;
791 ib
->base
.current
.cdw
= 0;
792 ib
->base
.current
.buf
= NULL
;
794 /* Allocate a new buffer for IBs if the current buffer is all used. */
795 if (!ib
->big_ib_buffer
||
796 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
797 if (!amdgpu_ib_new_buffer(ws
, ib
, cs
->ring_type
))
801 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
803 /* ib_bytes is in dwords and the conversion to bytes will be done before
805 ib
->ptr_ib_size
= &info
->ib_bytes
;
806 ib
->ptr_ib_size_inside_ib
= false;
808 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
809 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
811 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
813 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
814 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
);
815 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
816 ib
->base
.gpu_address
= info
->va_start
;
820 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
822 if (ib
->ptr_ib_size_inside_ib
) {
823 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
824 S_3F2_CHAIN(1) | S_3F2_VALID(1);
826 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
830 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
832 amdgpu_set_ib_size(ib
);
833 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
834 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_alignment
);
835 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
838 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
839 struct amdgpu_cs_context
*cs
,
840 enum ring_type ring_type
)
844 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
848 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
852 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
856 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
860 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
864 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
868 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
873 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
874 AMDGPU_HW_IP_COMPUTE
;
876 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
877 * invalidation is the beginning of IBs (the previous commit does that),
878 * because completion of an IB doesn't care about the state of GPU caches,
879 * but the beginning of an IB does. Draw calls from multiple IBs can be
880 * executed in parallel, so draw calls from the current IB can finish after
881 * the next IB starts drawing, and so the cache flush at the end of IB
884 if (ws
->info
.drm_minor
>= 26)
885 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
892 cs
->ib
[IB_PARALLEL_COMPUTE
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
893 cs
->ib
[IB_PARALLEL_COMPUTE
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
895 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
896 cs
->last_added_bo
= NULL
;
900 static void cleanup_fence_list(struct amdgpu_fence_list
*fences
)
902 for (unsigned i
= 0; i
< fences
->num
; i
++)
903 amdgpu_fence_reference(&fences
->list
[i
], NULL
);
907 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
911 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
912 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
913 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
915 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
916 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
917 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
919 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
920 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
921 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
923 cleanup_fence_list(&cs
->fence_dependencies
);
924 cleanup_fence_list(&cs
->syncobj_dependencies
);
925 cleanup_fence_list(&cs
->syncobj_to_signal
);
926 cleanup_fence_list(&cs
->compute_fence_dependencies
);
927 cleanup_fence_list(&cs
->compute_start_fence_dependencies
);
929 cs
->num_real_buffers
= 0;
930 cs
->num_slab_buffers
= 0;
931 cs
->num_sparse_buffers
= 0;
932 amdgpu_fence_reference(&cs
->fence
, NULL
);
934 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
935 cs
->last_added_bo
= NULL
;
938 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
940 amdgpu_cs_context_cleanup(cs
);
941 FREE(cs
->real_buffers
);
942 FREE(cs
->slab_buffers
);
943 FREE(cs
->sparse_buffers
);
944 FREE(cs
->fence_dependencies
.list
);
945 FREE(cs
->syncobj_dependencies
.list
);
946 FREE(cs
->syncobj_to_signal
.list
);
947 FREE(cs
->compute_fence_dependencies
.list
);
948 FREE(cs
->compute_start_fence_dependencies
.list
);
952 static struct radeon_cmdbuf
*
953 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
954 enum ring_type ring_type
,
955 void (*flush
)(void *ctx
, unsigned flags
,
956 struct pipe_fence_handle
**fence
),
958 bool stop_exec_on_failure
)
960 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
961 struct amdgpu_cs
*cs
;
963 cs
= CALLOC_STRUCT(amdgpu_cs
);
968 util_queue_fence_init(&cs
->flush_completed
);
971 cs
->flush_cs
= flush
;
972 cs
->flush_data
= flush_ctx
;
973 cs
->ring_type
= ring_type
;
974 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
976 struct amdgpu_cs_fence_info fence_info
;
977 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
978 fence_info
.offset
= cs
->ring_type
;
979 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
981 cs
->main
.ib_type
= IB_MAIN
;
982 cs
->compute_ib
.ib_type
= IB_PARALLEL_COMPUTE
;
984 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
989 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
990 amdgpu_destroy_cs_context(&cs
->csc1
);
995 /* Set the first submission context as current. */
999 if (!amdgpu_get_new_ib(ctx
->ws
, cs
, IB_MAIN
)) {
1000 amdgpu_destroy_cs_context(&cs
->csc2
);
1001 amdgpu_destroy_cs_context(&cs
->csc1
);
1006 p_atomic_inc(&ctx
->ws
->num_cs
);
1007 return &cs
->main
.base
;
1010 static struct radeon_cmdbuf
*
1011 amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf
*ib
,
1012 bool uses_gds_ordered_append
)
1014 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)ib
;
1015 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1017 if (cs
->ring_type
!= RING_GFX
)
1020 /* only one secondary IB can be added */
1021 if (cs
->compute_ib
.ib_mapped
)
1024 /* Allocate the compute IB. */
1025 if (!amdgpu_get_new_ib(ws
, cs
, IB_PARALLEL_COMPUTE
))
1028 if (uses_gds_ordered_append
) {
1029 cs
->csc1
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1030 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1031 cs
->csc2
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1032 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1034 return &cs
->compute_ib
.base
;
1037 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
1042 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
,
1043 bool force_chaining
)
1045 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
1046 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
1047 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
1048 unsigned cs_epilog_dw
= amdgpu_cs_epilog_dws(cs
);
1049 unsigned need_byte_size
= (dw
+ cs_epilog_dw
) * 4;
1051 uint32_t *new_ptr_ib_size
;
1053 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1055 /* 125% of the size for IB epilog. */
1056 unsigned safe_byte_size
= need_byte_size
+ need_byte_size
/ 4;
1057 ib
->max_check_space_size
= MAX2(ib
->max_check_space_size
,
1060 /* If force_chaining is true, we can't return. We have to chain. */
1061 if (!force_chaining
) {
1062 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
1065 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
1067 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
1071 if (!amdgpu_cs_has_chaining(cs
)) {
1072 assert(!force_chaining
);
1076 /* Allocate a new chunk */
1077 if (rcs
->num_prev
>= rcs
->max_prev
) {
1078 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
1079 struct radeon_cmdbuf_chunk
*new_prev
;
1081 new_prev
= REALLOC(rcs
->prev
,
1082 sizeof(*new_prev
) * rcs
->max_prev
,
1083 sizeof(*new_prev
) * new_max_prev
);
1087 rcs
->prev
= new_prev
;
1088 rcs
->max_prev
= new_max_prev
;
1091 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1094 assert(ib
->used_ib_space
== 0);
1095 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1097 /* This space was originally reserved. */
1098 rcs
->current
.max_dw
+= cs_epilog_dw
;
1100 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1101 while ((rcs
->current
.cdw
& 7) != 4)
1102 radeon_emit(rcs
, PKT3_NOP_PAD
);
1104 radeon_emit(rcs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1105 radeon_emit(rcs
, va
);
1106 radeon_emit(rcs
, va
>> 32);
1107 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1109 assert((rcs
->current
.cdw
& 7) == 0);
1110 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1112 amdgpu_set_ib_size(ib
);
1113 ib
->ptr_ib_size
= new_ptr_ib_size
;
1114 ib
->ptr_ib_size_inside_ib
= true;
1116 /* Hook up the new chunk */
1117 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1118 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1119 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1122 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1123 ib
->base
.current
.cdw
= 0;
1125 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1126 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - cs_epilog_dw
;
1127 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
1128 ib
->base
.gpu_address
= va
;
1130 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1131 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1136 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1137 struct radeon_bo_list_item
*list
)
1139 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1143 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1144 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1145 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1146 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1149 return cs
->num_real_buffers
;
1152 static void add_fence_to_list(struct amdgpu_fence_list
*fences
,
1153 struct amdgpu_fence
*fence
)
1155 unsigned idx
= fences
->num
++;
1157 if (idx
>= fences
->max
) {
1159 const unsigned increment
= 8;
1161 fences
->max
= idx
+ increment
;
1162 size
= fences
->max
* sizeof(fences
->list
[0]);
1163 fences
->list
= realloc(fences
->list
, size
);
1164 /* Clear the newly-allocated elements. */
1165 memset(fences
->list
+ idx
, 0,
1166 increment
* sizeof(fences
->list
[0]));
1168 amdgpu_fence_reference(&fences
->list
[idx
], (struct pipe_fence_handle
*)fence
);
1171 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1172 struct amdgpu_fence
*fence
)
1174 struct amdgpu_cs_context
*cs
= acs
->csc
;
1176 /* Detect no-op dependencies only when there is only 1 ring,
1177 * because IBs on one ring are always executed one at a time.
1179 * We always want no dependency between back-to-back gfx IBs, because
1180 * we need the parallelism between IBs for good performance.
1182 if ((acs
->ring_type
== RING_GFX
||
1183 acs
->ctx
->ws
->info
.num_rings
[acs
->ring_type
] == 1) &&
1184 !amdgpu_fence_is_syncobj(fence
) &&
1185 fence
->ctx
== acs
->ctx
&&
1186 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1187 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1188 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1191 return amdgpu_fence_wait((void *)fence
, 0, false);
1194 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1195 struct pipe_fence_handle
*pfence
,
1196 unsigned dependency_flags
)
1198 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1199 struct amdgpu_cs_context
*cs
= acs
->csc
;
1200 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1202 util_queue_fence_wait(&fence
->submitted
);
1204 if (dependency_flags
& RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
) {
1205 /* Syncobjs are not needed here. */
1206 assert(!amdgpu_fence_is_syncobj(fence
));
1208 if (acs
->ctx
->ws
->info
.has_scheduled_fence_dependency
&&
1209 dependency_flags
& RADEON_DEPENDENCY_START_FENCE
)
1210 add_fence_to_list(&cs
->compute_start_fence_dependencies
, fence
);
1212 add_fence_to_list(&cs
->compute_fence_dependencies
, fence
);
1216 /* Start fences are not needed here. */
1217 assert(!(dependency_flags
& RADEON_DEPENDENCY_START_FENCE
));
1219 if (is_noop_fence_dependency(acs
, fence
))
1222 if (amdgpu_fence_is_syncobj(fence
))
1223 add_fence_to_list(&cs
->syncobj_dependencies
, fence
);
1225 add_fence_to_list(&cs
->fence_dependencies
, fence
);
1228 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1229 struct amdgpu_cs_buffer
*buffer
)
1231 struct amdgpu_cs_context
*cs
= acs
->csc
;
1232 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1233 unsigned new_num_fences
= 0;
1235 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1236 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1238 if (is_noop_fence_dependency(acs
, bo_fence
))
1241 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1244 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1247 add_fence_to_list(&cs
->fence_dependencies
, bo_fence
);
1250 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1251 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1253 bo
->num_fences
= new_num_fences
;
1256 /* Add the given list of fences to the buffer's fence list.
1258 * Must be called with the winsys bo_fence_lock held.
1260 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1261 unsigned num_fences
,
1262 struct pipe_fence_handle
**fences
)
1264 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1265 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1266 struct pipe_fence_handle
**new_fences
=
1268 bo
->num_fences
* sizeof(*new_fences
),
1269 new_max_fences
* sizeof(*new_fences
));
1270 if (likely(new_fences
)) {
1271 bo
->fences
= new_fences
;
1272 bo
->max_fences
= new_max_fences
;
1276 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1277 if (!bo
->num_fences
)
1280 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1281 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1283 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1289 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1290 bo
->fences
[bo
->num_fences
] = NULL
;
1291 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1296 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1297 struct pipe_fence_handle
*fence
,
1298 unsigned num_buffers
,
1299 struct amdgpu_cs_buffer
*buffers
)
1301 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1302 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1303 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1305 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1306 p_atomic_inc(&bo
->num_active_ioctls
);
1307 amdgpu_add_fences(bo
, 1, &fence
);
1311 /* Since the kernel driver doesn't synchronize execution between different
1312 * rings automatically, we have to add fence dependencies manually.
1314 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1316 struct amdgpu_cs_context
*cs
= acs
->csc
;
1318 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1319 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1320 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1323 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1324 struct pipe_fence_handle
*fence
)
1326 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1327 struct amdgpu_cs_context
*cs
= acs
->csc
;
1329 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1331 add_fence_to_list(&cs
->syncobj_to_signal
, (struct amdgpu_fence
*)fence
);
1334 /* Add backing of sparse buffers to the buffer list.
1336 * This is done late, during submission, to keep the buffer list short before
1337 * submit, and to avoid managing fences for the backing buffers.
1339 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1341 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1342 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1343 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1345 simple_mtx_lock(&bo
->lock
);
1347 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1348 /* We can directly add the buffer here, because we know that each
1349 * backing buffer occurs only once.
1351 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1353 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1354 simple_mtx_unlock(&bo
->lock
);
1358 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1359 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1360 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1363 simple_mtx_unlock(&bo
->lock
);
1369 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1371 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1372 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1373 struct amdgpu_cs_context
*cs
= acs
->cst
;
1375 uint32_t bo_list
= 0;
1376 uint64_t seq_no
= 0;
1377 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1378 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1379 struct drm_amdgpu_bo_list_in bo_list_in
;
1381 /* Prepare the buffer list. */
1382 if (ws
->debug_all_bos
) {
1383 /* The buffer list contains all buffers. This is a slow path that
1384 * ensures that no buffer is missing in the BO list.
1386 unsigned num_handles
= 0;
1387 struct drm_amdgpu_bo_list_entry
*list
=
1388 alloca(ws
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1389 struct amdgpu_winsys_bo
*bo
;
1391 simple_mtx_lock(&ws
->global_bo_list_lock
);
1392 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1393 list
[num_handles
].bo_handle
= bo
->u
.real
.kms_handle
;
1394 list
[num_handles
].bo_priority
= 0;
1398 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
, list
, &bo_list
);
1399 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1401 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1405 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1406 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1411 struct drm_amdgpu_bo_list_entry
*list
=
1412 alloca((cs
->num_real_buffers
+ 2) * sizeof(struct drm_amdgpu_bo_list_entry
));
1414 unsigned num_handles
= 0;
1415 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1416 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1417 assert(buffer
->u
.real
.priority_usage
!= 0);
1419 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1420 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1424 if (use_bo_list_create
) {
1425 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1426 r
= amdgpu_bo_list_create_raw(ws
->dev
, num_handles
, list
, &bo_list
);
1428 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1432 /* Standard path passing the buffer list via the CS ioctl. */
1433 bo_list_in
.operation
= ~0;
1434 bo_list_in
.list_handle
= ~0;
1435 bo_list_in
.bo_number
= num_handles
;
1436 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1437 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1441 if (acs
->ring_type
== RING_GFX
)
1442 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1444 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1447 struct drm_amdgpu_cs_chunk chunks
[6];
1448 unsigned num_chunks
= 0;
1451 if (!use_bo_list_create
) {
1452 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1453 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1454 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1458 /* Fence dependencies. */
1459 unsigned num_dependencies
= cs
->fence_dependencies
.num
;
1460 if (num_dependencies
) {
1461 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1462 alloca(num_dependencies
* sizeof(*dep_chunk
));
1464 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1465 struct amdgpu_fence
*fence
=
1466 (struct amdgpu_fence
*)cs
->fence_dependencies
.list
[i
];
1468 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1469 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1472 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1473 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1474 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1478 /* Syncobj dependencies. */
1479 unsigned num_syncobj_dependencies
= cs
->syncobj_dependencies
.num
;
1480 if (num_syncobj_dependencies
) {
1481 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1482 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1484 for (unsigned i
= 0; i
< num_syncobj_dependencies
; i
++) {
1485 struct amdgpu_fence
*fence
=
1486 (struct amdgpu_fence
*)cs
->syncobj_dependencies
.list
[i
];
1488 if (!amdgpu_fence_is_syncobj(fence
))
1491 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1492 sem_chunk
[i
].handle
= fence
->syncobj
;
1495 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1496 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num_syncobj_dependencies
;
1497 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1501 /* Submit the parallel compute IB first. */
1502 if (cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
> 0) {
1503 unsigned old_num_chunks
= num_chunks
;
1505 /* Add compute fence dependencies. */
1506 unsigned num_dependencies
= cs
->compute_fence_dependencies
.num
;
1507 if (num_dependencies
) {
1508 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1509 alloca(num_dependencies
* sizeof(*dep_chunk
));
1511 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1512 struct amdgpu_fence
*fence
=
1513 (struct amdgpu_fence
*)cs
->compute_fence_dependencies
.list
[i
];
1515 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1516 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1519 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1520 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1521 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1525 /* Add compute start fence dependencies. */
1526 unsigned num_start_dependencies
= cs
->compute_start_fence_dependencies
.num
;
1527 if (num_start_dependencies
) {
1528 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1529 alloca(num_start_dependencies
* sizeof(*dep_chunk
));
1531 for (unsigned i
= 0; i
< num_start_dependencies
; i
++) {
1532 struct amdgpu_fence
*fence
=
1533 (struct amdgpu_fence
*)cs
->compute_start_fence_dependencies
.list
[i
];
1535 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1536 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1539 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
;
1540 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_start_dependencies
;
1541 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1545 /* Convert from dwords to bytes. */
1546 cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
*= 4;
1547 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1548 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1549 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_PARALLEL_COMPUTE
];
1552 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1553 num_chunks
, chunks
, NULL
);
1557 /* Back off the compute chunks. */
1558 num_chunks
= old_num_chunks
;
1561 /* Syncobj signals. */
1562 unsigned num_syncobj_to_signal
= cs
->syncobj_to_signal
.num
;
1563 if (num_syncobj_to_signal
) {
1564 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1565 alloca(num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1567 for (unsigned i
= 0; i
< num_syncobj_to_signal
; i
++) {
1568 struct amdgpu_fence
*fence
=
1569 (struct amdgpu_fence
*)cs
->syncobj_to_signal
.list
[i
];
1571 assert(amdgpu_fence_is_syncobj(fence
));
1572 sem_chunk
[i
].handle
= fence
->syncobj
;
1575 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1576 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1577 * num_syncobj_to_signal
;
1578 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1583 if (has_user_fence
) {
1584 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1585 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1586 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1591 cs
->ib
[IB_MAIN
].ib_bytes
*= 4; /* Convert from dwords to bytes. */
1592 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1593 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1594 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1597 if (ws
->secure
&& cs
->secure
)
1598 cs
->ib
[IB_MAIN
].flags
|= AMDGPU_IB_FLAGS_SECURE
;
1600 cs
->ib
[IB_MAIN
].flags
&= ~AMDGPU_IB_FLAGS_SECURE
;
1602 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1604 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1605 num_chunks
, chunks
, &seq_no
);
1611 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1612 else if (r
== -ECANCELED
)
1613 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1615 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1616 "see dmesg for more information (%i).\n", r
);
1618 acs
->ctx
->num_rejected_cs
++;
1619 ws
->num_total_rejected_cs
++;
1622 uint64_t *user_fence
= NULL
;
1625 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1626 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1631 amdgpu_bo_list_destroy_raw(ws
->dev
, bo_list
);
1634 /* If there was an error, signal the fence, because it won't be signalled
1635 * by the hardware. */
1637 amdgpu_fence_signalled(cs
->fence
);
1641 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1642 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1643 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1644 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1645 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1646 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1648 amdgpu_cs_context_cleanup(cs
);
1651 /* Make sure the previous submission is completed. */
1652 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1654 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1656 /* Wait for any pending ioctl of this CS to complete. */
1657 util_queue_fence_wait(&cs
->flush_completed
);
1660 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1662 struct pipe_fence_handle
**fence
)
1664 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1665 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1668 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
);
1670 switch (cs
->ring_type
) {
1672 /* pad DMA ring to 8 DWs */
1673 if (ws
->info
.chip_class
<= GFX6
) {
1674 while (rcs
->current
.cdw
& 7)
1675 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1680 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1681 if (ws
->info
.gfx_ib_pad_with_type2
) {
1682 while (rcs
->current
.cdw
& 7)
1683 radeon_emit(rcs
, PKT2_NOP_PAD
);
1685 while (rcs
->current
.cdw
& 7)
1686 radeon_emit(rcs
, PKT3_NOP_PAD
);
1688 if (cs
->ring_type
== RING_GFX
)
1689 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1691 /* Also pad secondary IBs. */
1692 if (cs
->compute_ib
.ib_mapped
) {
1693 while (cs
->compute_ib
.base
.current
.cdw
& 7)
1694 radeon_emit(&cs
->compute_ib
.base
, PKT3_NOP_PAD
);
1699 while (rcs
->current
.cdw
& 15)
1700 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1703 if (rcs
->current
.cdw
% 2)
1705 while (rcs
->current
.cdw
& 15) {
1706 radeon_emit(rcs
, 0x60000000); /* nop packet */
1707 radeon_emit(rcs
, 0x00000000);
1711 while (rcs
->current
.cdw
& 15)
1712 radeon_emit(rcs
, 0x81ff); /* nop packet */
1718 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1719 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1722 /* If the CS is not empty or overflowed.... */
1723 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1724 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1725 !debug_get_option_noop())) {
1726 struct amdgpu_cs_context
*cur
= cs
->csc
;
1729 amdgpu_ib_finalize(ws
, &cs
->main
);
1731 if (cs
->compute_ib
.ib_mapped
)
1732 amdgpu_ib_finalize(ws
, &cs
->compute_ib
);
1734 /* Create a fence. */
1735 amdgpu_fence_reference(&cur
->fence
, NULL
);
1736 if (cs
->next_fence
) {
1737 /* just move the reference */
1738 cur
->fence
= cs
->next_fence
;
1739 cs
->next_fence
= NULL
;
1741 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1742 cur
->ib
[IB_MAIN
].ip_type
,
1743 cur
->ib
[IB_MAIN
].ip_instance
,
1744 cur
->ib
[IB_MAIN
].ring
);
1747 amdgpu_fence_reference(fence
, cur
->fence
);
1749 amdgpu_cs_sync_flush(rcs
);
1753 * This fence must be held until the submission is queued to ensure
1754 * that the order of fence dependency updates matches the order of
1757 simple_mtx_lock(&ws
->bo_fence_lock
);
1758 amdgpu_add_fence_dependencies_bo_lists(cs
);
1760 /* Swap command streams. "cst" is going to be submitted. */
1765 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1766 amdgpu_cs_submit_ib
, NULL
, 0);
1767 /* The submission has been queued, unlock the fence now. */
1768 simple_mtx_unlock(&ws
->bo_fence_lock
);
1770 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1771 amdgpu_cs_sync_flush(rcs
);
1772 error_code
= cur
->error_code
;
1775 amdgpu_cs_context_cleanup(cs
->csc
);
1778 amdgpu_get_new_ib(ws
, cs
, IB_MAIN
);
1779 if (cs
->compute_ib
.ib_mapped
)
1780 amdgpu_get_new_ib(ws
, cs
, IB_PARALLEL_COMPUTE
);
1782 cs
->main
.base
.used_gart
= 0;
1783 cs
->main
.base
.used_vram
= 0;
1785 if (cs
->ring_type
== RING_GFX
)
1787 else if (cs
->ring_type
== RING_DMA
)
1793 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1795 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1797 amdgpu_cs_sync_flush(rcs
);
1798 util_queue_fence_destroy(&cs
->flush_completed
);
1799 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1800 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1801 FREE(cs
->main
.base
.prev
);
1802 pb_reference(&cs
->compute_ib
.big_ib_buffer
, NULL
);
1803 FREE(cs
->compute_ib
.base
.prev
);
1804 amdgpu_destroy_cs_context(&cs
->csc1
);
1805 amdgpu_destroy_cs_context(&cs
->csc2
);
1806 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1810 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1811 struct pb_buffer
*_buf
,
1812 enum radeon_bo_usage usage
)
1814 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1815 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1817 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1820 void amdgpu_cs_init_functions(struct amdgpu_screen_winsys
*ws
)
1822 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1823 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1824 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1825 ws
->base
.cs_create
= amdgpu_cs_create
;
1826 ws
->base
.cs_add_parallel_compute_ib
= amdgpu_cs_add_parallel_compute_ib
;
1827 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1828 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1829 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1830 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1831 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1832 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1833 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1834 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1835 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1836 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1837 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1838 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1839 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1840 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1841 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1842 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1843 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;