2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "amd/common/sid.h"
42 static struct pipe_fence_handle
*
43 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
44 unsigned ip_instance
, unsigned ring
)
46 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
48 fence
->reference
.count
= 1;
50 fence
->fence
.context
= ctx
->ctx
;
51 fence
->fence
.ip_type
= ip_type
;
52 fence
->fence
.ip_instance
= ip_instance
;
53 fence
->fence
.ring
= ring
;
54 fence
->submission_in_progress
= true;
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
60 struct amdgpu_cs_request
* request
,
61 uint64_t *user_fence_cpu_address
)
63 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
65 rfence
->fence
.fence
= request
->seq_no
;
66 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
67 rfence
->submission_in_progress
= false;
70 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
72 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
74 rfence
->signalled
= true;
75 rfence
->submission_in_progress
= false;
78 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
81 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
84 uint64_t *user_fence_cpu
;
87 if (rfence
->signalled
)
91 abs_timeout
= timeout
;
93 abs_timeout
= os_time_get_absolute_timeout(timeout
);
95 /* The fence might not have a number assigned if its IB is being
96 * submitted in the other thread right now. Wait until the submission
98 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
102 user_fence_cpu
= rfence
->user_fence_cpu_address
;
103 if (user_fence_cpu
) {
104 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
105 rfence
->signalled
= true;
109 /* No timeout, just query: no need for the ioctl. */
110 if (!absolute
&& !timeout
)
114 /* Now use the libdrm query. */
115 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
117 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
120 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
125 /* This variable can only transition from false to true, so it doesn't
126 * matter if threads race for it. */
127 rfence
->signalled
= true;
133 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
134 struct pipe_fence_handle
*fence
,
137 return amdgpu_fence_wait(fence
, timeout
, false);
140 static struct pipe_fence_handle
*
141 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
143 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
144 struct pipe_fence_handle
*fence
= NULL
;
146 if (cs
->next_fence
) {
147 amdgpu_fence_reference(&fence
, cs
->next_fence
);
151 fence
= amdgpu_fence_create(cs
->ctx
,
152 cs
->csc
->request
.ip_type
,
153 cs
->csc
->request
.ip_instance
,
154 cs
->csc
->request
.ring
);
158 amdgpu_fence_reference(&cs
->next_fence
, fence
);
164 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
166 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
168 struct amdgpu_bo_alloc_request alloc_buffer
= {};
169 amdgpu_bo_handle buf_handle
;
174 ctx
->ws
= amdgpu_winsys(ws
);
177 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
179 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
183 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
184 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
185 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
187 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
189 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
190 goto error_user_fence_alloc
;
193 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
195 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
196 goto error_user_fence_map
;
199 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
200 ctx
->user_fence_bo
= buf_handle
;
202 return (struct radeon_winsys_ctx
*)ctx
;
204 error_user_fence_map
:
205 amdgpu_bo_free(buf_handle
);
206 error_user_fence_alloc
:
207 amdgpu_cs_ctx_free(ctx
->ctx
);
213 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
215 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
218 static enum pipe_reset_status
219 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
221 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
222 uint32_t result
, hangs
;
225 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
227 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
228 return PIPE_NO_RESET
;
232 case AMDGPU_CTX_GUILTY_RESET
:
233 return PIPE_GUILTY_CONTEXT_RESET
;
234 case AMDGPU_CTX_INNOCENT_RESET
:
235 return PIPE_INNOCENT_CONTEXT_RESET
;
236 case AMDGPU_CTX_UNKNOWN_RESET
:
237 return PIPE_UNKNOWN_CONTEXT_RESET
;
238 case AMDGPU_CTX_NO_RESET
:
240 return PIPE_NO_RESET
;
244 /* COMMAND SUBMISSION */
246 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
248 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
249 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
252 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
254 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
255 cs
->ring_type
== RING_GFX
;
258 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
260 if (ring_type
== RING_GFX
)
261 return 4; /* for chaining */
266 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
268 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
269 int i
= cs
->buffer_indices_hashlist
[hash
];
270 struct amdgpu_cs_buffer
*buffers
;
274 buffers
= cs
->real_buffers
;
275 num_buffers
= cs
->num_real_buffers
;
277 buffers
= cs
->slab_buffers
;
278 num_buffers
= cs
->num_slab_buffers
;
281 /* not found or found */
282 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
285 /* Hash collision, look for the BO in the list of buffers linearly. */
286 for (i
= num_buffers
- 1; i
>= 0; i
--) {
287 if (buffers
[i
].bo
== bo
) {
288 /* Put this buffer in the hash list.
289 * This will prevent additional hash collisions if there are
290 * several consecutive lookup_buffer calls for the same buffer.
292 * Example: Assuming buffers A,B,C collide in the hash list,
293 * the following sequence of buffers:
294 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
295 * will collide here: ^ and here: ^,
296 * meaning that we should get very few collisions in the end. */
297 cs
->buffer_indices_hashlist
[hash
] = i
;
305 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
307 struct amdgpu_cs_context
*cs
= acs
->csc
;
308 struct amdgpu_cs_buffer
*buffer
;
310 int idx
= amdgpu_lookup_buffer(cs
, bo
);
315 /* New buffer, check if the backing array is large enough. */
316 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
318 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
319 struct amdgpu_cs_buffer
*new_buffers
;
320 amdgpu_bo_handle
*new_handles
;
323 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
324 new_handles
= MALLOC(new_max
* sizeof(*new_handles
));
325 new_flags
= MALLOC(new_max
* sizeof(*new_flags
));
327 if (!new_buffers
|| !new_handles
|| !new_flags
) {
328 fprintf(stderr
, "amdgpu_lookup_or_add_buffer: allocation failed\n");
335 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
336 memcpy(new_handles
, cs
->handles
, cs
->num_real_buffers
* sizeof(*new_handles
));
337 memcpy(new_flags
, cs
->flags
, cs
->num_real_buffers
* sizeof(*new_flags
));
339 FREE(cs
->real_buffers
);
343 cs
->max_real_buffers
= new_max
;
344 cs
->real_buffers
= new_buffers
;
345 cs
->handles
= new_handles
;
346 cs
->flags
= new_flags
;
349 idx
= cs
->num_real_buffers
;
350 buffer
= &cs
->real_buffers
[idx
];
352 memset(buffer
, 0, sizeof(*buffer
));
353 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
354 cs
->handles
[idx
] = bo
->bo
;
356 p_atomic_inc(&bo
->num_cs_references
);
357 cs
->num_real_buffers
++;
359 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
360 cs
->buffer_indices_hashlist
[hash
] = idx
;
362 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
363 acs
->main
.base
.used_vram
+= bo
->base
.size
;
364 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
365 acs
->main
.base
.used_gart
+= bo
->base
.size
;
370 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
371 struct amdgpu_winsys_bo
*bo
)
373 struct amdgpu_cs_context
*cs
= acs
->csc
;
374 struct amdgpu_cs_buffer
*buffer
;
376 int idx
= amdgpu_lookup_buffer(cs
, bo
);
382 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
386 /* New buffer, check if the backing array is large enough. */
387 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
389 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
390 struct amdgpu_cs_buffer
*new_buffers
;
392 new_buffers
= REALLOC(cs
->slab_buffers
,
393 cs
->max_slab_buffers
* sizeof(*new_buffers
),
394 new_max
* sizeof(*new_buffers
));
396 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
400 cs
->max_slab_buffers
= new_max
;
401 cs
->slab_buffers
= new_buffers
;
404 idx
= cs
->num_slab_buffers
;
405 buffer
= &cs
->slab_buffers
[idx
];
407 memset(buffer
, 0, sizeof(*buffer
));
408 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
409 buffer
->u
.slab
.real_idx
= real_idx
;
410 p_atomic_inc(&bo
->num_cs_references
);
411 cs
->num_slab_buffers
++;
413 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
414 cs
->buffer_indices_hashlist
[hash
] = idx
;
419 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
420 struct pb_buffer
*buf
,
421 enum radeon_bo_usage usage
,
422 enum radeon_bo_domain domains
,
423 enum radeon_bo_priority priority
)
425 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
426 * the buffer placement during command submission.
428 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
429 struct amdgpu_cs_context
*cs
= acs
->csc
;
430 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
431 struct amdgpu_cs_buffer
*buffer
;
435 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
439 buffer
= &cs
->slab_buffers
[index
];
440 buffer
->usage
|= usage
;
442 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
443 index
= buffer
->u
.slab
.real_idx
;
445 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
450 buffer
= &cs
->real_buffers
[index
];
451 buffer
->u
.real
.priority_usage
|= 1llu << priority
;
452 buffer
->usage
|= usage
;
453 cs
->flags
[index
] = MAX2(cs
->flags
[index
], priority
/ 4);
457 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
459 struct pb_buffer
*pb
;
461 unsigned buffer_size
;
463 /* Always create a buffer that is at least as large as the maximum seen IB
464 * size, aligned to a power of two (and multiplied by 4 to reduce internal
465 * fragmentation if chaining is not available). Limit to 512k dwords, which
466 * is the largest power of two that fits into the size field of the
467 * INDIRECT_BUFFER packet.
469 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
470 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
472 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
474 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
476 switch (ib
->ib_type
) {
477 case IB_CONST_PREAMBLE
:
478 buffer_size
= MAX2(buffer_size
, 4 * 1024);
481 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
484 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
487 unreachable("unhandled IB type");
490 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
491 ws
->info
.gart_page_size
,
493 RADEON_FLAG_CPU_ACCESS
);
497 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
499 pb_reference(&pb
, NULL
);
503 pb_reference(&ib
->big_ib_buffer
, pb
);
504 pb_reference(&pb
, NULL
);
506 ib
->ib_mapped
= mapped
;
507 ib
->used_ib_space
= 0;
512 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
516 /* Smaller submits means the GPU gets busy sooner and there is less
517 * waiting for buffers and fences. Proof:
518 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
521 case IB_CONST_PREAMBLE
:
523 /* There isn't really any reason to limit CE IB size beyond the natural
524 * limit implied by the main IB, except perhaps GTT size. Just return
525 * an extremely large value that we never get anywhere close to.
527 return 16 * 1024 * 1024;
529 unreachable("bad ib_type");
533 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
534 enum ib_type ib_type
)
536 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
537 /* Small IBs are better than big IBs, because the GPU goes idle quicker
538 * and there is less waiting for buffers and fences. Proof:
539 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
541 struct amdgpu_ib
*ib
= NULL
;
542 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
543 unsigned ib_size
= 0;
546 case IB_CONST_PREAMBLE
:
547 ib
= &cs
->const_preamble_ib
;
552 ib_size
= 8 * 1024 * 4;
556 ib_size
= 4 * 1024 * 4;
559 unreachable("unhandled IB type");
562 if (!amdgpu_cs_has_chaining(cs
)) {
563 ib_size
= MAX2(ib_size
,
564 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
565 amdgpu_ib_max_submit_dwords(ib_type
)));
568 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
570 ib
->base
.prev_dw
= 0;
571 ib
->base
.num_prev
= 0;
572 ib
->base
.current
.cdw
= 0;
573 ib
->base
.current
.buf
= NULL
;
575 /* Allocate a new buffer for IBs if the current buffer is all used. */
576 if (!ib
->big_ib_buffer
||
577 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
578 if (!amdgpu_ib_new_buffer(aws
, ib
))
582 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
585 ib
->ptr_ib_size
= &info
->size
;
587 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
588 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
590 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
592 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
593 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
597 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
599 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
600 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
601 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
604 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
605 enum ring_type ring_type
)
611 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
615 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
619 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
623 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
628 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
632 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
633 cs
->buffer_indices_hashlist
[i
] = -1;
636 cs
->request
.number_of_ibs
= 1;
637 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
639 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
640 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
641 AMDGPU_IB_FLAG_PREAMBLE
;
646 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
650 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
651 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
652 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
654 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
655 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
656 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
659 cs
->num_real_buffers
= 0;
660 cs
->num_slab_buffers
= 0;
661 amdgpu_fence_reference(&cs
->fence
, NULL
);
663 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
664 cs
->buffer_indices_hashlist
[i
] = -1;
668 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
670 amdgpu_cs_context_cleanup(cs
);
672 FREE(cs
->real_buffers
);
674 FREE(cs
->slab_buffers
);
675 FREE(cs
->request
.dependencies
);
679 static struct radeon_winsys_cs
*
680 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
681 enum ring_type ring_type
,
682 void (*flush
)(void *ctx
, unsigned flags
,
683 struct pipe_fence_handle
**fence
),
686 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
687 struct amdgpu_cs
*cs
;
689 cs
= CALLOC_STRUCT(amdgpu_cs
);
694 util_queue_fence_init(&cs
->flush_completed
);
697 cs
->flush_cs
= flush
;
698 cs
->flush_data
= flush_ctx
;
699 cs
->ring_type
= ring_type
;
701 cs
->main
.ib_type
= IB_MAIN
;
702 cs
->const_ib
.ib_type
= IB_CONST
;
703 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
705 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
710 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
711 amdgpu_destroy_cs_context(&cs
->csc1
);
716 /* Set the first submission context as current. */
720 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
721 amdgpu_destroy_cs_context(&cs
->csc2
);
722 amdgpu_destroy_cs_context(&cs
->csc1
);
727 p_atomic_inc(&ctx
->ws
->num_cs
);
728 return &cs
->main
.base
;
731 static struct radeon_winsys_cs
*
732 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
734 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
735 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
737 /* only one const IB can be added */
738 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
741 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
744 cs
->csc
->request
.number_of_ibs
= 2;
745 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
747 cs
->cst
->request
.number_of_ibs
= 2;
748 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
750 return &cs
->const_ib
.base
;
753 static struct radeon_winsys_cs
*
754 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
756 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
757 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
759 /* only one const preamble IB can be added and only when the const IB has
760 * also been mapped */
761 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
762 cs
->const_preamble_ib
.ib_mapped
)
765 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
768 cs
->csc
->request
.number_of_ibs
= 3;
769 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
771 cs
->cst
->request
.number_of_ibs
= 3;
772 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
774 return &cs
->const_preamble_ib
.base
;
777 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
782 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
784 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
785 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
786 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
788 uint32_t *new_ptr_ib_size
;
790 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
792 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
795 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
797 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
800 if (!amdgpu_cs_has_chaining(cs
))
803 /* Allocate a new chunk */
804 if (rcs
->num_prev
>= rcs
->max_prev
) {
805 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
806 struct radeon_winsys_cs_chunk
*new_prev
;
808 new_prev
= REALLOC(rcs
->prev
,
809 sizeof(*new_prev
) * rcs
->max_prev
,
810 sizeof(*new_prev
) * new_max_prev
);
814 rcs
->prev
= new_prev
;
815 rcs
->max_prev
= new_max_prev
;
818 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
821 assert(ib
->used_ib_space
== 0);
822 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
824 /* This space was originally reserved. */
825 rcs
->current
.max_dw
+= 4;
826 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
828 /* Pad with NOPs and add INDIRECT_BUFFER packet */
829 while ((rcs
->current
.cdw
& 7) != 4)
830 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
832 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
833 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
834 radeon_emit(rcs
, va
);
835 radeon_emit(rcs
, va
>> 32);
836 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
837 radeon_emit(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
839 assert((rcs
->current
.cdw
& 7) == 0);
840 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
842 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
843 ib
->ptr_ib_size
= new_ptr_ib_size
;
845 /* Hook up the new chunk */
846 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
847 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
848 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
851 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
852 ib
->base
.current
.cdw
= 0;
854 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
855 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
857 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
858 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
863 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
864 struct radeon_bo_list_item
*list
)
866 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
870 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
871 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
872 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
873 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
876 return cs
->num_real_buffers
;
879 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
881 static void amdgpu_add_fence_dependency(struct amdgpu_cs
*acs
,
882 struct amdgpu_cs_buffer
*buffer
)
884 struct amdgpu_cs_context
*cs
= acs
->csc
;
885 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
886 struct amdgpu_cs_fence
*dep
;
887 unsigned new_num_fences
= 0;
889 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
890 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
893 if (bo_fence
->ctx
== acs
->ctx
&&
894 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
895 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
896 bo_fence
->fence
.ring
== cs
->request
.ring
)
899 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
902 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
905 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
908 if (bo_fence
->submission_in_progress
)
909 os_wait_until_zero(&bo_fence
->submission_in_progress
,
910 PIPE_TIMEOUT_INFINITE
);
912 idx
= cs
->request
.number_of_dependencies
++;
913 if (idx
>= cs
->max_dependencies
) {
916 cs
->max_dependencies
= idx
+ 8;
917 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
918 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
921 dep
= &cs
->request
.dependencies
[idx
];
922 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
925 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
926 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
928 bo
->num_fences
= new_num_fences
;
931 /* Since the kernel driver doesn't synchronize execution between different
932 * rings automatically, we have to add fence dependencies manually.
934 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
936 struct amdgpu_cs_context
*cs
= acs
->csc
;
939 cs
->request
.number_of_dependencies
= 0;
941 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
942 amdgpu_add_fence_dependency(acs
, &cs
->real_buffers
[i
]);
943 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
944 amdgpu_add_fence_dependency(acs
, &cs
->slab_buffers
[i
]);
947 static void amdgpu_add_fence(struct amdgpu_winsys_bo
*bo
,
948 struct pipe_fence_handle
*fence
)
950 if (bo
->num_fences
>= bo
->max_fences
) {
951 unsigned new_max_fences
= MAX2(1, bo
->max_fences
* 2);
952 struct pipe_fence_handle
**new_fences
=
954 bo
->num_fences
* sizeof(*new_fences
),
955 new_max_fences
* sizeof(*new_fences
));
957 bo
->fences
= new_fences
;
958 bo
->max_fences
= new_max_fences
;
960 fprintf(stderr
, "amdgpu_add_fence: allocation failure, dropping fence\n");
964 bo
->num_fences
--; /* prefer to keep a more recent fence if possible */
965 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
969 bo
->fences
[bo
->num_fences
] = NULL
;
970 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fence
);
974 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
976 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
977 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
978 struct amdgpu_cs_context
*cs
= acs
->cst
;
981 cs
->request
.fence_info
.handle
= NULL
;
982 if (amdgpu_cs_has_user_fence(cs
)) {
983 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
984 cs
->request
.fence_info
.offset
= acs
->ring_type
;
987 /* Create the buffer list.
988 * Use a buffer list containing all allocated buffers if requested.
990 if (debug_get_option_all_bos()) {
991 struct amdgpu_winsys_bo
*bo
;
992 amdgpu_bo_handle
*handles
;
995 pipe_mutex_lock(ws
->global_bo_list_lock
);
997 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
999 pipe_mutex_unlock(ws
->global_bo_list_lock
);
1000 amdgpu_cs_context_cleanup(cs
);
1001 cs
->error_code
= -ENOMEM
;
1005 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1006 assert(num
< ws
->num_buffers
);
1007 handles
[num
++] = bo
->bo
;
1010 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1012 &cs
->request
.resources
);
1014 pipe_mutex_unlock(ws
->global_bo_list_lock
);
1016 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_real_buffers
,
1017 cs
->handles
, cs
->flags
,
1018 &cs
->request
.resources
);
1022 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1023 cs
->request
.resources
= NULL
;
1024 amdgpu_fence_signalled(cs
->fence
);
1029 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
1033 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1035 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1036 "see dmesg for more information (%i).\n", r
);
1038 amdgpu_fence_signalled(cs
->fence
);
1041 uint64_t *user_fence
= NULL
;
1042 if (amdgpu_cs_has_user_fence(cs
))
1043 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
1044 cs
->request
.fence_info
.offset
;
1045 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
1049 if (cs
->request
.resources
)
1050 amdgpu_bo_list_destroy(cs
->request
.resources
);
1053 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1054 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1055 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1056 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1058 amdgpu_cs_context_cleanup(cs
);
1061 /* Make sure the previous submission is completed. */
1062 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1064 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1065 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1067 /* Wait for any pending ioctl of this CS to complete. */
1068 if (util_queue_is_initialized(&ws
->cs_queue
))
1069 util_queue_job_wait(&cs
->flush_completed
);
1072 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
1074 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1076 struct pipe_fence_handle
**fence
)
1078 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1079 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1082 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1084 switch (cs
->ring_type
) {
1086 /* pad DMA ring to 8 DWs */
1087 if (ws
->info
.chip_class
<= SI
) {
1088 while (rcs
->current
.cdw
& 7)
1089 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1091 while (rcs
->current
.cdw
& 7)
1092 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1096 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1097 if (ws
->info
.gfx_ib_pad_with_type2
) {
1098 while (rcs
->current
.cdw
& 7)
1099 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1101 while (rcs
->current
.cdw
& 7)
1102 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1105 /* Also pad the const IB. */
1106 if (cs
->const_ib
.ib_mapped
)
1107 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
1108 radeon_emit(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1110 if (cs
->const_preamble_ib
.ib_mapped
)
1111 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1112 radeon_emit(&cs
->const_preamble_ib
.base
, 0xffff1000);
1115 while (rcs
->current
.cdw
& 15)
1116 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1122 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1123 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1126 /* If the CS is not empty or overflowed.... */
1127 if (radeon_emitted(&cs
->main
.base
, 0) &&
1128 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1129 !debug_get_option_noop()) {
1130 struct amdgpu_cs_context
*cur
= cs
->csc
;
1131 unsigned i
, num_buffers
;
1134 amdgpu_ib_finalize(&cs
->main
);
1136 if (cs
->const_ib
.ib_mapped
)
1137 amdgpu_ib_finalize(&cs
->const_ib
);
1139 if (cs
->const_preamble_ib
.ib_mapped
)
1140 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1142 /* Create a fence. */
1143 amdgpu_fence_reference(&cur
->fence
, NULL
);
1144 if (cs
->next_fence
) {
1145 /* just move the reference */
1146 cur
->fence
= cs
->next_fence
;
1147 cs
->next_fence
= NULL
;
1149 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1150 cur
->request
.ip_type
,
1151 cur
->request
.ip_instance
,
1155 amdgpu_fence_reference(fence
, cur
->fence
);
1157 /* Prepare buffers. */
1158 pipe_mutex_lock(ws
->bo_fence_lock
);
1159 amdgpu_add_fence_dependencies(cs
);
1161 num_buffers
= cur
->num_real_buffers
;
1162 for (i
= 0; i
< num_buffers
; i
++) {
1163 struct amdgpu_winsys_bo
*bo
= cur
->real_buffers
[i
].bo
;
1164 p_atomic_inc(&bo
->num_active_ioctls
);
1165 amdgpu_add_fence(bo
, cur
->fence
);
1168 num_buffers
= cur
->num_slab_buffers
;
1169 for (i
= 0; i
< num_buffers
; i
++) {
1170 struct amdgpu_winsys_bo
*bo
= cur
->slab_buffers
[i
].bo
;
1171 p_atomic_inc(&bo
->num_active_ioctls
);
1172 amdgpu_add_fence(bo
, cur
->fence
);
1174 pipe_mutex_unlock(ws
->bo_fence_lock
);
1176 amdgpu_cs_sync_flush(rcs
);
1178 /* Swap command streams. "cst" is going to be submitted. */
1183 if ((flags
& RADEON_FLUSH_ASYNC
) &&
1184 util_queue_is_initialized(&ws
->cs_queue
)) {
1185 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1186 amdgpu_cs_submit_ib
, NULL
);
1188 amdgpu_cs_submit_ib(cs
, 0);
1189 error_code
= cs
->cst
->error_code
;
1192 amdgpu_cs_context_cleanup(cs
->csc
);
1195 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1196 if (cs
->const_ib
.ib_mapped
)
1197 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1198 if (cs
->const_preamble_ib
.ib_mapped
)
1199 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1201 cs
->main
.base
.used_gart
= 0;
1202 cs
->main
.base
.used_vram
= 0;
1204 ws
->num_cs_flushes
++;
1208 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1210 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1212 amdgpu_cs_sync_flush(rcs
);
1213 util_queue_fence_destroy(&cs
->flush_completed
);
1214 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1215 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1216 FREE(cs
->main
.base
.prev
);
1217 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1218 FREE(cs
->const_ib
.base
.prev
);
1219 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1220 FREE(cs
->const_preamble_ib
.base
.prev
);
1221 amdgpu_destroy_cs_context(&cs
->csc1
);
1222 amdgpu_destroy_cs_context(&cs
->csc2
);
1223 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1227 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1228 struct pb_buffer
*_buf
,
1229 enum radeon_bo_usage usage
)
1231 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1232 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1234 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1237 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1239 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1240 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1241 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1242 ws
->base
.cs_create
= amdgpu_cs_create
;
1243 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1244 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1245 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1246 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1247 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1248 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1249 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1250 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1251 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1252 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1253 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1254 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1255 ws
->base
.fence_reference
= amdgpu_fence_reference
;