2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 util_queue_fence_init(&fence
->submitted
);
54 util_queue_fence_reset(&fence
->submitted
);
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static struct pipe_fence_handle
*
60 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
62 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
63 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
69 pipe_reference_init(&fence
->reference
, 1);
72 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
78 util_queue_fence_init(&fence
->submitted
);
80 assert(amdgpu_fence_is_syncobj(fence
));
81 return (struct pipe_fence_handle
*)fence
;
84 static struct pipe_fence_handle
*
85 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
87 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
88 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
93 pipe_reference_init(&fence
->reference
, 1);
95 /* fence->ctx == NULL means that the fence is syncobj-based. */
97 /* Convert sync_file into syncobj. */
98 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
104 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
106 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
111 util_queue_fence_init(&fence
->submitted
);
113 return (struct pipe_fence_handle
*)fence
;
116 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
117 struct pipe_fence_handle
*pfence
)
119 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
120 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
122 if (amdgpu_fence_is_syncobj(fence
)) {
125 /* Convert syncobj into sync_file. */
126 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
130 util_queue_fence_wait(&fence
->submitted
);
132 /* Convert the amdgpu fence into a fence FD. */
134 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
135 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
142 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
144 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
148 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
154 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
159 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
163 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
165 uint64_t *user_fence_cpu_address
)
167 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
169 afence
->fence
.fence
= seq_no
;
170 afence
->user_fence_cpu_address
= user_fence_cpu_address
;
171 util_queue_fence_signal(&afence
->submitted
);
174 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
176 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
178 afence
->signalled
= true;
179 util_queue_fence_signal(&afence
->submitted
);
182 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
185 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
188 uint64_t *user_fence_cpu
;
191 if (afence
->signalled
)
195 abs_timeout
= timeout
;
197 abs_timeout
= os_time_get_absolute_timeout(timeout
);
199 /* Handle syncobjs. */
200 if (amdgpu_fence_is_syncobj(afence
)) {
201 if (amdgpu_cs_syncobj_wait(afence
->ws
->dev
, &afence
->syncobj
, 1,
202 abs_timeout
, 0, NULL
))
205 afence
->signalled
= true;
209 /* The fence might not have a number assigned if its IB is being
210 * submitted in the other thread right now. Wait until the submission
212 if (!util_queue_fence_wait_timeout(&afence
->submitted
, abs_timeout
))
215 user_fence_cpu
= afence
->user_fence_cpu_address
;
216 if (user_fence_cpu
) {
217 if (*user_fence_cpu
>= afence
->fence
.fence
) {
218 afence
->signalled
= true;
222 /* No timeout, just query: no need for the ioctl. */
223 if (!absolute
&& !timeout
)
227 /* Now use the libdrm query. */
228 r
= amdgpu_cs_query_fence_status(&afence
->fence
,
230 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
233 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
238 /* This variable can only transition from false to true, so it doesn't
239 * matter if threads race for it. */
240 afence
->signalled
= true;
246 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
247 struct pipe_fence_handle
*fence
,
250 return amdgpu_fence_wait(fence
, timeout
, false);
253 static struct pipe_fence_handle
*
254 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
256 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
257 struct pipe_fence_handle
*fence
= NULL
;
259 if (debug_get_option_noop())
262 if (cs
->next_fence
) {
263 amdgpu_fence_reference(&fence
, cs
->next_fence
);
267 fence
= amdgpu_fence_create(cs
->ctx
,
268 cs
->csc
->ib
[IB_MAIN
].ip_type
,
269 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
270 cs
->csc
->ib
[IB_MAIN
].ring
);
274 amdgpu_fence_reference(&cs
->next_fence
, fence
);
280 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
282 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
284 struct amdgpu_bo_alloc_request alloc_buffer
= {};
285 amdgpu_bo_handle buf_handle
;
290 ctx
->ws
= amdgpu_winsys(ws
);
292 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
294 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
296 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
300 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
301 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
302 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
304 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
306 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
307 goto error_user_fence_alloc
;
310 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
312 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
313 goto error_user_fence_map
;
316 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
317 ctx
->user_fence_bo
= buf_handle
;
319 return (struct radeon_winsys_ctx
*)ctx
;
321 error_user_fence_map
:
322 amdgpu_bo_free(buf_handle
);
323 error_user_fence_alloc
:
324 amdgpu_cs_ctx_free(ctx
->ctx
);
330 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
332 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
335 static enum pipe_reset_status
336 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
338 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
341 /* Return a failure due to a GPU hang. */
342 if (ctx
->ws
->info
.drm_minor
>= 24) {
345 r
= amdgpu_cs_query_reset_state2(ctx
->ctx
, &flags
);
347 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
348 return PIPE_NO_RESET
;
351 if (flags
& AMDGPU_CTX_QUERY2_FLAGS_RESET
) {
352 if (flags
& AMDGPU_CTX_QUERY2_FLAGS_GUILTY
)
353 return PIPE_GUILTY_CONTEXT_RESET
;
355 return PIPE_INNOCENT_CONTEXT_RESET
;
358 uint32_t result
, hangs
;
360 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
362 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
363 return PIPE_NO_RESET
;
367 case AMDGPU_CTX_GUILTY_RESET
:
368 return PIPE_GUILTY_CONTEXT_RESET
;
369 case AMDGPU_CTX_INNOCENT_RESET
:
370 return PIPE_INNOCENT_CONTEXT_RESET
;
371 case AMDGPU_CTX_UNKNOWN_RESET
:
372 return PIPE_UNKNOWN_CONTEXT_RESET
;
376 /* Return a failure due to a rejected command submission. */
377 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
378 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
379 PIPE_INNOCENT_CONTEXT_RESET
;
381 return PIPE_NO_RESET
;
384 /* COMMAND SUBMISSION */
386 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
388 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
389 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
390 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
391 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
392 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
&&
393 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_JPEG
;
396 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
398 return cs
->ctx
->ws
->info
.chip_class
>= GFX7
&&
399 (cs
->ring_type
== RING_GFX
|| cs
->ring_type
== RING_COMPUTE
);
402 static unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs
*cs
)
404 if (amdgpu_cs_has_chaining(cs
))
405 return 4; /* for chaining */
410 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
412 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
413 int i
= cs
->buffer_indices_hashlist
[hash
];
414 struct amdgpu_cs_buffer
*buffers
;
418 buffers
= cs
->real_buffers
;
419 num_buffers
= cs
->num_real_buffers
;
420 } else if (!bo
->sparse
) {
421 buffers
= cs
->slab_buffers
;
422 num_buffers
= cs
->num_slab_buffers
;
424 buffers
= cs
->sparse_buffers
;
425 num_buffers
= cs
->num_sparse_buffers
;
428 /* not found or found */
429 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
432 /* Hash collision, look for the BO in the list of buffers linearly. */
433 for (i
= num_buffers
- 1; i
>= 0; i
--) {
434 if (buffers
[i
].bo
== bo
) {
435 /* Put this buffer in the hash list.
436 * This will prevent additional hash collisions if there are
437 * several consecutive lookup_buffer calls for the same buffer.
439 * Example: Assuming buffers A,B,C collide in the hash list,
440 * the following sequence of buffers:
441 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
442 * will collide here: ^ and here: ^,
443 * meaning that we should get very few collisions in the end. */
444 cs
->buffer_indices_hashlist
[hash
] = i
;
452 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
454 struct amdgpu_cs_buffer
*buffer
;
457 /* New buffer, check if the backing array is large enough. */
458 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
460 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
461 struct amdgpu_cs_buffer
*new_buffers
;
463 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
466 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
471 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
473 FREE(cs
->real_buffers
);
475 cs
->max_real_buffers
= new_max
;
476 cs
->real_buffers
= new_buffers
;
479 idx
= cs
->num_real_buffers
;
480 buffer
= &cs
->real_buffers
[idx
];
482 memset(buffer
, 0, sizeof(*buffer
));
483 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
484 p_atomic_inc(&bo
->num_cs_references
);
485 cs
->num_real_buffers
++;
491 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
493 struct amdgpu_cs_context
*cs
= acs
->csc
;
495 int idx
= amdgpu_lookup_buffer(cs
, bo
);
500 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
502 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
503 cs
->buffer_indices_hashlist
[hash
] = idx
;
505 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
506 acs
->main
.base
.used_vram
+= bo
->base
.size
;
507 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
508 acs
->main
.base
.used_gart
+= bo
->base
.size
;
513 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
514 struct amdgpu_winsys_bo
*bo
)
516 struct amdgpu_cs_context
*cs
= acs
->csc
;
517 struct amdgpu_cs_buffer
*buffer
;
519 int idx
= amdgpu_lookup_buffer(cs
, bo
);
525 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
529 /* New buffer, check if the backing array is large enough. */
530 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
532 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
533 struct amdgpu_cs_buffer
*new_buffers
;
535 new_buffers
= REALLOC(cs
->slab_buffers
,
536 cs
->max_slab_buffers
* sizeof(*new_buffers
),
537 new_max
* sizeof(*new_buffers
));
539 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
543 cs
->max_slab_buffers
= new_max
;
544 cs
->slab_buffers
= new_buffers
;
547 idx
= cs
->num_slab_buffers
;
548 buffer
= &cs
->slab_buffers
[idx
];
550 memset(buffer
, 0, sizeof(*buffer
));
551 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
552 buffer
->u
.slab
.real_idx
= real_idx
;
553 p_atomic_inc(&bo
->num_cs_references
);
554 cs
->num_slab_buffers
++;
556 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
557 cs
->buffer_indices_hashlist
[hash
] = idx
;
562 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
563 struct amdgpu_winsys_bo
*bo
)
565 struct amdgpu_cs_context
*cs
= acs
->csc
;
566 struct amdgpu_cs_buffer
*buffer
;
568 int idx
= amdgpu_lookup_buffer(cs
, bo
);
573 /* New buffer, check if the backing array is large enough. */
574 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
576 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
577 struct amdgpu_cs_buffer
*new_buffers
;
579 new_buffers
= REALLOC(cs
->sparse_buffers
,
580 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
581 new_max
* sizeof(*new_buffers
));
583 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
587 cs
->max_sparse_buffers
= new_max
;
588 cs
->sparse_buffers
= new_buffers
;
591 idx
= cs
->num_sparse_buffers
;
592 buffer
= &cs
->sparse_buffers
[idx
];
594 memset(buffer
, 0, sizeof(*buffer
));
595 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
596 p_atomic_inc(&bo
->num_cs_references
);
597 cs
->num_sparse_buffers
++;
599 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
600 cs
->buffer_indices_hashlist
[hash
] = idx
;
602 /* We delay adding the backing buffers until we really have to. However,
603 * we cannot delay accounting for memory use.
605 simple_mtx_lock(&bo
->lock
);
607 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
608 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
609 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
610 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
611 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
614 simple_mtx_unlock(&bo
->lock
);
619 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
620 struct pb_buffer
*buf
,
621 enum radeon_bo_usage usage
,
622 enum radeon_bo_domain domains
,
623 enum radeon_bo_priority priority
)
625 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
626 * the buffer placement during command submission.
628 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
629 struct amdgpu_cs_context
*cs
= acs
->csc
;
630 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
631 struct amdgpu_cs_buffer
*buffer
;
634 /* Fast exit for no-op calls.
635 * This is very effective with suballocators and linear uploaders that
636 * are outside of the winsys.
638 if (bo
== cs
->last_added_bo
&&
639 (usage
& cs
->last_added_bo_usage
) == usage
&&
640 (1u << priority
) & cs
->last_added_bo_priority_usage
)
641 return cs
->last_added_bo_index
;
645 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
649 buffer
= &cs
->slab_buffers
[index
];
650 buffer
->usage
|= usage
;
652 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
653 index
= buffer
->u
.slab
.real_idx
;
655 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
660 buffer
= &cs
->real_buffers
[index
];
662 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
666 buffer
= &cs
->sparse_buffers
[index
];
669 buffer
->u
.real
.priority_usage
|= 1u << priority
;
670 buffer
->usage
|= usage
;
672 cs
->last_added_bo
= bo
;
673 cs
->last_added_bo_index
= index
;
674 cs
->last_added_bo_usage
= buffer
->usage
;
675 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
679 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
,
680 struct amdgpu_ib
*ib
,
681 enum ring_type ring_type
)
683 struct pb_buffer
*pb
;
685 unsigned buffer_size
;
687 /* Always create a buffer that is at least as large as the maximum seen IB
688 * size, aligned to a power of two (and multiplied by 4 to reduce internal
689 * fragmentation if chaining is not available). Limit to 512k dwords, which
690 * is the largest power of two that fits into the size field of the
691 * INDIRECT_BUFFER packet.
693 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
694 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
696 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
698 const unsigned min_size
= MAX2(ib
->max_check_space_size
, 8 * 1024 * 4);
699 const unsigned max_size
= 512 * 1024 * 4;
701 buffer_size
= MIN2(buffer_size
, max_size
);
702 buffer_size
= MAX2(buffer_size
, min_size
); /* min_size is more important */
704 pb
= amdgpu_bo_create(ws
, buffer_size
,
705 ws
->info
.gart_page_size
,
707 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
708 (ring_type
== RING_GFX
||
709 ring_type
== RING_COMPUTE
||
710 ring_type
== RING_DMA
?
711 RADEON_FLAG_32BIT
| RADEON_FLAG_GTT_WC
: 0));
715 mapped
= amdgpu_bo_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
717 pb_reference(&pb
, NULL
);
721 pb_reference(&ib
->big_ib_buffer
, pb
);
722 pb_reference(&pb
, NULL
);
724 ib
->ib_mapped
= mapped
;
725 ib
->used_ib_space
= 0;
730 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
732 /* The maximum IB size including all chained IBs. */
735 /* Smaller submits means the GPU gets busy sooner and there is less
736 * waiting for buffers and fences. Proof:
737 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
740 case IB_PARALLEL_COMPUTE
:
741 /* Always chain this IB. */
744 unreachable("bad ib_type");
748 static bool amdgpu_get_new_ib(struct amdgpu_winsys
*ws
, struct amdgpu_cs
*cs
,
749 enum ib_type ib_type
)
751 /* Small IBs are better than big IBs, because the GPU goes idle quicker
752 * and there is less waiting for buffers and fences. Proof:
753 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
755 struct amdgpu_ib
*ib
= NULL
;
756 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
757 /* This is the minimum size of a contiguous IB. */
758 unsigned ib_size
= 4 * 1024 * 4;
761 case IB_PARALLEL_COMPUTE
:
762 ib
= &cs
->compute_ib
;
768 unreachable("unhandled IB type");
771 /* Always allocate at least the size of the biggest cs_check_space call,
772 * because precisely the last call might have requested this size.
774 ib_size
= MAX2(ib_size
, ib
->max_check_space_size
);
776 if (!amdgpu_cs_has_chaining(cs
)) {
777 ib_size
= MAX2(ib_size
,
778 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
779 amdgpu_ib_max_submit_dwords(ib_type
)));
782 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
784 ib
->base
.prev_dw
= 0;
785 ib
->base
.num_prev
= 0;
786 ib
->base
.current
.cdw
= 0;
787 ib
->base
.current
.buf
= NULL
;
789 /* Allocate a new buffer for IBs if the current buffer is all used. */
790 if (!ib
->big_ib_buffer
||
791 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
792 if (!amdgpu_ib_new_buffer(ws
, ib
, cs
->ring_type
))
796 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
798 /* ib_bytes is in dwords and the conversion to bytes will be done before
800 ib
->ptr_ib_size
= &info
->ib_bytes
;
801 ib
->ptr_ib_size_inside_ib
= false;
803 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
804 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
806 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
808 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
809 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
);
810 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
811 ib
->base
.gpu_address
= info
->va_start
;
815 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
817 if (ib
->ptr_ib_size_inside_ib
) {
818 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
819 S_3F2_CHAIN(1) | S_3F2_VALID(1);
821 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
825 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
827 amdgpu_set_ib_size(ib
);
828 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
829 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_alignment
);
830 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
833 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
834 struct amdgpu_cs_context
*cs
,
835 enum ring_type ring_type
)
839 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
843 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
847 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
851 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
855 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
859 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
863 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
868 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
869 AMDGPU_HW_IP_COMPUTE
;
871 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
872 * invalidation is the beginning of IBs (the previous commit does that),
873 * because completion of an IB doesn't care about the state of GPU caches,
874 * but the beginning of an IB does. Draw calls from multiple IBs can be
875 * executed in parallel, so draw calls from the current IB can finish after
876 * the next IB starts drawing, and so the cache flush at the end of IB
879 if (ws
->info
.drm_minor
>= 26)
880 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
887 cs
->ib
[IB_PARALLEL_COMPUTE
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
888 cs
->ib
[IB_PARALLEL_COMPUTE
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
890 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
891 cs
->last_added_bo
= NULL
;
895 static void cleanup_fence_list(struct amdgpu_fence_list
*fences
)
897 for (unsigned i
= 0; i
< fences
->num
; i
++)
898 amdgpu_fence_reference(&fences
->list
[i
], NULL
);
902 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
906 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
907 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
908 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
910 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
911 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
912 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
914 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
915 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
916 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
918 cleanup_fence_list(&cs
->fence_dependencies
);
919 cleanup_fence_list(&cs
->syncobj_dependencies
);
920 cleanup_fence_list(&cs
->syncobj_to_signal
);
921 cleanup_fence_list(&cs
->compute_fence_dependencies
);
922 cleanup_fence_list(&cs
->compute_start_fence_dependencies
);
924 cs
->num_real_buffers
= 0;
925 cs
->num_slab_buffers
= 0;
926 cs
->num_sparse_buffers
= 0;
927 amdgpu_fence_reference(&cs
->fence
, NULL
);
929 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
930 cs
->last_added_bo
= NULL
;
933 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
935 amdgpu_cs_context_cleanup(cs
);
936 FREE(cs
->real_buffers
);
937 FREE(cs
->slab_buffers
);
938 FREE(cs
->sparse_buffers
);
939 FREE(cs
->fence_dependencies
.list
);
940 FREE(cs
->syncobj_dependencies
.list
);
941 FREE(cs
->syncobj_to_signal
.list
);
942 FREE(cs
->compute_fence_dependencies
.list
);
943 FREE(cs
->compute_start_fence_dependencies
.list
);
947 static struct radeon_cmdbuf
*
948 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
949 enum ring_type ring_type
,
950 void (*flush
)(void *ctx
, unsigned flags
,
951 struct pipe_fence_handle
**fence
),
953 bool stop_exec_on_failure
)
955 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
956 struct amdgpu_cs
*cs
;
958 cs
= CALLOC_STRUCT(amdgpu_cs
);
963 util_queue_fence_init(&cs
->flush_completed
);
966 cs
->flush_cs
= flush
;
967 cs
->flush_data
= flush_ctx
;
968 cs
->ring_type
= ring_type
;
969 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
971 struct amdgpu_cs_fence_info fence_info
;
972 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
973 fence_info
.offset
= cs
->ring_type
;
974 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
976 cs
->main
.ib_type
= IB_MAIN
;
977 cs
->compute_ib
.ib_type
= IB_PARALLEL_COMPUTE
;
979 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
984 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
985 amdgpu_destroy_cs_context(&cs
->csc1
);
990 /* Set the first submission context as current. */
994 if (!amdgpu_get_new_ib(ctx
->ws
, cs
, IB_MAIN
)) {
995 amdgpu_destroy_cs_context(&cs
->csc2
);
996 amdgpu_destroy_cs_context(&cs
->csc1
);
1001 p_atomic_inc(&ctx
->ws
->num_cs
);
1002 return &cs
->main
.base
;
1005 static struct radeon_cmdbuf
*
1006 amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf
*ib
,
1007 bool uses_gds_ordered_append
)
1009 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)ib
;
1010 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1012 if (cs
->ring_type
!= RING_GFX
)
1015 /* only one secondary IB can be added */
1016 if (cs
->compute_ib
.ib_mapped
)
1019 /* Allocate the compute IB. */
1020 if (!amdgpu_get_new_ib(ws
, cs
, IB_PARALLEL_COMPUTE
))
1023 if (uses_gds_ordered_append
) {
1024 cs
->csc1
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1025 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1026 cs
->csc2
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1027 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1029 return &cs
->compute_ib
.base
;
1033 amdgpu_cs_setup_preemption(struct radeon_cmdbuf
*rcs
, const uint32_t *preamble_ib
,
1034 unsigned preamble_num_dw
)
1036 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
1037 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
1038 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1039 struct amdgpu_cs_context
*csc
[2] = {&cs
->csc1
, &cs
->csc2
};
1040 unsigned size
= align(preamble_num_dw
* 4, ws
->info
.ib_alignment
);
1041 struct pb_buffer
*preamble_bo
;
1044 /* Create the preamble IB buffer. */
1045 preamble_bo
= amdgpu_bo_create(ws
, size
, ws
->info
.ib_alignment
,
1047 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
1048 RADEON_FLAG_GTT_WC
|
1049 RADEON_FLAG_READ_ONLY
);
1053 map
= (uint32_t*)amdgpu_bo_map(preamble_bo
, NULL
,
1054 PIPE_TRANSFER_WRITE
| RADEON_TRANSFER_TEMPORARY
);
1056 pb_reference(&preamble_bo
, NULL
);
1060 /* Upload the preamble IB. */
1061 memcpy(map
, preamble_ib
, preamble_num_dw
* 4);
1064 uint32_t ib_pad_dw_mask
= ws
->info
.ib_pad_dw_mask
[cs
->ring_type
];
1065 while (preamble_num_dw
& ib_pad_dw_mask
)
1066 map
[preamble_num_dw
++] = PKT3_NOP_PAD
;
1067 amdgpu_bo_unmap(preamble_bo
);
1069 for (unsigned i
= 0; i
< 2; i
++) {
1070 csc
[i
]->ib
[IB_PREAMBLE
] = csc
[i
]->ib
[IB_MAIN
];
1071 csc
[i
]->ib
[IB_PREAMBLE
].flags
|= AMDGPU_IB_FLAG_PREAMBLE
;
1072 csc
[i
]->ib
[IB_PREAMBLE
].va_start
= amdgpu_winsys_bo(preamble_bo
)->va
;
1073 csc
[i
]->ib
[IB_PREAMBLE
].ib_bytes
= preamble_num_dw
* 4;
1075 csc
[i
]->ib
[IB_MAIN
].flags
|= AMDGPU_IB_FLAG_PREEMPT
;
1078 assert(!cs
->preamble_ib_bo
);
1079 cs
->preamble_ib_bo
= preamble_bo
;
1081 amdgpu_cs_add_buffer(rcs
, cs
->preamble_ib_bo
, RADEON_USAGE_READ
, 0,
1086 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
1091 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
,
1092 bool force_chaining
)
1094 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
1095 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
1096 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
1097 unsigned cs_epilog_dw
= amdgpu_cs_epilog_dws(cs
);
1098 unsigned need_byte_size
= (dw
+ cs_epilog_dw
) * 4;
1100 uint32_t *new_ptr_ib_size
;
1102 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1104 /* 125% of the size for IB epilog. */
1105 unsigned safe_byte_size
= need_byte_size
+ need_byte_size
/ 4;
1106 ib
->max_check_space_size
= MAX2(ib
->max_check_space_size
,
1109 /* If force_chaining is true, we can't return. We have to chain. */
1110 if (!force_chaining
) {
1111 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
1114 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
1116 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
1120 if (!amdgpu_cs_has_chaining(cs
)) {
1121 assert(!force_chaining
);
1125 /* Allocate a new chunk */
1126 if (rcs
->num_prev
>= rcs
->max_prev
) {
1127 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
1128 struct radeon_cmdbuf_chunk
*new_prev
;
1130 new_prev
= REALLOC(rcs
->prev
,
1131 sizeof(*new_prev
) * rcs
->max_prev
,
1132 sizeof(*new_prev
) * new_max_prev
);
1136 rcs
->prev
= new_prev
;
1137 rcs
->max_prev
= new_max_prev
;
1140 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1143 assert(ib
->used_ib_space
== 0);
1144 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1146 /* This space was originally reserved. */
1147 rcs
->current
.max_dw
+= cs_epilog_dw
;
1149 /* Pad with NOPs but leave 4 dwords for INDIRECT_BUFFER. */
1150 uint32_t ib_pad_dw_mask
= cs
->ctx
->ws
->info
.ib_pad_dw_mask
[cs
->ring_type
];
1151 while ((rcs
->current
.cdw
& ib_pad_dw_mask
) != ib_pad_dw_mask
- 3)
1152 radeon_emit(rcs
, PKT3_NOP_PAD
);
1154 radeon_emit(rcs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1155 radeon_emit(rcs
, va
);
1156 radeon_emit(rcs
, va
>> 32);
1157 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1158 assert((rcs
->current
.cdw
& ib_pad_dw_mask
) == 0);
1160 assert((rcs
->current
.cdw
& 7) == 0);
1161 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1163 amdgpu_set_ib_size(ib
);
1164 ib
->ptr_ib_size
= new_ptr_ib_size
;
1165 ib
->ptr_ib_size_inside_ib
= true;
1167 /* Hook up the new chunk */
1168 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1169 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1170 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1173 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1174 ib
->base
.current
.cdw
= 0;
1176 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1177 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - cs_epilog_dw
;
1178 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
1179 ib
->base
.gpu_address
= va
;
1181 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1182 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1187 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1188 struct radeon_bo_list_item
*list
)
1190 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1194 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1195 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1196 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1197 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1200 return cs
->num_real_buffers
;
1203 static void add_fence_to_list(struct amdgpu_fence_list
*fences
,
1204 struct amdgpu_fence
*fence
)
1206 unsigned idx
= fences
->num
++;
1208 if (idx
>= fences
->max
) {
1210 const unsigned increment
= 8;
1212 fences
->max
= idx
+ increment
;
1213 size
= fences
->max
* sizeof(fences
->list
[0]);
1214 fences
->list
= realloc(fences
->list
, size
);
1215 /* Clear the newly-allocated elements. */
1216 memset(fences
->list
+ idx
, 0,
1217 increment
* sizeof(fences
->list
[0]));
1219 amdgpu_fence_reference(&fences
->list
[idx
], (struct pipe_fence_handle
*)fence
);
1222 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1223 struct amdgpu_fence
*fence
)
1225 struct amdgpu_cs_context
*cs
= acs
->csc
;
1227 /* Detect no-op dependencies only when there is only 1 ring,
1228 * because IBs on one ring are always executed one at a time.
1230 * We always want no dependency between back-to-back gfx IBs, because
1231 * we need the parallelism between IBs for good performance.
1233 if ((acs
->ring_type
== RING_GFX
||
1234 acs
->ctx
->ws
->info
.num_rings
[acs
->ring_type
] == 1) &&
1235 !amdgpu_fence_is_syncobj(fence
) &&
1236 fence
->ctx
== acs
->ctx
&&
1237 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1238 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1239 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1242 return amdgpu_fence_wait((void *)fence
, 0, false);
1245 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1246 struct pipe_fence_handle
*pfence
,
1247 unsigned dependency_flags
)
1249 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1250 struct amdgpu_cs_context
*cs
= acs
->csc
;
1251 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1253 util_queue_fence_wait(&fence
->submitted
);
1255 if (dependency_flags
& RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
) {
1256 /* Syncobjs are not needed here. */
1257 assert(!amdgpu_fence_is_syncobj(fence
));
1259 if (acs
->ctx
->ws
->info
.has_scheduled_fence_dependency
&&
1260 dependency_flags
& RADEON_DEPENDENCY_START_FENCE
)
1261 add_fence_to_list(&cs
->compute_start_fence_dependencies
, fence
);
1263 add_fence_to_list(&cs
->compute_fence_dependencies
, fence
);
1267 /* Start fences are not needed here. */
1268 assert(!(dependency_flags
& RADEON_DEPENDENCY_START_FENCE
));
1270 if (is_noop_fence_dependency(acs
, fence
))
1273 if (amdgpu_fence_is_syncobj(fence
))
1274 add_fence_to_list(&cs
->syncobj_dependencies
, fence
);
1276 add_fence_to_list(&cs
->fence_dependencies
, fence
);
1279 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1280 struct amdgpu_cs_buffer
*buffer
)
1282 struct amdgpu_cs_context
*cs
= acs
->csc
;
1283 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1284 unsigned new_num_fences
= 0;
1286 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1287 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1289 if (is_noop_fence_dependency(acs
, bo_fence
))
1292 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1295 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1298 add_fence_to_list(&cs
->fence_dependencies
, bo_fence
);
1301 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1302 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1304 bo
->num_fences
= new_num_fences
;
1307 /* Add the given list of fences to the buffer's fence list.
1309 * Must be called with the winsys bo_fence_lock held.
1311 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1312 unsigned num_fences
,
1313 struct pipe_fence_handle
**fences
)
1315 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1316 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1317 struct pipe_fence_handle
**new_fences
=
1319 bo
->num_fences
* sizeof(*new_fences
),
1320 new_max_fences
* sizeof(*new_fences
));
1321 if (likely(new_fences
)) {
1322 bo
->fences
= new_fences
;
1323 bo
->max_fences
= new_max_fences
;
1327 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1328 if (!bo
->num_fences
)
1331 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1332 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1334 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1340 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1341 bo
->fences
[bo
->num_fences
] = NULL
;
1342 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1347 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1348 struct pipe_fence_handle
*fence
,
1349 unsigned num_buffers
,
1350 struct amdgpu_cs_buffer
*buffers
)
1352 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1353 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1354 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1356 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1357 p_atomic_inc(&bo
->num_active_ioctls
);
1358 amdgpu_add_fences(bo
, 1, &fence
);
1362 /* Since the kernel driver doesn't synchronize execution between different
1363 * rings automatically, we have to add fence dependencies manually.
1365 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1367 struct amdgpu_cs_context
*cs
= acs
->csc
;
1369 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1370 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1371 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1374 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1375 struct pipe_fence_handle
*fence
)
1377 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1378 struct amdgpu_cs_context
*cs
= acs
->csc
;
1380 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1382 add_fence_to_list(&cs
->syncobj_to_signal
, (struct amdgpu_fence
*)fence
);
1385 /* Add backing of sparse buffers to the buffer list.
1387 * This is done late, during submission, to keep the buffer list short before
1388 * submit, and to avoid managing fences for the backing buffers.
1390 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1392 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1393 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1394 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1396 simple_mtx_lock(&bo
->lock
);
1398 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1399 /* We can directly add the buffer here, because we know that each
1400 * backing buffer occurs only once.
1402 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1404 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1405 simple_mtx_unlock(&bo
->lock
);
1409 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1410 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1411 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1414 simple_mtx_unlock(&bo
->lock
);
1420 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1422 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1423 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1424 struct amdgpu_cs_context
*cs
= acs
->cst
;
1426 uint32_t bo_list
= 0;
1427 uint64_t seq_no
= 0;
1428 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1429 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1430 struct drm_amdgpu_bo_list_in bo_list_in
;
1432 /* Prepare the buffer list. */
1433 if (ws
->debug_all_bos
) {
1434 /* The buffer list contains all buffers. This is a slow path that
1435 * ensures that no buffer is missing in the BO list.
1437 unsigned num_handles
= 0;
1438 struct drm_amdgpu_bo_list_entry
*list
=
1439 alloca(ws
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1440 struct amdgpu_winsys_bo
*bo
;
1442 simple_mtx_lock(&ws
->global_bo_list_lock
);
1443 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1444 list
[num_handles
].bo_handle
= bo
->u
.real
.kms_handle
;
1445 list
[num_handles
].bo_priority
= 0;
1449 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
, list
, &bo_list
);
1450 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1452 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1456 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1457 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1462 struct drm_amdgpu_bo_list_entry
*list
=
1463 alloca((cs
->num_real_buffers
+ 2) * sizeof(struct drm_amdgpu_bo_list_entry
));
1465 unsigned num_handles
= 0;
1466 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1467 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1468 assert(buffer
->u
.real
.priority_usage
!= 0);
1470 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1471 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1475 if (use_bo_list_create
) {
1476 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1477 r
= amdgpu_bo_list_create_raw(ws
->dev
, num_handles
, list
, &bo_list
);
1479 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1483 /* Standard path passing the buffer list via the CS ioctl. */
1484 bo_list_in
.operation
= ~0;
1485 bo_list_in
.list_handle
= ~0;
1486 bo_list_in
.bo_number
= num_handles
;
1487 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1488 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1492 if (acs
->ring_type
== RING_GFX
)
1493 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1495 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1498 struct drm_amdgpu_cs_chunk chunks
[7];
1499 unsigned num_chunks
= 0;
1502 if (!use_bo_list_create
) {
1503 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1504 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1505 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1509 /* Fence dependencies. */
1510 unsigned num_dependencies
= cs
->fence_dependencies
.num
;
1511 if (num_dependencies
) {
1512 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1513 alloca(num_dependencies
* sizeof(*dep_chunk
));
1515 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1516 struct amdgpu_fence
*fence
=
1517 (struct amdgpu_fence
*)cs
->fence_dependencies
.list
[i
];
1519 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1520 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1523 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1524 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1525 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1529 /* Syncobj dependencies. */
1530 unsigned num_syncobj_dependencies
= cs
->syncobj_dependencies
.num
;
1531 if (num_syncobj_dependencies
) {
1532 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1533 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1535 for (unsigned i
= 0; i
< num_syncobj_dependencies
; i
++) {
1536 struct amdgpu_fence
*fence
=
1537 (struct amdgpu_fence
*)cs
->syncobj_dependencies
.list
[i
];
1539 if (!amdgpu_fence_is_syncobj(fence
))
1542 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1543 sem_chunk
[i
].handle
= fence
->syncobj
;
1546 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1547 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num_syncobj_dependencies
;
1548 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1552 /* Submit the parallel compute IB first. */
1553 if (cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
> 0) {
1554 unsigned old_num_chunks
= num_chunks
;
1556 /* Add compute fence dependencies. */
1557 unsigned num_dependencies
= cs
->compute_fence_dependencies
.num
;
1558 if (num_dependencies
) {
1559 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1560 alloca(num_dependencies
* sizeof(*dep_chunk
));
1562 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1563 struct amdgpu_fence
*fence
=
1564 (struct amdgpu_fence
*)cs
->compute_fence_dependencies
.list
[i
];
1566 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1567 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1570 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1571 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1572 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1576 /* Add compute start fence dependencies. */
1577 unsigned num_start_dependencies
= cs
->compute_start_fence_dependencies
.num
;
1578 if (num_start_dependencies
) {
1579 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1580 alloca(num_start_dependencies
* sizeof(*dep_chunk
));
1582 for (unsigned i
= 0; i
< num_start_dependencies
; i
++) {
1583 struct amdgpu_fence
*fence
=
1584 (struct amdgpu_fence
*)cs
->compute_start_fence_dependencies
.list
[i
];
1586 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1587 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1590 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
;
1591 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_start_dependencies
;
1592 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1596 /* Convert from dwords to bytes. */
1597 cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
*= 4;
1598 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1599 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1600 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_PARALLEL_COMPUTE
];
1603 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1604 num_chunks
, chunks
, NULL
);
1608 /* Back off the compute chunks. */
1609 num_chunks
= old_num_chunks
;
1612 /* Syncobj signals. */
1613 unsigned num_syncobj_to_signal
= cs
->syncobj_to_signal
.num
;
1614 if (num_syncobj_to_signal
) {
1615 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1616 alloca(num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1618 for (unsigned i
= 0; i
< num_syncobj_to_signal
; i
++) {
1619 struct amdgpu_fence
*fence
=
1620 (struct amdgpu_fence
*)cs
->syncobj_to_signal
.list
[i
];
1622 assert(amdgpu_fence_is_syncobj(fence
));
1623 sem_chunk
[i
].handle
= fence
->syncobj
;
1626 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1627 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1628 * num_syncobj_to_signal
;
1629 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1634 if (has_user_fence
) {
1635 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1636 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1637 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1642 if (cs
->ib
[IB_PREAMBLE
].ib_bytes
) {
1643 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1644 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1645 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_PREAMBLE
];
1650 cs
->ib
[IB_MAIN
].ib_bytes
*= 4; /* Convert from dwords to bytes. */
1651 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1652 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1653 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1656 if (ws
->secure
&& cs
->secure
) {
1657 cs
->ib
[IB_PREAMBLE
].flags
|= AMDGPU_IB_FLAGS_SECURE
;
1658 cs
->ib
[IB_MAIN
].flags
|= AMDGPU_IB_FLAGS_SECURE
;
1660 cs
->ib
[IB_PREAMBLE
].flags
&= ~AMDGPU_IB_FLAGS_SECURE
;
1661 cs
->ib
[IB_MAIN
].flags
&= ~AMDGPU_IB_FLAGS_SECURE
;
1664 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1666 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1667 num_chunks
, chunks
, &seq_no
);
1673 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1674 else if (r
== -ECANCELED
)
1675 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1677 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1678 "see dmesg for more information (%i).\n", r
);
1680 acs
->ctx
->num_rejected_cs
++;
1681 ws
->num_total_rejected_cs
++;
1684 uint64_t *user_fence
= NULL
;
1686 /* Need to reserve 4 QWORD for user fence:
1687 * QWORD[0]: completed fence
1688 * QWORD[1]: preempted fence
1689 * QWORD[2]: reset fence
1690 * QWORD[3]: preempted then reset
1693 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
* 4;
1694 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1699 amdgpu_bo_list_destroy_raw(ws
->dev
, bo_list
);
1702 /* If there was an error, signal the fence, because it won't be signalled
1703 * by the hardware. */
1705 amdgpu_fence_signalled(cs
->fence
);
1709 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1710 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1711 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1712 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1713 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1714 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1716 amdgpu_cs_context_cleanup(cs
);
1719 /* Make sure the previous submission is completed. */
1720 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1722 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1724 /* Wait for any pending ioctl of this CS to complete. */
1725 util_queue_fence_wait(&cs
->flush_completed
);
1728 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1730 struct pipe_fence_handle
**fence
)
1732 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1733 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1735 uint32_t ib_pad_dw_mask
= ws
->info
.ib_pad_dw_mask
[cs
->ring_type
];
1737 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
);
1739 /* Pad the IB according to the mask. */
1740 switch (cs
->ring_type
) {
1742 if (ws
->info
.chip_class
<= GFX6
) {
1743 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1744 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1746 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1747 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1752 if (ws
->info
.gfx_ib_pad_with_type2
) {
1753 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1754 radeon_emit(rcs
, PKT2_NOP_PAD
);
1756 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1757 radeon_emit(rcs
, PKT3_NOP_PAD
);
1759 if (cs
->ring_type
== RING_GFX
)
1760 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1762 /* Also pad secondary IBs. */
1763 if (cs
->compute_ib
.ib_mapped
) {
1764 while (cs
->compute_ib
.base
.current
.cdw
& ib_pad_dw_mask
)
1765 radeon_emit(&cs
->compute_ib
.base
, PKT3_NOP_PAD
);
1770 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1771 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1774 if (rcs
->current
.cdw
% 2)
1776 while (rcs
->current
.cdw
& ib_pad_dw_mask
) {
1777 radeon_emit(rcs
, 0x60000000); /* nop packet */
1778 radeon_emit(rcs
, 0x00000000);
1782 while (rcs
->current
.cdw
& ib_pad_dw_mask
)
1783 radeon_emit(rcs
, 0x81ff); /* nop packet */
1789 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1790 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1793 /* If the CS is not empty or overflowed.... */
1794 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1795 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1796 !debug_get_option_noop())) {
1797 struct amdgpu_cs_context
*cur
= cs
->csc
;
1800 amdgpu_ib_finalize(ws
, &cs
->main
);
1802 if (cs
->compute_ib
.ib_mapped
)
1803 amdgpu_ib_finalize(ws
, &cs
->compute_ib
);
1805 /* Create a fence. */
1806 amdgpu_fence_reference(&cur
->fence
, NULL
);
1807 if (cs
->next_fence
) {
1808 /* just move the reference */
1809 cur
->fence
= cs
->next_fence
;
1810 cs
->next_fence
= NULL
;
1812 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1813 cur
->ib
[IB_MAIN
].ip_type
,
1814 cur
->ib
[IB_MAIN
].ip_instance
,
1815 cur
->ib
[IB_MAIN
].ring
);
1818 amdgpu_fence_reference(fence
, cur
->fence
);
1820 amdgpu_cs_sync_flush(rcs
);
1824 * This fence must be held until the submission is queued to ensure
1825 * that the order of fence dependency updates matches the order of
1828 simple_mtx_lock(&ws
->bo_fence_lock
);
1829 amdgpu_add_fence_dependencies_bo_lists(cs
);
1831 /* Swap command streams. "cst" is going to be submitted. */
1836 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1837 amdgpu_cs_submit_ib
, NULL
, 0);
1838 /* The submission has been queued, unlock the fence now. */
1839 simple_mtx_unlock(&ws
->bo_fence_lock
);
1841 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1842 amdgpu_cs_sync_flush(rcs
);
1843 error_code
= cur
->error_code
;
1846 amdgpu_cs_context_cleanup(cs
->csc
);
1849 amdgpu_get_new_ib(ws
, cs
, IB_MAIN
);
1850 if (cs
->compute_ib
.ib_mapped
)
1851 amdgpu_get_new_ib(ws
, cs
, IB_PARALLEL_COMPUTE
);
1853 if (cs
->preamble_ib_bo
) {
1854 amdgpu_cs_add_buffer(rcs
, cs
->preamble_ib_bo
, RADEON_USAGE_READ
, 0,
1858 cs
->main
.base
.used_gart
= 0;
1859 cs
->main
.base
.used_vram
= 0;
1861 if (cs
->ring_type
== RING_GFX
)
1863 else if (cs
->ring_type
== RING_DMA
)
1869 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1871 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1873 amdgpu_cs_sync_flush(rcs
);
1874 util_queue_fence_destroy(&cs
->flush_completed
);
1875 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1876 pb_reference(&cs
->preamble_ib_bo
, NULL
);
1877 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1878 FREE(cs
->main
.base
.prev
);
1879 pb_reference(&cs
->compute_ib
.big_ib_buffer
, NULL
);
1880 FREE(cs
->compute_ib
.base
.prev
);
1881 amdgpu_destroy_cs_context(&cs
->csc1
);
1882 amdgpu_destroy_cs_context(&cs
->csc2
);
1883 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1887 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1888 struct pb_buffer
*_buf
,
1889 enum radeon_bo_usage usage
)
1891 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1892 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1894 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1897 void amdgpu_cs_init_functions(struct amdgpu_screen_winsys
*ws
)
1899 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1900 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1901 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1902 ws
->base
.cs_create
= amdgpu_cs_create
;
1903 ws
->base
.cs_add_parallel_compute_ib
= amdgpu_cs_add_parallel_compute_ib
;
1904 ws
->base
.cs_setup_preemption
= amdgpu_cs_setup_preemption
;
1905 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1906 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1907 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1908 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1909 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1910 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1911 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1912 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1913 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1914 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1915 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1916 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1917 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1918 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1919 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1920 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1921 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;