2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 util_queue_fence_init(&fence
->submitted
);
54 util_queue_fence_reset(&fence
->submitted
);
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static struct pipe_fence_handle
*
60 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
62 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
63 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
69 pipe_reference_init(&fence
->reference
, 1);
72 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
78 util_queue_fence_init(&fence
->submitted
);
80 assert(amdgpu_fence_is_syncobj(fence
));
81 return (struct pipe_fence_handle
*)fence
;
84 static struct pipe_fence_handle
*
85 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
87 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
88 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
93 pipe_reference_init(&fence
->reference
, 1);
95 /* fence->ctx == NULL means that the fence is syncobj-based. */
97 /* Convert sync_file into syncobj. */
98 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
104 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
106 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
111 util_queue_fence_init(&fence
->submitted
);
113 return (struct pipe_fence_handle
*)fence
;
116 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
117 struct pipe_fence_handle
*pfence
)
119 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
120 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
122 if (amdgpu_fence_is_syncobj(fence
)) {
125 /* Convert syncobj into sync_file. */
126 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
130 util_queue_fence_wait(&fence
->submitted
);
132 /* Convert the amdgpu fence into a fence FD. */
134 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
135 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
142 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
144 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
148 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
154 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
159 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
163 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
165 uint64_t *user_fence_cpu_address
)
167 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
169 afence
->fence
.fence
= seq_no
;
170 afence
->user_fence_cpu_address
= user_fence_cpu_address
;
171 util_queue_fence_signal(&afence
->submitted
);
174 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
176 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
178 afence
->signalled
= true;
179 util_queue_fence_signal(&afence
->submitted
);
182 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
185 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
188 uint64_t *user_fence_cpu
;
191 if (afence
->signalled
)
194 /* Handle syncobjs. */
195 if (amdgpu_fence_is_syncobj(afence
)) {
196 /* Absolute timeouts are only be used by BO fences, which aren't
197 * backed by syncobjs.
201 if (amdgpu_cs_syncobj_wait(afence
->ws
->dev
, &afence
->syncobj
, 1,
205 afence
->signalled
= true;
210 abs_timeout
= timeout
;
212 abs_timeout
= os_time_get_absolute_timeout(timeout
);
214 /* The fence might not have a number assigned if its IB is being
215 * submitted in the other thread right now. Wait until the submission
217 if (!util_queue_fence_wait_timeout(&afence
->submitted
, abs_timeout
))
220 user_fence_cpu
= afence
->user_fence_cpu_address
;
221 if (user_fence_cpu
) {
222 if (*user_fence_cpu
>= afence
->fence
.fence
) {
223 afence
->signalled
= true;
227 /* No timeout, just query: no need for the ioctl. */
228 if (!absolute
&& !timeout
)
232 /* Now use the libdrm query. */
233 r
= amdgpu_cs_query_fence_status(&afence
->fence
,
235 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
238 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
243 /* This variable can only transition from false to true, so it doesn't
244 * matter if threads race for it. */
245 afence
->signalled
= true;
251 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
252 struct pipe_fence_handle
*fence
,
255 return amdgpu_fence_wait(fence
, timeout
, false);
258 static struct pipe_fence_handle
*
259 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
261 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
262 struct pipe_fence_handle
*fence
= NULL
;
264 if (debug_get_option_noop())
267 if (cs
->next_fence
) {
268 amdgpu_fence_reference(&fence
, cs
->next_fence
);
272 fence
= amdgpu_fence_create(cs
->ctx
,
273 cs
->csc
->ib
[IB_MAIN
].ip_type
,
274 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
275 cs
->csc
->ib
[IB_MAIN
].ring
);
279 amdgpu_fence_reference(&cs
->next_fence
, fence
);
285 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
287 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
289 struct amdgpu_bo_alloc_request alloc_buffer
= {};
290 amdgpu_bo_handle buf_handle
;
295 ctx
->ws
= amdgpu_winsys(ws
);
297 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
299 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
301 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
305 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
306 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
307 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
309 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
311 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
312 goto error_user_fence_alloc
;
315 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
317 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
318 goto error_user_fence_map
;
321 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
322 ctx
->user_fence_bo
= buf_handle
;
324 return (struct radeon_winsys_ctx
*)ctx
;
326 error_user_fence_map
:
327 amdgpu_bo_free(buf_handle
);
328 error_user_fence_alloc
:
329 amdgpu_cs_ctx_free(ctx
->ctx
);
335 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
337 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
340 static enum pipe_reset_status
341 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
343 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
344 uint32_t result
, hangs
;
347 /* Return a failure due to a rejected command submission. */
348 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
349 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
350 PIPE_INNOCENT_CONTEXT_RESET
;
353 /* Return a failure due to a GPU hang. */
354 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
356 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
357 return PIPE_NO_RESET
;
361 case AMDGPU_CTX_GUILTY_RESET
:
362 return PIPE_GUILTY_CONTEXT_RESET
;
363 case AMDGPU_CTX_INNOCENT_RESET
:
364 return PIPE_INNOCENT_CONTEXT_RESET
;
365 case AMDGPU_CTX_UNKNOWN_RESET
:
366 return PIPE_UNKNOWN_CONTEXT_RESET
;
367 case AMDGPU_CTX_NO_RESET
:
369 return PIPE_NO_RESET
;
373 /* COMMAND SUBMISSION */
375 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
377 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
378 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
379 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
380 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
381 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
;
384 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
386 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
387 cs
->ring_type
== RING_GFX
;
390 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
392 if (ring_type
== RING_GFX
)
393 return 4; /* for chaining */
398 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
400 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
401 int i
= cs
->buffer_indices_hashlist
[hash
];
402 struct amdgpu_cs_buffer
*buffers
;
406 buffers
= cs
->real_buffers
;
407 num_buffers
= cs
->num_real_buffers
;
408 } else if (!bo
->sparse
) {
409 buffers
= cs
->slab_buffers
;
410 num_buffers
= cs
->num_slab_buffers
;
412 buffers
= cs
->sparse_buffers
;
413 num_buffers
= cs
->num_sparse_buffers
;
416 /* not found or found */
417 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
420 /* Hash collision, look for the BO in the list of buffers linearly. */
421 for (i
= num_buffers
- 1; i
>= 0; i
--) {
422 if (buffers
[i
].bo
== bo
) {
423 /* Put this buffer in the hash list.
424 * This will prevent additional hash collisions if there are
425 * several consecutive lookup_buffer calls for the same buffer.
427 * Example: Assuming buffers A,B,C collide in the hash list,
428 * the following sequence of buffers:
429 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
430 * will collide here: ^ and here: ^,
431 * meaning that we should get very few collisions in the end. */
432 cs
->buffer_indices_hashlist
[hash
] = i
;
440 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
442 struct amdgpu_cs_buffer
*buffer
;
445 /* New buffer, check if the backing array is large enough. */
446 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
448 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
449 struct amdgpu_cs_buffer
*new_buffers
;
451 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
454 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
459 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
461 FREE(cs
->real_buffers
);
463 cs
->max_real_buffers
= new_max
;
464 cs
->real_buffers
= new_buffers
;
467 idx
= cs
->num_real_buffers
;
468 buffer
= &cs
->real_buffers
[idx
];
470 memset(buffer
, 0, sizeof(*buffer
));
471 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
472 p_atomic_inc(&bo
->num_cs_references
);
473 cs
->num_real_buffers
++;
479 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
481 struct amdgpu_cs_context
*cs
= acs
->csc
;
483 int idx
= amdgpu_lookup_buffer(cs
, bo
);
488 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
490 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
491 cs
->buffer_indices_hashlist
[hash
] = idx
;
493 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
494 acs
->main
.base
.used_vram
+= bo
->base
.size
;
495 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
496 acs
->main
.base
.used_gart
+= bo
->base
.size
;
501 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
502 struct amdgpu_winsys_bo
*bo
)
504 struct amdgpu_cs_context
*cs
= acs
->csc
;
505 struct amdgpu_cs_buffer
*buffer
;
507 int idx
= amdgpu_lookup_buffer(cs
, bo
);
513 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
517 /* New buffer, check if the backing array is large enough. */
518 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
520 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
521 struct amdgpu_cs_buffer
*new_buffers
;
523 new_buffers
= REALLOC(cs
->slab_buffers
,
524 cs
->max_slab_buffers
* sizeof(*new_buffers
),
525 new_max
* sizeof(*new_buffers
));
527 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
531 cs
->max_slab_buffers
= new_max
;
532 cs
->slab_buffers
= new_buffers
;
535 idx
= cs
->num_slab_buffers
;
536 buffer
= &cs
->slab_buffers
[idx
];
538 memset(buffer
, 0, sizeof(*buffer
));
539 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
540 buffer
->u
.slab
.real_idx
= real_idx
;
541 p_atomic_inc(&bo
->num_cs_references
);
542 cs
->num_slab_buffers
++;
544 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
545 cs
->buffer_indices_hashlist
[hash
] = idx
;
550 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
551 struct amdgpu_winsys_bo
*bo
)
553 struct amdgpu_cs_context
*cs
= acs
->csc
;
554 struct amdgpu_cs_buffer
*buffer
;
556 int idx
= amdgpu_lookup_buffer(cs
, bo
);
561 /* New buffer, check if the backing array is large enough. */
562 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
564 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
565 struct amdgpu_cs_buffer
*new_buffers
;
567 new_buffers
= REALLOC(cs
->sparse_buffers
,
568 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
569 new_max
* sizeof(*new_buffers
));
571 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
575 cs
->max_sparse_buffers
= new_max
;
576 cs
->sparse_buffers
= new_buffers
;
579 idx
= cs
->num_sparse_buffers
;
580 buffer
= &cs
->sparse_buffers
[idx
];
582 memset(buffer
, 0, sizeof(*buffer
));
583 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
584 p_atomic_inc(&bo
->num_cs_references
);
585 cs
->num_sparse_buffers
++;
587 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
588 cs
->buffer_indices_hashlist
[hash
] = idx
;
590 /* We delay adding the backing buffers until we really have to. However,
591 * we cannot delay accounting for memory use.
593 simple_mtx_lock(&bo
->lock
);
595 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
596 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
597 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
598 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
599 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
602 simple_mtx_unlock(&bo
->lock
);
607 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
608 struct pb_buffer
*buf
,
609 enum radeon_bo_usage usage
,
610 enum radeon_bo_domain domains
,
611 enum radeon_bo_priority priority
)
613 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
614 * the buffer placement during command submission.
616 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
617 struct amdgpu_cs_context
*cs
= acs
->csc
;
618 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
619 struct amdgpu_cs_buffer
*buffer
;
622 /* Fast exit for no-op calls.
623 * This is very effective with suballocators and linear uploaders that
624 * are outside of the winsys.
626 if (bo
== cs
->last_added_bo
&&
627 (usage
& cs
->last_added_bo_usage
) == usage
&&
628 (1u << priority
) & cs
->last_added_bo_priority_usage
)
629 return cs
->last_added_bo_index
;
633 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
637 buffer
= &cs
->slab_buffers
[index
];
638 buffer
->usage
|= usage
;
640 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
641 index
= buffer
->u
.slab
.real_idx
;
643 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
648 buffer
= &cs
->real_buffers
[index
];
650 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
654 buffer
= &cs
->sparse_buffers
[index
];
657 buffer
->u
.real
.priority_usage
|= 1u << priority
;
658 buffer
->usage
|= usage
;
660 cs
->last_added_bo
= bo
;
661 cs
->last_added_bo_index
= index
;
662 cs
->last_added_bo_usage
= buffer
->usage
;
663 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
667 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
668 enum ring_type ring_type
)
670 struct pb_buffer
*pb
;
672 unsigned buffer_size
;
674 /* Always create a buffer that is at least as large as the maximum seen IB
675 * size, aligned to a power of two (and multiplied by 4 to reduce internal
676 * fragmentation if chaining is not available). Limit to 512k dwords, which
677 * is the largest power of two that fits into the size field of the
678 * INDIRECT_BUFFER packet.
680 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
681 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
683 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
685 const unsigned min_size
= MAX2(ib
->max_check_space_size
, 8 * 1024 * 4);
686 const unsigned max_size
= 512 * 1024 * 4;
688 buffer_size
= MIN2(buffer_size
, max_size
);
689 buffer_size
= MAX2(buffer_size
, min_size
); /* min_size is more important */
691 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
692 ws
->info
.gart_page_size
,
694 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
695 (ring_type
== RING_GFX
||
696 ring_type
== RING_COMPUTE
||
697 ring_type
== RING_DMA
?
698 RADEON_FLAG_READ_ONLY
| RADEON_FLAG_GTT_WC
: 0));
702 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
704 pb_reference(&pb
, NULL
);
708 pb_reference(&ib
->big_ib_buffer
, pb
);
709 pb_reference(&pb
, NULL
);
711 ib
->ib_mapped
= mapped
;
712 ib
->used_ib_space
= 0;
717 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
721 /* Smaller submits means the GPU gets busy sooner and there is less
722 * waiting for buffers and fences. Proof:
723 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
727 unreachable("bad ib_type");
731 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
732 enum ib_type ib_type
)
734 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
735 /* Small IBs are better than big IBs, because the GPU goes idle quicker
736 * and there is less waiting for buffers and fences. Proof:
737 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
739 struct amdgpu_ib
*ib
= NULL
;
740 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
741 unsigned ib_size
= 0;
746 ib_size
= 4 * 1024 * 4;
749 unreachable("unhandled IB type");
752 /* Always allocate at least the size of the biggest cs_check_space call,
753 * because precisely the last call might have requested this size.
755 ib_size
= MAX2(ib_size
, ib
->max_check_space_size
);
757 if (!amdgpu_cs_has_chaining(cs
)) {
758 ib_size
= MAX2(ib_size
,
759 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
760 amdgpu_ib_max_submit_dwords(ib_type
)));
763 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
765 ib
->base
.prev_dw
= 0;
766 ib
->base
.num_prev
= 0;
767 ib
->base
.current
.cdw
= 0;
768 ib
->base
.current
.buf
= NULL
;
770 /* Allocate a new buffer for IBs if the current buffer is all used. */
771 if (!ib
->big_ib_buffer
||
772 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
773 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
777 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
779 /* ib_bytes is in dwords and the conversion to bytes will be done before
781 ib
->ptr_ib_size
= &info
->ib_bytes
;
782 ib
->ptr_ib_size_inside_ib
= false;
784 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
785 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
787 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
789 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
790 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
791 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
795 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
797 if (ib
->ptr_ib_size_inside_ib
) {
798 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
799 S_3F2_CHAIN(1) | S_3F2_VALID(1);
801 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
805 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
807 amdgpu_set_ib_size(ib
);
808 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
809 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_start_alignment
);
810 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
813 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
814 struct amdgpu_cs_context
*cs
,
815 enum ring_type ring_type
)
819 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
823 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
827 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
831 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
835 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
839 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
843 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
848 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
849 AMDGPU_HW_IP_COMPUTE
;
851 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
852 * invalidation is the beginning of IBs (the previous commit does that),
853 * because completion of an IB doesn't care about the state of GPU caches,
854 * but the beginning of an IB does. Draw calls from multiple IBs can be
855 * executed in parallel, so draw calls from the current IB can finish after
856 * the next IB starts drawing, and so the cache flush at the end of IB
859 if (ws
->info
.drm_minor
>= 26)
860 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
867 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
868 cs
->last_added_bo
= NULL
;
872 static void cleanup_fence_list(struct amdgpu_fence_list
*fences
)
874 for (unsigned i
= 0; i
< fences
->num
; i
++)
875 amdgpu_fence_reference(&fences
->list
[i
], NULL
);
879 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
883 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
884 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
885 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
887 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
888 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
889 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
891 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
892 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
893 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
895 cleanup_fence_list(&cs
->fence_dependencies
);
896 cleanup_fence_list(&cs
->syncobj_dependencies
);
897 cleanup_fence_list(&cs
->syncobj_to_signal
);
899 cs
->num_real_buffers
= 0;
900 cs
->num_slab_buffers
= 0;
901 cs
->num_sparse_buffers
= 0;
902 amdgpu_fence_reference(&cs
->fence
, NULL
);
904 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
905 cs
->last_added_bo
= NULL
;
908 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
910 amdgpu_cs_context_cleanup(cs
);
911 FREE(cs
->real_buffers
);
912 FREE(cs
->slab_buffers
);
913 FREE(cs
->sparse_buffers
);
914 FREE(cs
->fence_dependencies
.list
);
915 FREE(cs
->syncobj_dependencies
.list
);
916 FREE(cs
->syncobj_to_signal
.list
);
920 static struct radeon_cmdbuf
*
921 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
922 enum ring_type ring_type
,
923 void (*flush
)(void *ctx
, unsigned flags
,
924 struct pipe_fence_handle
**fence
),
926 bool stop_exec_on_failure
)
928 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
929 struct amdgpu_cs
*cs
;
931 cs
= CALLOC_STRUCT(amdgpu_cs
);
936 util_queue_fence_init(&cs
->flush_completed
);
939 cs
->flush_cs
= flush
;
940 cs
->flush_data
= flush_ctx
;
941 cs
->ring_type
= ring_type
;
942 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
944 struct amdgpu_cs_fence_info fence_info
;
945 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
946 fence_info
.offset
= cs
->ring_type
;
947 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
949 cs
->main
.ib_type
= IB_MAIN
;
951 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
956 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
957 amdgpu_destroy_cs_context(&cs
->csc1
);
962 /* Set the first submission context as current. */
966 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
967 amdgpu_destroy_cs_context(&cs
->csc2
);
968 amdgpu_destroy_cs_context(&cs
->csc1
);
973 p_atomic_inc(&ctx
->ws
->num_cs
);
974 return &cs
->main
.base
;
977 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
982 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
)
984 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
985 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
986 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
987 unsigned cs_epilog_dw
= amdgpu_cs_epilog_dws(cs
->ring_type
);
988 unsigned need_byte_size
= (dw
+ cs_epilog_dw
) * 4;
990 uint32_t *new_ptr_ib_size
;
992 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
994 /* 125% of the size for IB epilog. */
995 unsigned safe_byte_size
= need_byte_size
+ need_byte_size
/ 4;
996 ib
->max_check_space_size
= MAX2(ib
->max_check_space_size
,
999 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
1002 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
1004 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
1007 if (!amdgpu_cs_has_chaining(cs
))
1010 /* Allocate a new chunk */
1011 if (rcs
->num_prev
>= rcs
->max_prev
) {
1012 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
1013 struct radeon_cmdbuf_chunk
*new_prev
;
1015 new_prev
= REALLOC(rcs
->prev
,
1016 sizeof(*new_prev
) * rcs
->max_prev
,
1017 sizeof(*new_prev
) * new_max_prev
);
1021 rcs
->prev
= new_prev
;
1022 rcs
->max_prev
= new_max_prev
;
1025 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1028 assert(ib
->used_ib_space
== 0);
1029 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1031 /* This space was originally reserved. */
1032 rcs
->current
.max_dw
+= 4;
1033 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
1035 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1036 while ((rcs
->current
.cdw
& 7) != 4)
1037 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1039 radeon_emit(rcs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1040 radeon_emit(rcs
, va
);
1041 radeon_emit(rcs
, va
>> 32);
1042 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1044 assert((rcs
->current
.cdw
& 7) == 0);
1045 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1047 amdgpu_set_ib_size(ib
);
1048 ib
->ptr_ib_size
= new_ptr_ib_size
;
1049 ib
->ptr_ib_size_inside_ib
= true;
1051 /* Hook up the new chunk */
1052 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1053 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1054 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1057 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1058 ib
->base
.current
.cdw
= 0;
1060 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1061 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - cs_epilog_dw
;
1062 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
1064 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1065 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1070 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1071 struct radeon_bo_list_item
*list
)
1073 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1077 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1078 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1079 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1080 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1083 return cs
->num_real_buffers
;
1086 static void add_fence_to_list(struct amdgpu_fence_list
*fences
,
1087 struct amdgpu_fence
*fence
)
1089 unsigned idx
= fences
->num
++;
1091 if (idx
>= fences
->max
) {
1093 const unsigned increment
= 8;
1095 fences
->max
= idx
+ increment
;
1096 size
= fences
->max
* sizeof(fences
->list
[0]);
1097 fences
->list
= realloc(fences
->list
, size
);
1098 /* Clear the newly-allocated elements. */
1099 memset(fences
->list
+ idx
, 0,
1100 increment
* sizeof(fences
->list
[0]));
1102 amdgpu_fence_reference(&fences
->list
[idx
], (struct pipe_fence_handle
*)fence
);
1105 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1106 struct amdgpu_fence
*fence
)
1108 struct amdgpu_cs_context
*cs
= acs
->csc
;
1110 if (!amdgpu_fence_is_syncobj(fence
) &&
1111 fence
->ctx
== acs
->ctx
&&
1112 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1113 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1114 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1117 return amdgpu_fence_wait((void *)fence
, 0, false);
1120 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1121 struct pipe_fence_handle
*pfence
)
1123 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1124 struct amdgpu_cs_context
*cs
= acs
->csc
;
1125 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1127 util_queue_fence_wait(&fence
->submitted
);
1129 if (is_noop_fence_dependency(acs
, fence
))
1132 if (amdgpu_fence_is_syncobj(fence
))
1133 add_fence_to_list(&cs
->syncobj_dependencies
, fence
);
1135 add_fence_to_list(&cs
->fence_dependencies
, fence
);
1138 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1139 struct amdgpu_cs_buffer
*buffer
)
1141 struct amdgpu_cs_context
*cs
= acs
->csc
;
1142 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1143 unsigned new_num_fences
= 0;
1145 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1146 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1148 if (is_noop_fence_dependency(acs
, bo_fence
))
1151 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1154 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1157 add_fence_to_list(&cs
->fence_dependencies
, bo_fence
);
1160 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1161 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1163 bo
->num_fences
= new_num_fences
;
1166 /* Add the given list of fences to the buffer's fence list.
1168 * Must be called with the winsys bo_fence_lock held.
1170 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1171 unsigned num_fences
,
1172 struct pipe_fence_handle
**fences
)
1174 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1175 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1176 struct pipe_fence_handle
**new_fences
=
1178 bo
->num_fences
* sizeof(*new_fences
),
1179 new_max_fences
* sizeof(*new_fences
));
1180 if (likely(new_fences
)) {
1181 bo
->fences
= new_fences
;
1182 bo
->max_fences
= new_max_fences
;
1186 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1187 if (!bo
->num_fences
)
1190 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1191 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1193 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1199 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1200 bo
->fences
[bo
->num_fences
] = NULL
;
1201 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1206 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1207 struct pipe_fence_handle
*fence
,
1208 unsigned num_buffers
,
1209 struct amdgpu_cs_buffer
*buffers
)
1211 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1212 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1213 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1215 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1216 p_atomic_inc(&bo
->num_active_ioctls
);
1217 amdgpu_add_fences(bo
, 1, &fence
);
1221 /* Since the kernel driver doesn't synchronize execution between different
1222 * rings automatically, we have to add fence dependencies manually.
1224 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1226 struct amdgpu_cs_context
*cs
= acs
->csc
;
1228 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1229 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1230 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1233 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1234 struct pipe_fence_handle
*fence
)
1236 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1237 struct amdgpu_cs_context
*cs
= acs
->csc
;
1239 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1241 add_fence_to_list(&cs
->syncobj_to_signal
, (struct amdgpu_fence
*)fence
);
1244 /* Add backing of sparse buffers to the buffer list.
1246 * This is done late, during submission, to keep the buffer list short before
1247 * submit, and to avoid managing fences for the backing buffers.
1249 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1251 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1252 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1253 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1255 simple_mtx_lock(&bo
->lock
);
1257 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1258 /* We can directly add the buffer here, because we know that each
1259 * backing buffer occurs only once.
1261 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1263 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1264 simple_mtx_unlock(&bo
->lock
);
1268 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1269 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1270 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1273 simple_mtx_unlock(&bo
->lock
);
1279 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1281 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1282 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1283 struct amdgpu_cs_context
*cs
= acs
->cst
;
1285 uint32_t bo_list
= 0;
1286 uint64_t seq_no
= 0;
1287 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1288 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1289 struct drm_amdgpu_bo_list_in bo_list_in
;
1291 /* Prepare the buffer list. */
1292 if (ws
->debug_all_bos
) {
1293 /* The buffer list contains all buffers. This is a slow path that
1294 * ensures that no buffer is missing in the BO list.
1296 unsigned num_handles
= 0;
1297 struct drm_amdgpu_bo_list_entry
*list
=
1298 alloca(ws
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1299 struct amdgpu_winsys_bo
*bo
;
1301 simple_mtx_lock(&ws
->global_bo_list_lock
);
1302 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1306 list
[num_handles
].bo_handle
= bo
->u
.real
.kms_handle
;
1307 list
[num_handles
].bo_priority
= 0;
1311 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
, list
, &bo_list
);
1312 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1314 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1318 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1319 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1324 struct drm_amdgpu_bo_list_entry
*list
=
1325 alloca(cs
->num_real_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1327 unsigned num_handles
= 0;
1328 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1329 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1331 if (buffer
->bo
->is_local
)
1334 assert(buffer
->u
.real
.priority_usage
!= 0);
1336 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1337 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1341 if (use_bo_list_create
) {
1342 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1343 r
= amdgpu_bo_list_create_raw(ws
->dev
, num_handles
, list
, &bo_list
);
1345 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1349 /* Standard path passing the buffer list via the CS ioctl. */
1350 bo_list_in
.operation
= ~0;
1351 bo_list_in
.list_handle
= ~0;
1352 bo_list_in
.bo_number
= num_handles
;
1353 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1354 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1358 if (acs
->ring_type
== RING_GFX
)
1359 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1361 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1364 struct drm_amdgpu_cs_chunk chunks
[6];
1365 unsigned num_chunks
= 0;
1367 /* Convert from dwords to bytes. */
1368 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1371 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1372 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1373 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1377 if (has_user_fence
) {
1378 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1379 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1380 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1384 /* Fence dependencies. */
1385 unsigned num_dependencies
= cs
->fence_dependencies
.num
;
1386 if (num_dependencies
) {
1387 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1388 alloca(num_dependencies
* sizeof(*dep_chunk
));
1390 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1391 struct amdgpu_fence
*fence
=
1392 (struct amdgpu_fence
*)cs
->fence_dependencies
.list
[i
];
1394 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1395 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1398 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1399 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1400 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1404 /* Syncobj dependencies. */
1405 unsigned num_syncobj_dependencies
= cs
->syncobj_dependencies
.num
;
1406 if (num_syncobj_dependencies
) {
1407 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1408 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1410 for (unsigned i
= 0; i
< num_syncobj_dependencies
; i
++) {
1411 struct amdgpu_fence
*fence
=
1412 (struct amdgpu_fence
*)cs
->syncobj_dependencies
.list
[i
];
1414 if (!amdgpu_fence_is_syncobj(fence
))
1417 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1418 sem_chunk
[i
].handle
= fence
->syncobj
;
1421 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1422 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num_syncobj_dependencies
;
1423 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1427 /* Syncobj signals. */
1428 unsigned num_syncobj_to_signal
= cs
->syncobj_to_signal
.num
;
1429 if (num_syncobj_to_signal
) {
1430 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1431 alloca(num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1433 for (unsigned i
= 0; i
< num_syncobj_to_signal
; i
++) {
1434 struct amdgpu_fence
*fence
=
1435 (struct amdgpu_fence
*)cs
->syncobj_to_signal
.list
[i
];
1437 assert(amdgpu_fence_is_syncobj(fence
));
1438 sem_chunk
[i
].handle
= fence
->syncobj
;
1441 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1442 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1443 * num_syncobj_to_signal
;
1444 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1449 if (!use_bo_list_create
) {
1450 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1451 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1452 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1456 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1458 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1459 num_chunks
, chunks
, &seq_no
);
1464 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1465 else if (r
== -ECANCELED
)
1466 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1468 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1469 "see dmesg for more information (%i).\n", r
);
1471 acs
->ctx
->num_rejected_cs
++;
1472 ws
->num_total_rejected_cs
++;
1475 uint64_t *user_fence
= NULL
;
1478 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1479 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1484 amdgpu_bo_list_destroy_raw(ws
->dev
, bo_list
);
1487 /* If there was an error, signal the fence, because it won't be signalled
1488 * by the hardware. */
1490 amdgpu_fence_signalled(cs
->fence
);
1494 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1495 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1496 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1497 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1498 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1499 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1501 amdgpu_cs_context_cleanup(cs
);
1504 /* Make sure the previous submission is completed. */
1505 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1507 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1509 /* Wait for any pending ioctl of this CS to complete. */
1510 util_queue_fence_wait(&cs
->flush_completed
);
1513 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1515 struct pipe_fence_handle
**fence
)
1517 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1518 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1521 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1523 switch (cs
->ring_type
) {
1525 /* pad DMA ring to 8 DWs */
1526 if (ws
->info
.chip_class
<= SI
) {
1527 while (rcs
->current
.cdw
& 7)
1528 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1530 while (rcs
->current
.cdw
& 7)
1531 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1536 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1537 if (ws
->info
.gfx_ib_pad_with_type2
) {
1538 while (rcs
->current
.cdw
& 7)
1539 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1541 while (rcs
->current
.cdw
& 7)
1542 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1544 if (cs
->ring_type
== RING_GFX
)
1545 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1549 while (rcs
->current
.cdw
& 15)
1550 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1553 if (rcs
->current
.cdw
% 2)
1555 while (rcs
->current
.cdw
& 15) {
1556 radeon_emit(rcs
, 0x60000000); /* nop packet */
1557 radeon_emit(rcs
, 0x00000000);
1561 while (rcs
->current
.cdw
& 15)
1562 radeon_emit(rcs
, 0x81ff); /* nop packet */
1568 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1569 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1572 /* If the CS is not empty or overflowed.... */
1573 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1574 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1575 !debug_get_option_noop())) {
1576 struct amdgpu_cs_context
*cur
= cs
->csc
;
1579 amdgpu_ib_finalize(ws
, &cs
->main
);
1581 /* Create a fence. */
1582 amdgpu_fence_reference(&cur
->fence
, NULL
);
1583 if (cs
->next_fence
) {
1584 /* just move the reference */
1585 cur
->fence
= cs
->next_fence
;
1586 cs
->next_fence
= NULL
;
1588 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1589 cur
->ib
[IB_MAIN
].ip_type
,
1590 cur
->ib
[IB_MAIN
].ip_instance
,
1591 cur
->ib
[IB_MAIN
].ring
);
1594 amdgpu_fence_reference(fence
, cur
->fence
);
1596 amdgpu_cs_sync_flush(rcs
);
1600 * This fence must be held until the submission is queued to ensure
1601 * that the order of fence dependency updates matches the order of
1604 simple_mtx_lock(&ws
->bo_fence_lock
);
1605 amdgpu_add_fence_dependencies_bo_lists(cs
);
1607 /* Swap command streams. "cst" is going to be submitted. */
1612 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1613 amdgpu_cs_submit_ib
, NULL
);
1614 /* The submission has been queued, unlock the fence now. */
1615 simple_mtx_unlock(&ws
->bo_fence_lock
);
1617 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1618 amdgpu_cs_sync_flush(rcs
);
1619 error_code
= cur
->error_code
;
1622 amdgpu_cs_context_cleanup(cs
->csc
);
1625 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1627 cs
->main
.base
.used_gart
= 0;
1628 cs
->main
.base
.used_vram
= 0;
1630 if (cs
->ring_type
== RING_GFX
)
1632 else if (cs
->ring_type
== RING_DMA
)
1638 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1640 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1642 amdgpu_cs_sync_flush(rcs
);
1643 util_queue_fence_destroy(&cs
->flush_completed
);
1644 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1645 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1646 FREE(cs
->main
.base
.prev
);
1647 amdgpu_destroy_cs_context(&cs
->csc1
);
1648 amdgpu_destroy_cs_context(&cs
->csc2
);
1649 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1653 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1654 struct pb_buffer
*_buf
,
1655 enum radeon_bo_usage usage
)
1657 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1658 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1660 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1663 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1665 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1666 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1667 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1668 ws
->base
.cs_create
= amdgpu_cs_create
;
1669 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1670 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1671 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1672 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1673 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1674 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1675 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1676 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1677 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1678 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1679 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1680 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1681 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1682 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1683 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1684 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1685 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;