src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu && *user_fence_cpu >= rfence->fence.fence) {
  93         rfence->signalled = true;
  94         return true;
  95    }
  96    /* Now use the libdrm query. */
  97    r = amdgpu_cs_query_fence_status(&rfence->fence,
  98                                     abs_timeout,
  99                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 100                                     &expired);
 101    if (r) {
 102       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 103       return FALSE;
 104    }
 105
 106    if (expired) {
 107       /* This variable can only transition from false to true, so it doesn't
 108        * matter if threads race for it. */
 109       rfence->signalled = true;
 110       return true;
 111    }
 112    return false;
 113 }
 114
 115 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 116                                           struct pipe_fence_handle *fence,
 117                                           uint64_t timeout)
 118 {
 119    return amdgpu_fence_wait(fence, timeout, false);
 120 }
 121
 122 /* CONTEXTS */
 123
 124 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 125 {
 126    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 127    int r;
 128    struct amdgpu_bo_alloc_request alloc_buffer = {};
 129    amdgpu_bo_handle buf_handle;
 130
 131    ctx->ws = amdgpu_winsys(ws);
 132    ctx->refcount = 1;
 133
 134    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 137       FREE(ctx);
 138       return NULL;
 139    }
 140
 141    alloc_buffer.alloc_size = 4 * 1024;
 142    alloc_buffer.phys_alignment = 4 *1024;
 143    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 144
 145    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 148       amdgpu_cs_ctx_free(ctx->ctx);
 149       FREE(ctx);
 150       return NULL;
 151    }
 152
 153    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 154    if (r) {
 155       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 156       amdgpu_bo_free(buf_handle);
 157       amdgpu_cs_ctx_free(ctx->ctx);
 158       FREE(ctx);
 159       return NULL;
 160    }
 161
 162    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 163    ctx->user_fence_bo = buf_handle;
 164
 165    return (struct radeon_winsys_ctx*)ctx;
 166 }
 167
 168 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 169 {
 170    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 171 }
 172
 173 static enum pipe_reset_status
 174 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 175 {
 176    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 177    uint32_t result, hangs;
 178    int r;
 179
 180    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 181    if (r) {
 182       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 183       return PIPE_NO_RESET;
 184    }
 185
 186    switch (result) {
 187    case AMDGPU_CTX_GUILTY_RESET:
 188       return PIPE_GUILTY_CONTEXT_RESET;
 189    case AMDGPU_CTX_INNOCENT_RESET:
 190       return PIPE_INNOCENT_CONTEXT_RESET;
 191    case AMDGPU_CTX_UNKNOWN_RESET:
 192       return PIPE_UNKNOWN_CONTEXT_RESET;
 193    case AMDGPU_CTX_NO_RESET:
 194    default:
 195       return PIPE_NO_RESET;
 196    }
 197 }
 198
 199 /* COMMAND SUBMISSION */
 200
 201 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
 202                               struct amdgpu_cs_ib_info *info, unsigned ib_type)
 203 {
 204    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 205     * and there is less waiting for buffers and fences. Proof:
 206     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 207     */
 208    unsigned buffer_size, ib_size;
 209
 210    switch (ib_type) {
 211    case IB_CONST_PREAMBLE:
 212       buffer_size = 4 * 1024 * 4;
 213       ib_size = 1024 * 4;
 214    case IB_CONST:
 215       buffer_size = 512 * 1024 * 4;
 216       ib_size = 128 * 1024 * 4;
 217       break;
 218    case IB_MAIN:
 219       buffer_size = 128 * 1024 * 4;
 220       ib_size = 20 * 1024 * 4;
 221    }
 222
 223    ib->base.cdw = 0;
 224    ib->base.buf = NULL;
 225
 226    /* Allocate a new buffer for IBs if the current buffer is all used. */
 227    if (!ib->big_ib_buffer ||
 228        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 229
 230       pb_reference(&ib->big_ib_buffer, NULL);
 231       ib->ib_mapped = NULL;
 232       ib->used_ib_space = 0;
 233
 234       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 235                                             4096, true,
 236                                             RADEON_DOMAIN_GTT,
 237                                             RADEON_FLAG_CPU_ACCESS);
 238       if (!ib->big_ib_buffer)
 239          return false;
 240
 241       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 242                                      PIPE_TRANSFER_WRITE);
 243       if (!ib->ib_mapped) {
 244          pb_reference(&ib->big_ib_buffer, NULL);
 245          return false;
 246       }
 247    }
 248
 249    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 250                          ib->used_ib_space;
 251    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 252    ib->base.max_dw = ib_size / 4;
 253    return true;
 254 }
 255
 256 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 257                                       enum ring_type ring_type)
 258 {
 259    int i;
 260
 261    switch (ring_type) {
 262    case RING_DMA:
 263       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 264       break;
 265
 266    case RING_UVD:
 267       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 268       break;
 269
 270    case RING_VCE:
 271       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 272       break;
 273
 274    case RING_COMPUTE:
 275       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 276       break;
 277
 278    default:
 279    case RING_GFX:
 280       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 281       break;
 282    }
 283
 284    cs->max_num_buffers = 512;
 285    cs->buffers = (struct amdgpu_cs_buffer*)
 286                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 287    if (!cs->buffers) {
 288       return FALSE;
 289    }
 290
 291    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 292    if (!cs->handles) {
 293       FREE(cs->buffers);
 294       return FALSE;
 295    }
 296
 297    cs->flags = CALLOC(1, cs->max_num_buffers);
 298    if (!cs->flags) {
 299       FREE(cs->handles);
 300       FREE(cs->buffers);
 301       return FALSE;
 302    }
 303
 304    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 305       cs->buffer_indices_hashlist[i] = -1;
 306    }
 307    return TRUE;
 308 }
 309
 310 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 311 {
 312    unsigned i;
 313
 314    for (i = 0; i < cs->num_buffers; i++) {
 315       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 316       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 317       cs->handles[i] = NULL;
 318       cs->flags[i] = 0;
 319    }
 320
 321    cs->num_buffers = 0;
 322    cs->used_gart = 0;
 323    cs->used_vram = 0;
 324
 325    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 326       cs->buffer_indices_hashlist[i] = -1;
 327    }
 328 }
 329
 330 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 331 {
 332    amdgpu_cs_context_cleanup(cs);
 333    FREE(cs->flags);
 334    FREE(cs->buffers);
 335    FREE(cs->handles);
 336    FREE(cs->request.dependencies);
 337 }
 338
 339
 340 static struct radeon_winsys_cs *
 341 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 342                  enum ring_type ring_type,
 343                  void (*flush)(void *ctx, unsigned flags,
 344                                struct pipe_fence_handle **fence),
 345                  void *flush_ctx)
 346 {
 347    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 348    struct amdgpu_cs *cs;
 349
 350    cs = CALLOC_STRUCT(amdgpu_cs);
 351    if (!cs) {
 352       return NULL;
 353    }
 354
 355    cs->ctx = ctx;
 356    cs->flush_cs = flush;
 357    cs->flush_data = flush_ctx;
 358    cs->ring_type = ring_type;
 359
 360    if (!amdgpu_init_cs_context(cs, ring_type)) {
 361       FREE(cs);
 362       return NULL;
 363    }
 364
 365    if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
 366       amdgpu_destroy_cs_context(cs);
 367       FREE(cs);
 368       return NULL;
 369    }
 370
 371    cs->request.number_of_ibs = 1;
 372    cs->request.ibs = &cs->ib[IB_MAIN];
 373
 374    p_atomic_inc(&ctx->ws->num_cs);
 375    return &cs->main.base;
 376 }
 377
 378 static struct radeon_winsys_cs *
 379 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 380 {
 381    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 382    struct amdgpu_winsys *ws = cs->ctx->ws;
 383
 384    /* only one const IB can be added */
 385    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 386       return NULL;
 387
 388    if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
 389       return NULL;
 390
 391    cs->request.number_of_ibs = 2;
 392    cs->request.ibs = &cs->ib[IB_CONST];
 393    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 394
 395    return &cs->const_ib.base;
 396 }
 397
 398 static struct radeon_winsys_cs *
 399 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 400 {
 401    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 402    struct amdgpu_winsys *ws = cs->ctx->ws;
 403
 404    /* only one const preamble IB can be added and only when the const IB has
 405     * also been mapped */
 406    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 407        cs->const_preamble_ib.ib_mapped)
 408       return NULL;
 409
 410    if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 411                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
 412       return NULL;
 413
 414    cs->request.number_of_ibs = 3;
 415    cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE];
 416    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE;
 417
 418    return &cs->const_preamble_ib.base;
 419 }
 420
 421 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 422
 423 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 424 {
 425    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 426    int i = cs->buffer_indices_hashlist[hash];
 427
 428    /* not found or found */
 429    if (i == -1 || cs->buffers[i].bo == bo)
 430       return i;
 431
 432    /* Hash collision, look for the BO in the list of buffers linearly. */
 433    for (i = cs->num_buffers - 1; i >= 0; i--) {
 434       if (cs->buffers[i].bo == bo) {
 435          /* Put this buffer in the hash list.
 436           * This will prevent additional hash collisions if there are
 437           * several consecutive lookup_buffer calls for the same buffer.
 438           *
 439           * Example: Assuming buffers A,B,C collide in the hash list,
 440           * the following sequence of buffers:
 441           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 442           * will collide here: ^ and here:   ^,
 443           * meaning that we should get very few collisions in the end. */
 444          cs->buffer_indices_hashlist[hash] = i;
 445          return i;
 446       }
 447    }
 448    return -1;
 449 }
 450
 451 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 452                                  struct amdgpu_winsys_bo *bo,
 453                                  enum radeon_bo_usage usage,
 454                                  enum radeon_bo_domain domains,
 455                                  unsigned priority,
 456                                  enum radeon_bo_domain *added_domains)
 457 {
 458    struct amdgpu_cs_buffer *buffer;
 459    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 460    int i = -1;
 461
 462    assert(priority < 64);
 463    *added_domains = 0;
 464
 465    i = amdgpu_lookup_buffer(cs, bo);
 466
 467    if (i >= 0) {
 468       buffer = &cs->buffers[i];
 469       buffer->priority_usage |= 1llu << priority;
 470       buffer->usage |= usage;
 471       *added_domains = domains & ~buffer->domains;
 472       buffer->domains |= domains;
 473       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 474       return i;
 475    }
 476
 477    /* New buffer, check if the backing array is large enough. */
 478    if (cs->num_buffers >= cs->max_num_buffers) {
 479       uint32_t size;
 480       cs->max_num_buffers += 10;
 481
 482       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 483       cs->buffers = realloc(cs->buffers, size);
 484
 485       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 486       cs->handles = realloc(cs->handles, size);
 487
 488       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 489    }
 490
 491    /* Initialize the new buffer. */
 492    cs->buffers[cs->num_buffers].bo = NULL;
 493    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 494    cs->handles[cs->num_buffers] = bo->bo;
 495    cs->flags[cs->num_buffers] = priority / 4;
 496    p_atomic_inc(&bo->num_cs_references);
 497    buffer = &cs->buffers[cs->num_buffers];
 498    buffer->bo = bo;
 499    buffer->priority_usage = 1llu << priority;
 500    buffer->usage = usage;
 501    buffer->domains = domains;
 502
 503    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 504
 505    *added_domains = domains;
 506    return cs->num_buffers++;
 507 }
 508
 509 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 510                                     struct pb_buffer *buf,
 511                                     enum radeon_bo_usage usage,
 512                                     enum radeon_bo_domain domains,
 513                                     enum radeon_bo_priority priority)
 514 {
 515    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 516     * the buffer placement during command submission.
 517     */
 518    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 519    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 520    enum radeon_bo_domain added_domains;
 521    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 522                                      priority, &added_domains);
 523
 524    if (added_domains & RADEON_DOMAIN_GTT)
 525       cs->used_gart += bo->base.size;
 526    if (added_domains & RADEON_DOMAIN_VRAM)
 527       cs->used_vram += bo->base.size;
 528
 529    return index;
 530 }
 531
 532 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 533                                struct pb_buffer *buf)
 534 {
 535    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 536
 537    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 538 }
 539
 540 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 541 {
 542    return TRUE;
 543 }
 544
 545 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 546 {
 547    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 548    boolean status =
 549          (cs->used_gart + gtt) < cs->ctx->ws->info.gart_size * 0.7 &&
 550          (cs->used_vram + vram) < cs->ctx->ws->info.vram_size * 0.7;
 551
 552    return status;
 553 }
 554
 555 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 556                                           struct radeon_bo_list_item *list)
 557 {
 558     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 559     int i;
 560
 561     if (list) {
 562         for (i = 0; i < cs->num_buffers; i++) {
 563             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 564             list[i].vm_address = cs->buffers[i].bo->va;
 565             list[i].priority_usage = cs->buffers[i].priority_usage;
 566         }
 567     }
 568     return cs->num_buffers;
 569 }
 570
 571 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 572                                     struct pipe_fence_handle **out_fence)
 573 {
 574    struct amdgpu_winsys *ws = cs->ctx->ws;
 575    struct pipe_fence_handle *fence;
 576    int i, j, r;
 577
 578    /* Create a fence. */
 579    fence = amdgpu_fence_create(cs->ctx,
 580                                cs->request.ip_type,
 581                                cs->request.ip_instance,
 582                                cs->request.ring);
 583    if (out_fence)
 584       amdgpu_fence_reference(out_fence, fence);
 585
 586    cs->request.number_of_dependencies = 0;
 587
 588    /* Since the kernel driver doesn't synchronize execution between different
 589     * rings automatically, we have to add fence dependencies manually. */
 590    pipe_mutex_lock(ws->bo_fence_lock);
 591    for (i = 0; i < cs->num_buffers; i++) {
 592       for (j = 0; j < RING_LAST; j++) {
 593          struct amdgpu_cs_fence *dep;
 594          unsigned idx;
 595
 596          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 597          if (!bo_fence)
 598             continue;
 599
 600          if (bo_fence->ctx == cs->ctx &&
 601              bo_fence->fence.ip_type == cs->request.ip_type &&
 602              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 603              bo_fence->fence.ring == cs->request.ring)
 604             continue;
 605
 606          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 607             continue;
 608
 609          idx = cs->request.number_of_dependencies++;
 610          if (idx >= cs->max_dependencies) {
 611             unsigned size;
 612
 613             cs->max_dependencies = idx + 8;
 614             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 615             cs->request.dependencies = realloc(cs->request.dependencies, size);
 616          }
 617
 618          dep = &cs->request.dependencies[idx];
 619          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 620       }
 621    }
 622
 623    cs->request.fence_info.handle = NULL;
 624    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 625         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 626         cs->request.fence_info.offset = cs->ring_type;
 627    }
 628
 629    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 630    if (r) {
 631       if (r == -ENOMEM)
 632          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 633       else
 634          fprintf(stderr, "amdgpu: The CS has been rejected, "
 635                  "see dmesg for more information.\n");
 636
 637       amdgpu_fence_signalled(fence);
 638    } else {
 639       /* Success. */
 640       uint64_t *user_fence = NULL;
 641       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 642          user_fence = cs->ctx->user_fence_cpu_address_base +
 643                       cs->request.fence_info.offset;
 644       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 645
 646       for (i = 0; i < cs->num_buffers; i++)
 647          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
 648                                 fence);
 649    }
 650    pipe_mutex_unlock(ws->bo_fence_lock);
 651    amdgpu_fence_reference(&fence, NULL);
 652 }
 653
 654 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 655 {
 656    /* no-op */
 657 }
 658
 659 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 660 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 661
 662 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 663                             unsigned flags,
 664                             struct pipe_fence_handle **fence)
 665 {
 666    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 667    struct amdgpu_winsys *ws = cs->ctx->ws;
 668
 669    switch (cs->ring_type) {
 670    case RING_DMA:
 671       /* pad DMA ring to 8 DWs */
 672       while (rcs->cdw & 7)
 673          OUT_CS(rcs, 0x00000000); /* NOP packet */
 674       break;
 675    case RING_GFX:
 676       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 677       while (rcs->cdw & 7)
 678          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 679
 680       /* Also pad the const IB. */
 681       if (cs->const_ib.ib_mapped)
 682          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 683             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 684
 685       if (cs->const_preamble_ib.ib_mapped)
 686          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 687             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 688       break;
 689    case RING_UVD:
 690       while (rcs->cdw & 15)
 691          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 692       break;
 693    default:
 694       break;
 695    }
 696
 697    if (rcs->cdw > rcs->max_dw) {
 698       fprintf(stderr, "amdgpu: command stream overflowed\n");
 699    }
 700
 701    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 702                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 703
 704    if (cs->const_ib.ib_mapped)
 705       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 706                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 707
 708    if (cs->const_preamble_ib.ib_mapped)
 709       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 710                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 711
 712    /* If the CS is not empty or overflowed.... */
 713    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) {
 714       int r;
 715
 716       /* Use a buffer list containing all allocated buffers if requested. */
 717       if (debug_get_option_all_bos()) {
 718          struct amdgpu_winsys_bo *bo;
 719          amdgpu_bo_handle *handles;
 720          unsigned num = 0;
 721
 722          pipe_mutex_lock(ws->global_bo_list_lock);
 723
 724          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 725          if (!handles) {
 726             pipe_mutex_unlock(ws->global_bo_list_lock);
 727             goto cleanup;
 728          }
 729
 730          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 731             assert(num < ws->num_buffers);
 732             handles[num++] = bo->bo;
 733          }
 734
 735          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 736                                    handles, NULL,
 737                                    &cs->request.resources);
 738          free(handles);
 739          pipe_mutex_unlock(ws->global_bo_list_lock);
 740       } else {
 741          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 742                                    cs->handles, cs->flags,
 743                                    &cs->request.resources);
 744       }
 745
 746       if (r) {
 747          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 748          cs->request.resources = NULL;
 749          goto cleanup;
 750       }
 751
 752       cs->ib[IB_MAIN].size = cs->main.base.cdw;
 753       cs->main.used_ib_space += cs->main.base.cdw * 4;
 754
 755       if (cs->const_ib.ib_mapped) {
 756          cs->ib[IB_CONST].size = cs->const_ib.base.cdw;
 757          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 758       }
 759
 760       if (cs->const_preamble_ib.ib_mapped) {
 761          cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 762          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 763       }
 764
 765       amdgpu_cs_do_submission(cs, fence);
 766
 767       /* Cleanup. */
 768       if (cs->request.resources)
 769          amdgpu_bo_list_destroy(cs->request.resources);
 770    }
 771
 772 cleanup:
 773    amdgpu_cs_context_cleanup(cs);
 774
 775    amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
 776    if (cs->const_ib.ib_mapped)
 777       amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
 778    if (cs->const_preamble_ib.ib_mapped)
 779       amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 780                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
 781
 782    ws->num_cs_flushes++;
 783 }
 784
 785 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 786 {
 787    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 788
 789    amdgpu_destroy_cs_context(cs);
 790    p_atomic_dec(&cs->ctx->ws->num_cs);
 791    pb_reference(&cs->main.big_ib_buffer, NULL);
 792    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 793    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 794    FREE(cs);
 795 }
 796
 797 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 798                                        struct pb_buffer *_buf,
 799                                        enum radeon_bo_usage usage)
 800 {
 801    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 802    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 803
 804    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 805 }
 806
 807 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 808 {
 809    ws->base.ctx_create = amdgpu_ctx_create;
 810    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 811    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 812    ws->base.cs_create = amdgpu_cs_create;
 813    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 814    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 815    ws->base.cs_destroy = amdgpu_cs_destroy;
 816    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 817    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 818    ws->base.cs_validate = amdgpu_cs_validate;
 819    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 820    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 821    ws->base.cs_flush = amdgpu_cs_flush;
 822    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 823    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 824    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 825    ws->base.fence_reference = amdgpu_fence_reference;
 826 }