src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu && *user_fence_cpu >= rfence->fence.fence) {
  93         rfence->signalled = true;
  94         return true;
  95    }
  96    /* Now use the libdrm query. */
  97    r = amdgpu_cs_query_fence_status(&rfence->fence,
  98                                     abs_timeout,
  99                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 100                                     &expired);
 101    if (r) {
 102       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 103       return FALSE;
 104    }
 105
 106    if (expired) {
 107       /* This variable can only transition from false to true, so it doesn't
 108        * matter if threads race for it. */
 109       rfence->signalled = true;
 110       return true;
 111    }
 112    return false;
 113 }
 114
 115 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 116                                           struct pipe_fence_handle *fence,
 117                                           uint64_t timeout)
 118 {
 119    return amdgpu_fence_wait(fence, timeout, false);
 120 }
 121
 122 /* CONTEXTS */
 123
 124 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 125 {
 126    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 127    int r;
 128    struct amdgpu_bo_alloc_request alloc_buffer = {};
 129    amdgpu_bo_handle buf_handle;
 130
 131    ctx->ws = amdgpu_winsys(ws);
 132    ctx->refcount = 1;
 133
 134    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 137       FREE(ctx);
 138       return NULL;
 139    }
 140
 141    alloc_buffer.alloc_size = 4 * 1024;
 142    alloc_buffer.phys_alignment = 4 *1024;
 143    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 144
 145    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 148       amdgpu_cs_ctx_free(ctx->ctx);
 149       FREE(ctx);
 150       return NULL;
 151    }
 152
 153    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 154    if (r) {
 155       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 156       amdgpu_bo_free(buf_handle);
 157       amdgpu_cs_ctx_free(ctx->ctx);
 158       FREE(ctx);
 159       return NULL;
 160    }
 161
 162    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 163    ctx->user_fence_bo = buf_handle;
 164
 165    return (struct radeon_winsys_ctx*)ctx;
 166 }
 167
 168 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 169 {
 170    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 171 }
 172
 173 static enum pipe_reset_status
 174 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 175 {
 176    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 177    uint32_t result, hangs;
 178    int r;
 179
 180    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 181    if (r) {
 182       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 183       return PIPE_NO_RESET;
 184    }
 185
 186    switch (result) {
 187    case AMDGPU_CTX_GUILTY_RESET:
 188       return PIPE_GUILTY_CONTEXT_RESET;
 189    case AMDGPU_CTX_INNOCENT_RESET:
 190       return PIPE_INNOCENT_CONTEXT_RESET;
 191    case AMDGPU_CTX_UNKNOWN_RESET:
 192       return PIPE_UNKNOWN_CONTEXT_RESET;
 193    case AMDGPU_CTX_NO_RESET:
 194    default:
 195       return PIPE_NO_RESET;
 196    }
 197 }
 198
 199 /* COMMAND SUBMISSION */
 200
 201 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
 202                               struct amdgpu_cs_ib_info *info)
 203 {
 204    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 205     * and there is less waiting for buffers and fences. Proof:
 206     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 207     */
 208    const unsigned buffer_size = 128 * 1024 * 4;
 209    const unsigned ib_size = 20 * 1024 * 4;
 210
 211    ib->base.cdw = 0;
 212    ib->base.buf = NULL;
 213
 214    /* Allocate a new buffer for IBs if the current buffer is all used. */
 215    if (!ib->big_ib_buffer ||
 216        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 217
 218       pb_reference(&ib->big_ib_buffer, NULL);
 219       ib->ib_mapped = NULL;
 220       ib->used_ib_space = 0;
 221
 222       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 223                                             4096, true,
 224                                             RADEON_DOMAIN_GTT,
 225                                             RADEON_FLAG_CPU_ACCESS);
 226       if (!ib->big_ib_buffer)
 227          return false;
 228
 229       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 230                                      PIPE_TRANSFER_WRITE);
 231       if (!ib->ib_mapped) {
 232          pb_reference(&ib->big_ib_buffer, NULL);
 233          return false;
 234       }
 235    }
 236
 237    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 238                          ib->used_ib_space;
 239    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 240    ib->base.max_dw = ib_size / 4;
 241    return true;
 242 }
 243
 244 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 245                                       enum ring_type ring_type)
 246 {
 247    int i;
 248
 249    switch (ring_type) {
 250    case RING_DMA:
 251       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 252       break;
 253
 254    case RING_UVD:
 255       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 256       break;
 257
 258    case RING_VCE:
 259       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 260       break;
 261
 262    case RING_COMPUTE:
 263       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 264       break;
 265
 266    default:
 267    case RING_GFX:
 268       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 269       break;
 270    }
 271
 272    cs->max_num_buffers = 512;
 273    cs->buffers = (struct amdgpu_cs_buffer*)
 274                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 275    if (!cs->buffers) {
 276       return FALSE;
 277    }
 278
 279    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 280    if (!cs->handles) {
 281       FREE(cs->buffers);
 282       return FALSE;
 283    }
 284
 285    cs->flags = CALLOC(1, cs->max_num_buffers);
 286    if (!cs->flags) {
 287       FREE(cs->handles);
 288       FREE(cs->buffers);
 289       return FALSE;
 290    }
 291
 292    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 293       cs->buffer_indices_hashlist[i] = -1;
 294    }
 295    return TRUE;
 296 }
 297
 298 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 299 {
 300    unsigned i;
 301
 302    for (i = 0; i < cs->num_buffers; i++) {
 303       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 304       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 305       cs->handles[i] = NULL;
 306       cs->flags[i] = 0;
 307    }
 308
 309    cs->num_buffers = 0;
 310    cs->used_gart = 0;
 311    cs->used_vram = 0;
 312
 313    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 314       cs->buffer_indices_hashlist[i] = -1;
 315    }
 316 }
 317
 318 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 319 {
 320    amdgpu_cs_context_cleanup(cs);
 321    FREE(cs->flags);
 322    FREE(cs->buffers);
 323    FREE(cs->handles);
 324    FREE(cs->request.dependencies);
 325 }
 326
 327
 328 static struct radeon_winsys_cs *
 329 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 330                  enum ring_type ring_type,
 331                  void (*flush)(void *ctx, unsigned flags,
 332                                struct pipe_fence_handle **fence),
 333                  void *flush_ctx)
 334 {
 335    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 336    struct amdgpu_cs *cs;
 337
 338    cs = CALLOC_STRUCT(amdgpu_cs);
 339    if (!cs) {
 340       return NULL;
 341    }
 342
 343    cs->ctx = ctx;
 344    cs->flush_cs = flush;
 345    cs->flush_data = flush_ctx;
 346    cs->ring_type = ring_type;
 347
 348    if (!amdgpu_init_cs_context(cs, ring_type)) {
 349       FREE(cs);
 350       return NULL;
 351    }
 352
 353    if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN])) {
 354       amdgpu_destroy_cs_context(cs);
 355       FREE(cs);
 356       return NULL;
 357    }
 358
 359    cs->request.number_of_ibs = 1;
 360    cs->request.ibs = &cs->ib[IB_MAIN];
 361
 362    p_atomic_inc(&ctx->ws->num_cs);
 363    return &cs->main.base;
 364 }
 365
 366 static struct radeon_winsys_cs *
 367 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 368 {
 369    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 370    struct amdgpu_winsys *ws = cs->ctx->ws;
 371
 372    /* only one const IB can be added */
 373    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 374       return NULL;
 375
 376    if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]))
 377       return NULL;
 378
 379    cs->request.number_of_ibs = 2;
 380    cs->request.ibs = &cs->ib[IB_CONST];
 381    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 382
 383    return &cs->const_ib.base;
 384 }
 385
 386 static struct radeon_winsys_cs *
 387 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 388 {
 389    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 390    struct amdgpu_winsys *ws = cs->ctx->ws;
 391
 392    /* only one const preamble IB can be added and only when the const IB has
 393     * also been mapped */
 394    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 395        cs->const_preamble_ib.ib_mapped)
 396       return NULL;
 397
 398    if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 399                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
 400       return NULL;
 401
 402    cs->request.number_of_ibs = 3;
 403    cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE];
 404    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE;
 405
 406    return &cs->const_preamble_ib.base;
 407 }
 408
 409 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 410
 411 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 412 {
 413    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 414    int i = cs->buffer_indices_hashlist[hash];
 415
 416    /* not found or found */
 417    if (i == -1 || cs->buffers[i].bo == bo)
 418       return i;
 419
 420    /* Hash collision, look for the BO in the list of buffers linearly. */
 421    for (i = cs->num_buffers - 1; i >= 0; i--) {
 422       if (cs->buffers[i].bo == bo) {
 423          /* Put this buffer in the hash list.
 424           * This will prevent additional hash collisions if there are
 425           * several consecutive lookup_buffer calls for the same buffer.
 426           *
 427           * Example: Assuming buffers A,B,C collide in the hash list,
 428           * the following sequence of buffers:
 429           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 430           * will collide here: ^ and here:   ^,
 431           * meaning that we should get very few collisions in the end. */
 432          cs->buffer_indices_hashlist[hash] = i;
 433          return i;
 434       }
 435    }
 436    return -1;
 437 }
 438
 439 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 440                                  struct amdgpu_winsys_bo *bo,
 441                                  enum radeon_bo_usage usage,
 442                                  enum radeon_bo_domain domains,
 443                                  unsigned priority,
 444                                  enum radeon_bo_domain *added_domains)
 445 {
 446    struct amdgpu_cs_buffer *buffer;
 447    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 448    int i = -1;
 449
 450    assert(priority < 64);
 451    *added_domains = 0;
 452
 453    i = amdgpu_lookup_buffer(cs, bo);
 454
 455    if (i >= 0) {
 456       buffer = &cs->buffers[i];
 457       buffer->priority_usage |= 1llu << priority;
 458       buffer->usage |= usage;
 459       *added_domains = domains & ~buffer->domains;
 460       buffer->domains |= domains;
 461       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 462       return i;
 463    }
 464
 465    /* New buffer, check if the backing array is large enough. */
 466    if (cs->num_buffers >= cs->max_num_buffers) {
 467       uint32_t size;
 468       cs->max_num_buffers += 10;
 469
 470       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 471       cs->buffers = realloc(cs->buffers, size);
 472
 473       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 474       cs->handles = realloc(cs->handles, size);
 475
 476       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 477    }
 478
 479    /* Initialize the new buffer. */
 480    cs->buffers[cs->num_buffers].bo = NULL;
 481    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 482    cs->handles[cs->num_buffers] = bo->bo;
 483    cs->flags[cs->num_buffers] = priority / 4;
 484    p_atomic_inc(&bo->num_cs_references);
 485    buffer = &cs->buffers[cs->num_buffers];
 486    buffer->bo = bo;
 487    buffer->priority_usage = 1llu << priority;
 488    buffer->usage = usage;
 489    buffer->domains = domains;
 490
 491    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 492
 493    *added_domains = domains;
 494    return cs->num_buffers++;
 495 }
 496
 497 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 498                                     struct pb_buffer *buf,
 499                                     enum radeon_bo_usage usage,
 500                                     enum radeon_bo_domain domains,
 501                                     enum radeon_bo_priority priority)
 502 {
 503    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 504     * the buffer placement during command submission.
 505     */
 506    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 507    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 508    enum radeon_bo_domain added_domains;
 509    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 510                                      priority, &added_domains);
 511
 512    if (added_domains & RADEON_DOMAIN_GTT)
 513       cs->used_gart += bo->base.size;
 514    if (added_domains & RADEON_DOMAIN_VRAM)
 515       cs->used_vram += bo->base.size;
 516
 517    return index;
 518 }
 519
 520 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 521                                struct pb_buffer *buf)
 522 {
 523    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 524
 525    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 526 }
 527
 528 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 529 {
 530    return TRUE;
 531 }
 532
 533 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 534 {
 535    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 536    boolean status =
 537          (cs->used_gart + gtt) < cs->ctx->ws->info.gart_size * 0.7 &&
 538          (cs->used_vram + vram) < cs->ctx->ws->info.vram_size * 0.7;
 539
 540    return status;
 541 }
 542
 543 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 544                                           struct radeon_bo_list_item *list)
 545 {
 546     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 547     int i;
 548
 549     if (list) {
 550         for (i = 0; i < cs->num_buffers; i++) {
 551             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 552             list[i].vm_address = cs->buffers[i].bo->va;
 553             list[i].priority_usage = cs->buffers[i].priority_usage;
 554         }
 555     }
 556     return cs->num_buffers;
 557 }
 558
 559 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 560                                     struct pipe_fence_handle **out_fence)
 561 {
 562    struct amdgpu_winsys *ws = cs->ctx->ws;
 563    struct pipe_fence_handle *fence;
 564    int i, j, r;
 565
 566    /* Create a fence. */
 567    fence = amdgpu_fence_create(cs->ctx,
 568                                cs->request.ip_type,
 569                                cs->request.ip_instance,
 570                                cs->request.ring);
 571    if (out_fence)
 572       amdgpu_fence_reference(out_fence, fence);
 573
 574    cs->request.number_of_dependencies = 0;
 575
 576    /* Since the kernel driver doesn't synchronize execution between different
 577     * rings automatically, we have to add fence dependencies manually. */
 578    pipe_mutex_lock(ws->bo_fence_lock);
 579    for (i = 0; i < cs->num_buffers; i++) {
 580       for (j = 0; j < RING_LAST; j++) {
 581          struct amdgpu_cs_fence *dep;
 582          unsigned idx;
 583
 584          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 585          if (!bo_fence)
 586             continue;
 587
 588          if (bo_fence->ctx == cs->ctx &&
 589              bo_fence->fence.ip_type == cs->request.ip_type &&
 590              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 591              bo_fence->fence.ring == cs->request.ring)
 592             continue;
 593
 594          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 595             continue;
 596
 597          idx = cs->request.number_of_dependencies++;
 598          if (idx >= cs->max_dependencies) {
 599             unsigned size;
 600
 601             cs->max_dependencies = idx + 8;
 602             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 603             cs->request.dependencies = realloc(cs->request.dependencies, size);
 604          }
 605
 606          dep = &cs->request.dependencies[idx];
 607          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 608       }
 609    }
 610
 611    cs->request.fence_info.handle = NULL;
 612    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 613         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 614         cs->request.fence_info.offset = cs->ring_type;
 615    }
 616
 617    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 618    if (r) {
 619       if (r == -ENOMEM)
 620          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 621       else
 622          fprintf(stderr, "amdgpu: The CS has been rejected, "
 623                  "see dmesg for more information.\n");
 624
 625       amdgpu_fence_signalled(fence);
 626    } else {
 627       /* Success. */
 628       uint64_t *user_fence = NULL;
 629       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 630          user_fence = cs->ctx->user_fence_cpu_address_base +
 631                       cs->request.fence_info.offset;
 632       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 633
 634       for (i = 0; i < cs->num_buffers; i++)
 635          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
 636                                 fence);
 637    }
 638    pipe_mutex_unlock(ws->bo_fence_lock);
 639    amdgpu_fence_reference(&fence, NULL);
 640 }
 641
 642 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 643 {
 644    /* no-op */
 645 }
 646
 647 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 648 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 649
 650 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 651                             unsigned flags,
 652                             struct pipe_fence_handle **fence)
 653 {
 654    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 655    struct amdgpu_winsys *ws = cs->ctx->ws;
 656
 657    switch (cs->ring_type) {
 658    case RING_DMA:
 659       /* pad DMA ring to 8 DWs */
 660       while (rcs->cdw & 7)
 661          OUT_CS(rcs, 0x00000000); /* NOP packet */
 662       break;
 663    case RING_GFX:
 664       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 665       while (rcs->cdw & 7)
 666          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 667
 668       /* Also pad the const IB. */
 669       if (cs->const_ib.ib_mapped)
 670          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 671             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 672
 673       if (cs->const_preamble_ib.ib_mapped)
 674          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 675             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 676       break;
 677    case RING_UVD:
 678       while (rcs->cdw & 15)
 679          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 680       break;
 681    default:
 682       break;
 683    }
 684
 685    if (rcs->cdw > rcs->max_dw) {
 686       fprintf(stderr, "amdgpu: command stream overflowed\n");
 687    }
 688
 689    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 690                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 691
 692    if (cs->const_ib.ib_mapped)
 693       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 694                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 695
 696    if (cs->const_preamble_ib.ib_mapped)
 697       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 698                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 699
 700    /* If the CS is not empty or overflowed.... */
 701    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) {
 702       int r;
 703
 704       /* Use a buffer list containing all allocated buffers if requested. */
 705       if (debug_get_option_all_bos()) {
 706          struct amdgpu_winsys_bo *bo;
 707          amdgpu_bo_handle *handles;
 708          unsigned num = 0;
 709
 710          pipe_mutex_lock(ws->global_bo_list_lock);
 711
 712          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 713          if (!handles) {
 714             pipe_mutex_unlock(ws->global_bo_list_lock);
 715             goto cleanup;
 716          }
 717
 718          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 719             assert(num < ws->num_buffers);
 720             handles[num++] = bo->bo;
 721          }
 722
 723          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 724                                    handles, NULL,
 725                                    &cs->request.resources);
 726          free(handles);
 727          pipe_mutex_unlock(ws->global_bo_list_lock);
 728       } else {
 729          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 730                                    cs->handles, cs->flags,
 731                                    &cs->request.resources);
 732       }
 733
 734       if (r) {
 735          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 736          cs->request.resources = NULL;
 737          goto cleanup;
 738       }
 739
 740       cs->ib[IB_MAIN].size = cs->main.base.cdw;
 741       cs->main.used_ib_space += cs->main.base.cdw * 4;
 742
 743       if (cs->const_ib.ib_mapped) {
 744          cs->ib[IB_CONST].size = cs->const_ib.base.cdw;
 745          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 746       }
 747
 748       if (cs->const_preamble_ib.ib_mapped) {
 749          cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 750          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 751       }
 752
 753       amdgpu_cs_do_submission(cs, fence);
 754
 755       /* Cleanup. */
 756       if (cs->request.resources)
 757          amdgpu_bo_list_destroy(cs->request.resources);
 758    }
 759
 760 cleanup:
 761    amdgpu_cs_context_cleanup(cs);
 762
 763    amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN]);
 764    if (cs->const_ib.ib_mapped)
 765       amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]);
 766    if (cs->const_preamble_ib.ib_mapped)
 767       amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 768                                  &cs->ib[IB_CONST_PREAMBLE]);
 769
 770    ws->num_cs_flushes++;
 771 }
 772
 773 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 774 {
 775    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 776
 777    amdgpu_destroy_cs_context(cs);
 778    p_atomic_dec(&cs->ctx->ws->num_cs);
 779    pb_reference(&cs->main.big_ib_buffer, NULL);
 780    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 781    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 782    FREE(cs);
 783 }
 784
 785 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 786                                        struct pb_buffer *_buf,
 787                                        enum radeon_bo_usage usage)
 788 {
 789    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 790    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 791
 792    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 793 }
 794
 795 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 796 {
 797    ws->base.ctx_create = amdgpu_ctx_create;
 798    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 799    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 800    ws->base.cs_create = amdgpu_cs_create;
 801    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 802    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 803    ws->base.cs_destroy = amdgpu_cs_destroy;
 804    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 805    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 806    ws->base.cs_validate = amdgpu_cs_validate;
 807    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 808    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 809    ws->base.cs_flush = amdgpu_cs_flush;
 810    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 811    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 812    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 813    ws->base.fence_reference = amdgpu_fence_reference;
 814 }