src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    fence->submission_in_progress = true;
  54    p_atomic_inc(&ctx->refcount);
  55    return (struct pipe_fence_handle *)fence;
  56 }
  57
  58 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  59                                 struct amdgpu_cs_request* request,
  60                                 uint64_t *user_fence_cpu_address)
  61 {
  62    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  63
  64    rfence->fence.fence = request->seq_no;
  65    rfence->user_fence_cpu_address = user_fence_cpu_address;
  66    rfence->submission_in_progress = false;
  67 }
  68
  69 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  70 {
  71    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  72
  73    rfence->signalled = true;
  74    rfence->submission_in_progress = false;
  75 }
  76
  77 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  78                        bool absolute)
  79 {
  80    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  81    uint32_t expired;
  82    int64_t abs_timeout;
  83    uint64_t *user_fence_cpu;
  84    int r;
  85
  86    if (rfence->signalled)
  87       return true;
  88
  89    if (absolute)
  90       abs_timeout = timeout;
  91    else
  92       abs_timeout = os_time_get_absolute_timeout(timeout);
  93
  94    /* The fence might not have a number assigned if its IB is being
  95     * submitted in the other thread right now. Wait until the submission
  96     * is done. */
  97    if (!os_wait_until_zero_abs_timeout(&rfence->submission_in_progress,
  98                                        abs_timeout))
  99       return false;
 100
 101    user_fence_cpu = rfence->user_fence_cpu_address;
 102    if (user_fence_cpu) {
 103       if (*user_fence_cpu >= rfence->fence.fence) {
 104          rfence->signalled = true;
 105          return true;
 106       }
 107
 108       /* No timeout, just query: no need for the ioctl. */
 109       if (!absolute && !timeout)
 110          return false;
 111    }
 112
 113    /* Now use the libdrm query. */
 114    r = amdgpu_cs_query_fence_status(&rfence->fence,
 115                                     abs_timeout,
 116                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 117                                     &expired);
 118    if (r) {
 119       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 120       return FALSE;
 121    }
 122
 123    if (expired) {
 124       /* This variable can only transition from false to true, so it doesn't
 125        * matter if threads race for it. */
 126       rfence->signalled = true;
 127       return true;
 128    }
 129    return false;
 130 }
 131
 132 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 133                                           struct pipe_fence_handle *fence,
 134                                           uint64_t timeout)
 135 {
 136    return amdgpu_fence_wait(fence, timeout, false);
 137 }
 138
 139 /* CONTEXTS */
 140
 141 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 142 {
 143    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 144    int r;
 145    struct amdgpu_bo_alloc_request alloc_buffer = {};
 146    amdgpu_bo_handle buf_handle;
 147
 148    if (!ctx)
 149       return NULL;
 150
 151    ctx->ws = amdgpu_winsys(ws);
 152    ctx->refcount = 1;
 153
 154    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 155    if (r) {
 156       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 157       goto error_create;
 158    }
 159
 160    alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
 161    alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
 162    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 163
 164    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 165    if (r) {
 166       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 167       goto error_user_fence_alloc;
 168    }
 169
 170    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 171    if (r) {
 172       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 173       goto error_user_fence_map;
 174    }
 175
 176    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 177    ctx->user_fence_bo = buf_handle;
 178
 179    return (struct radeon_winsys_ctx*)ctx;
 180
 181 error_user_fence_map:
 182    amdgpu_bo_free(buf_handle);
 183 error_user_fence_alloc:
 184    amdgpu_cs_ctx_free(ctx->ctx);
 185 error_create:
 186    FREE(ctx);
 187    return NULL;
 188 }
 189
 190 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 191 {
 192    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 193 }
 194
 195 static enum pipe_reset_status
 196 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 197 {
 198    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 199    uint32_t result, hangs;
 200    int r;
 201
 202    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 203    if (r) {
 204       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 205       return PIPE_NO_RESET;
 206    }
 207
 208    switch (result) {
 209    case AMDGPU_CTX_GUILTY_RESET:
 210       return PIPE_GUILTY_CONTEXT_RESET;
 211    case AMDGPU_CTX_INNOCENT_RESET:
 212       return PIPE_INNOCENT_CONTEXT_RESET;
 213    case AMDGPU_CTX_UNKNOWN_RESET:
 214       return PIPE_UNKNOWN_CONTEXT_RESET;
 215    case AMDGPU_CTX_NO_RESET:
 216    default:
 217       return PIPE_NO_RESET;
 218    }
 219 }
 220
 221 /* COMMAND SUBMISSION */
 222
 223 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
 224 {
 225    return cs->request.ip_type != AMDGPU_HW_IP_UVD &&
 226           cs->request.ip_type != AMDGPU_HW_IP_VCE;
 227 }
 228
 229 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo)
 230 {
 231    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 232    int i = cs->buffer_indices_hashlist[hash];
 233
 234    /* not found or found */
 235    if (i == -1 || cs->buffers[i].bo == bo)
 236       return i;
 237
 238    /* Hash collision, look for the BO in the list of buffers linearly. */
 239    for (i = cs->num_buffers - 1; i >= 0; i--) {
 240       if (cs->buffers[i].bo == bo) {
 241          /* Put this buffer in the hash list.
 242           * This will prevent additional hash collisions if there are
 243           * several consecutive lookup_buffer calls for the same buffer.
 244           *
 245           * Example: Assuming buffers A,B,C collide in the hash list,
 246           * the following sequence of buffers:
 247           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 248           * will collide here: ^ and here:   ^,
 249           * meaning that we should get very few collisions in the end. */
 250          cs->buffer_indices_hashlist[hash] = i;
 251          return i;
 252       }
 253    }
 254    return -1;
 255 }
 256
 257 static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
 258                                  struct amdgpu_winsys_bo *bo,
 259                                  enum radeon_bo_usage usage,
 260                                  enum radeon_bo_domain domains,
 261                                  unsigned priority,
 262                                  enum radeon_bo_domain *added_domains)
 263 {
 264    struct amdgpu_cs_context *cs = acs->csc;
 265    struct amdgpu_cs_buffer *buffer;
 266    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 267    int i = -1;
 268
 269    assert(priority < 64);
 270    *added_domains = 0;
 271
 272    i = amdgpu_lookup_buffer(cs, bo);
 273
 274    if (i >= 0) {
 275       buffer = &cs->buffers[i];
 276       buffer->priority_usage |= 1llu << priority;
 277       buffer->usage |= usage;
 278       *added_domains = domains & ~buffer->domains;
 279       buffer->domains |= domains;
 280       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 281       return i;
 282    }
 283
 284    /* New buffer, check if the backing array is large enough. */
 285    if (cs->num_buffers >= cs->max_num_buffers) {
 286       uint32_t size;
 287       cs->max_num_buffers += 10;
 288
 289       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 290       cs->buffers = realloc(cs->buffers, size);
 291
 292       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 293       cs->handles = realloc(cs->handles, size);
 294
 295       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 296    }
 297
 298    /* Initialize the new buffer. */
 299    cs->buffers[cs->num_buffers].bo = NULL;
 300    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 301    cs->handles[cs->num_buffers] = bo->bo;
 302    cs->flags[cs->num_buffers] = priority / 4;
 303    p_atomic_inc(&bo->num_cs_references);
 304    buffer = &cs->buffers[cs->num_buffers];
 305    buffer->bo = bo;
 306    buffer->priority_usage = 1llu << priority;
 307    buffer->usage = usage;
 308    buffer->domains = domains;
 309
 310    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 311
 312    *added_domains = domains;
 313    return cs->num_buffers++;
 314 }
 315
 316 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 317                                     struct pb_buffer *buf,
 318                                     enum radeon_bo_usage usage,
 319                                     enum radeon_bo_domain domains,
 320                                     enum radeon_bo_priority priority)
 321 {
 322    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 323     * the buffer placement during command submission.
 324     */
 325    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 326    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 327    enum radeon_bo_domain added_domains;
 328    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 329                                      priority, &added_domains);
 330
 331    if (added_domains & RADEON_DOMAIN_VRAM)
 332       cs->csc->used_vram += bo->base.size;
 333    else if (added_domains & RADEON_DOMAIN_GTT)
 334       cs->csc->used_gart += bo->base.size;
 335
 336    return index;
 337 }
 338
 339 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
 340 {
 341    struct pb_buffer *pb;
 342    uint8_t *mapped;
 343    unsigned buffer_size;
 344
 345    /* Always create a buffer that is 4 times larger than the maximum seen IB
 346     * size, aligned to a power of two. Limit to 512k dwords, which is the
 347     * largest power of two that fits into the size field of the INDIRECT_BUFFER
 348     * packet.
 349     */
 350    buffer_size = 4 * MIN2(util_next_power_of_two(4 * ib->max_ib_size),
 351                           512 * 1024);
 352
 353    switch (ib->ib_type) {
 354    case IB_CONST_PREAMBLE:
 355       buffer_size = MAX2(buffer_size, 4 * 1024);
 356       break;
 357    case IB_CONST:
 358       buffer_size = MAX2(buffer_size, 16 * 1024 * 4);
 359       break;
 360    case IB_MAIN:
 361       buffer_size = MAX2(buffer_size, 8 * 1024 * 4);
 362       break;
 363    default:
 364       unreachable("unhandled IB type");
 365    }
 366
 367    pb = ws->base.buffer_create(&ws->base, buffer_size,
 368                                ws->info.gart_page_size,
 369                                RADEON_DOMAIN_GTT,
 370                                RADEON_FLAG_CPU_ACCESS);
 371    if (!pb)
 372       return false;
 373
 374    mapped = ws->base.buffer_map(pb, NULL, PIPE_TRANSFER_WRITE);
 375    if (!mapped) {
 376       pb_reference(&pb, NULL);
 377       return false;
 378    }
 379
 380    pb_reference(&ib->big_ib_buffer, pb);
 381    pb_reference(&pb, NULL);
 382
 383    ib->ib_mapped = mapped;
 384    ib->used_ib_space = 0;
 385
 386    return true;
 387 }
 388
 389 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
 390 {
 391    switch (ib_type) {
 392    case IB_MAIN:
 393       /* Smaller submits means the GPU gets busy sooner and there is less
 394        * waiting for buffers and fences. Proof:
 395        *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 396        */
 397       return 20 * 1024;
 398    case IB_CONST_PREAMBLE:
 399    case IB_CONST:
 400       /* There isn't really any reason to limit CE IB size beyond the natural
 401        * limit implied by the main IB, except perhaps GTT size. Just return
 402        * an extremely large value that we never get anywhere close to.
 403        */
 404       return 16 * 1024 * 1024;
 405    default:
 406       unreachable("bad ib_type");
 407    }
 408 }
 409
 410 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
 411                               enum ib_type ib_type)
 412 {
 413    struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
 414    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 415     * and there is less waiting for buffers and fences. Proof:
 416     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 417     */
 418    struct amdgpu_ib *ib = NULL;
 419    struct amdgpu_cs_ib_info *info = &cs->csc->ib[ib_type];
 420    unsigned ib_size = 0;
 421
 422    switch (ib_type) {
 423    case IB_CONST_PREAMBLE:
 424       ib = &cs->const_preamble_ib;
 425       ib_size = 256 * 4;
 426       break;
 427    case IB_CONST:
 428       ib = &cs->const_ib;
 429       ib_size = 8 * 1024 * 4;
 430       break;
 431    case IB_MAIN:
 432       ib = &cs->main;
 433       ib_size = 4 * 1024 * 4;
 434       break;
 435    default:
 436       unreachable("unhandled IB type");
 437    }
 438
 439    ib_size = MAX2(ib_size,
 440                   4 * MIN2(util_next_power_of_two(ib->max_ib_size),
 441                            amdgpu_ib_max_submit_dwords(ib_type)));
 442
 443    ib->base.cdw = 0;
 444    ib->base.buf = NULL;
 445
 446    /* Allocate a new buffer for IBs if the current buffer is all used. */
 447    if (!ib->big_ib_buffer ||
 448        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 449       if (!amdgpu_ib_new_buffer(aws, ib))
 450          return false;
 451    }
 452
 453    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 454                          ib->used_ib_space;
 455    amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
 456                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 457
 458    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 459
 460    ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
 461    ib->base.max_dw = ib_size / 4;
 462    return true;
 463 }
 464
 465 static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
 466                                       enum ring_type ring_type)
 467 {
 468    int i;
 469
 470    switch (ring_type) {
 471    case RING_DMA:
 472       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 473       break;
 474
 475    case RING_UVD:
 476       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 477       break;
 478
 479    case RING_VCE:
 480       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 481       break;
 482
 483    case RING_COMPUTE:
 484       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 485       break;
 486
 487    default:
 488    case RING_GFX:
 489       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 490       break;
 491    }
 492
 493    cs->max_num_buffers = 512;
 494    cs->buffers = (struct amdgpu_cs_buffer*)
 495                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 496    if (!cs->buffers) {
 497       return FALSE;
 498    }
 499
 500    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 501    if (!cs->handles) {
 502       FREE(cs->buffers);
 503       return FALSE;
 504    }
 505
 506    cs->flags = CALLOC(1, cs->max_num_buffers);
 507    if (!cs->flags) {
 508       FREE(cs->handles);
 509       FREE(cs->buffers);
 510       return FALSE;
 511    }
 512
 513    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 514       cs->buffer_indices_hashlist[i] = -1;
 515    }
 516
 517    cs->request.number_of_ibs = 1;
 518    cs->request.ibs = &cs->ib[IB_MAIN];
 519
 520    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 521    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE |
 522                                      AMDGPU_IB_FLAG_PREAMBLE;
 523
 524    return TRUE;
 525 }
 526
 527 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs)
 528 {
 529    unsigned i;
 530
 531    for (i = 0; i < cs->num_buffers; i++) {
 532       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 533       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 534       cs->handles[i] = NULL;
 535       cs->flags[i] = 0;
 536    }
 537
 538    cs->num_buffers = 0;
 539    cs->used_gart = 0;
 540    cs->used_vram = 0;
 541    amdgpu_fence_reference(&cs->fence, NULL);
 542
 543    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 544       cs->buffer_indices_hashlist[i] = -1;
 545    }
 546 }
 547
 548 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs)
 549 {
 550    amdgpu_cs_context_cleanup(cs);
 551    FREE(cs->flags);
 552    FREE(cs->buffers);
 553    FREE(cs->handles);
 554    FREE(cs->request.dependencies);
 555 }
 556
 557
 558 static struct radeon_winsys_cs *
 559 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 560                  enum ring_type ring_type,
 561                  void (*flush)(void *ctx, unsigned flags,
 562                                struct pipe_fence_handle **fence),
 563                  void *flush_ctx)
 564 {
 565    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 566    struct amdgpu_cs *cs;
 567
 568    cs = CALLOC_STRUCT(amdgpu_cs);
 569    if (!cs) {
 570       return NULL;
 571    }
 572
 573    pipe_semaphore_init(&cs->flush_completed, 1);
 574
 575    cs->ctx = ctx;
 576    cs->flush_cs = flush;
 577    cs->flush_data = flush_ctx;
 578    cs->ring_type = ring_type;
 579
 580    cs->main.ib_type = IB_MAIN;
 581    cs->const_ib.ib_type = IB_CONST;
 582    cs->const_preamble_ib.ib_type = IB_CONST_PREAMBLE;
 583
 584    if (!amdgpu_init_cs_context(&cs->csc1, ring_type)) {
 585       FREE(cs);
 586       return NULL;
 587    }
 588
 589    if (!amdgpu_init_cs_context(&cs->csc2, ring_type)) {
 590       amdgpu_destroy_cs_context(&cs->csc1);
 591       FREE(cs);
 592       return NULL;
 593    }
 594
 595    /* Set the first submission context as current. */
 596    cs->csc = &cs->csc1;
 597    cs->cst = &cs->csc2;
 598
 599    if (!amdgpu_get_new_ib(&ctx->ws->base, cs, IB_MAIN)) {
 600       amdgpu_destroy_cs_context(&cs->csc2);
 601       amdgpu_destroy_cs_context(&cs->csc1);
 602       FREE(cs);
 603       return NULL;
 604    }
 605
 606    p_atomic_inc(&ctx->ws->num_cs);
 607    return &cs->main.base;
 608 }
 609
 610 static struct radeon_winsys_cs *
 611 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 612 {
 613    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 614    struct amdgpu_winsys *ws = cs->ctx->ws;
 615
 616    /* only one const IB can be added */
 617    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 618       return NULL;
 619
 620    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST))
 621       return NULL;
 622
 623    cs->csc->request.number_of_ibs = 2;
 624    cs->csc->request.ibs = &cs->csc->ib[IB_CONST];
 625
 626    cs->cst->request.number_of_ibs = 2;
 627    cs->cst->request.ibs = &cs->cst->ib[IB_CONST];
 628
 629    return &cs->const_ib.base;
 630 }
 631
 632 static struct radeon_winsys_cs *
 633 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 634 {
 635    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 636    struct amdgpu_winsys *ws = cs->ctx->ws;
 637
 638    /* only one const preamble IB can be added and only when the const IB has
 639     * also been mapped */
 640    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 641        cs->const_preamble_ib.ib_mapped)
 642       return NULL;
 643
 644    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE))
 645       return NULL;
 646
 647    cs->csc->request.number_of_ibs = 3;
 648    cs->csc->request.ibs = &cs->csc->ib[IB_CONST_PREAMBLE];
 649
 650    cs->cst->request.number_of_ibs = 3;
 651    cs->cst->request.ibs = &cs->cst->ib[IB_CONST_PREAMBLE];
 652
 653    return &cs->const_preamble_ib.base;
 654 }
 655
 656 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 657
 658 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 659                                struct pb_buffer *buf)
 660 {
 661    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 662
 663    return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
 664 }
 665
 666 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 667 {
 668    return TRUE;
 669 }
 670
 671 static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw)
 672 {
 673    struct amdgpu_ib *ib = amdgpu_ib(rcs);
 674    struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib);
 675    unsigned requested_size = rcs->cdw + dw;
 676
 677    assert(rcs->cdw <= rcs->max_dw);
 678
 679    if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type))
 680       return false;
 681
 682    ib->max_ib_size = MAX2(ib->max_ib_size, requested_size);
 683
 684    return rcs->max_dw - rcs->cdw >= dw;
 685 }
 686
 687 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 688 {
 689    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 690    struct amdgpu_winsys *ws = cs->ctx->ws;
 691
 692    vram += cs->csc->used_vram;
 693    gtt += cs->csc->used_gart;
 694
 695    /* Anything that goes above the VRAM size should go to GTT. */
 696    if (vram > ws->info.vram_size)
 697        gtt += vram - ws->info.vram_size;
 698
 699    /* Now we just need to check if we have enough GTT. */
 700    return gtt < ws->info.gart_size * 0.7;
 701 }
 702
 703 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
 704 {
 705    struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 706
 707    return cs->used_vram + cs->used_gart;
 708 }
 709
 710 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 711                                           struct radeon_bo_list_item *list)
 712 {
 713     struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 714     int i;
 715
 716     if (list) {
 717         for (i = 0; i < cs->num_buffers; i++) {
 718             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 719             list[i].vm_address = cs->buffers[i].bo->va;
 720             list[i].priority_usage = cs->buffers[i].priority_usage;
 721         }
 722     }
 723     return cs->num_buffers;
 724 }
 725
 726 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 727
 728 /* Since the kernel driver doesn't synchronize execution between different
 729  * rings automatically, we have to add fence dependencies manually.
 730  */
 731 static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs)
 732 {
 733    struct amdgpu_cs_context *cs = acs->csc;
 734    int i, j;
 735
 736    cs->request.number_of_dependencies = 0;
 737
 738    for (i = 0; i < cs->num_buffers; i++) {
 739       for (j = 0; j < RING_LAST; j++) {
 740          struct amdgpu_cs_fence *dep;
 741          unsigned idx;
 742
 743          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 744          if (!bo_fence)
 745             continue;
 746
 747          if (bo_fence->ctx == acs->ctx &&
 748              bo_fence->fence.ip_type == cs->request.ip_type &&
 749              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 750              bo_fence->fence.ring == cs->request.ring)
 751             continue;
 752
 753          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 754             continue;
 755
 756          if (bo_fence->submission_in_progress)
 757             os_wait_until_zero(&bo_fence->submission_in_progress,
 758                                PIPE_TIMEOUT_INFINITE);
 759
 760          idx = cs->request.number_of_dependencies++;
 761          if (idx >= cs->max_dependencies) {
 762             unsigned size;
 763
 764             cs->max_dependencies = idx + 8;
 765             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 766             cs->request.dependencies = realloc(cs->request.dependencies, size);
 767          }
 768
 769          dep = &cs->request.dependencies[idx];
 770          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 771       }
 772    }
 773 }
 774
 775 void amdgpu_cs_submit_ib(struct amdgpu_cs *acs)
 776 {
 777    struct amdgpu_winsys *ws = acs->ctx->ws;
 778    struct amdgpu_cs_context *cs = acs->cst;
 779    int i, r;
 780
 781    cs->request.fence_info.handle = NULL;
 782    if (amdgpu_cs_has_user_fence(cs)) {
 783         cs->request.fence_info.handle = acs->ctx->user_fence_bo;
 784         cs->request.fence_info.offset = acs->ring_type;
 785    }
 786
 787    /* Create the buffer list.
 788     * Use a buffer list containing all allocated buffers if requested.
 789     */
 790    if (debug_get_option_all_bos()) {
 791       struct amdgpu_winsys_bo *bo;
 792       amdgpu_bo_handle *handles;
 793       unsigned num = 0;
 794
 795       pipe_mutex_lock(ws->global_bo_list_lock);
 796
 797       handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 798       if (!handles) {
 799          pipe_mutex_unlock(ws->global_bo_list_lock);
 800          amdgpu_cs_context_cleanup(cs);
 801          return;
 802       }
 803
 804       LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 805          assert(num < ws->num_buffers);
 806          handles[num++] = bo->bo;
 807       }
 808
 809       r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 810                                 handles, NULL,
 811                                 &cs->request.resources);
 812       free(handles);
 813       pipe_mutex_unlock(ws->global_bo_list_lock);
 814    } else {
 815       r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 816                                 cs->handles, cs->flags,
 817                                 &cs->request.resources);
 818    }
 819
 820    if (r) {
 821       fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
 822       cs->request.resources = NULL;
 823       amdgpu_fence_signalled(cs->fence);
 824       goto cleanup;
 825    }
 826
 827    r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1);
 828    if (r) {
 829       if (r == -ENOMEM)
 830          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 831       else
 832          fprintf(stderr, "amdgpu: The CS has been rejected, "
 833                  "see dmesg for more information.\n");
 834
 835       amdgpu_fence_signalled(cs->fence);
 836    } else {
 837       /* Success. */
 838       uint64_t *user_fence = NULL;
 839       if (amdgpu_cs_has_user_fence(cs))
 840          user_fence = acs->ctx->user_fence_cpu_address_base +
 841                       cs->request.fence_info.offset;
 842       amdgpu_fence_submitted(cs->fence, &cs->request, user_fence);
 843    }
 844
 845    /* Cleanup. */
 846    if (cs->request.resources)
 847       amdgpu_bo_list_destroy(cs->request.resources);
 848
 849 cleanup:
 850    for (i = 0; i < cs->num_buffers; i++)
 851       p_atomic_dec(&cs->buffers[i].bo->num_active_ioctls);
 852
 853    amdgpu_cs_context_cleanup(cs);
 854 }
 855
 856 /* Make sure the previous submission is completed. */
 857 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 858 {
 859    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 860
 861    /* Wait for any pending ioctl of this CS to complete. */
 862    if (cs->ctx->ws->thread) {
 863       /* wait and set the semaphore to "busy" */
 864       pipe_semaphore_wait(&cs->flush_completed);
 865       /* set the semaphore to "idle" */
 866       pipe_semaphore_signal(&cs->flush_completed);
 867    }
 868 }
 869
 870 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 871
 872 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 873                             unsigned flags,
 874                             struct pipe_fence_handle **fence)
 875 {
 876    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 877    struct amdgpu_winsys *ws = cs->ctx->ws;
 878
 879    switch (cs->ring_type) {
 880    case RING_DMA:
 881       /* pad DMA ring to 8 DWs */
 882       while (rcs->cdw & 7)
 883          OUT_CS(rcs, 0x00000000); /* NOP packet */
 884       break;
 885    case RING_GFX:
 886       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 887       while (rcs->cdw & 7)
 888          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 889
 890       /* Also pad the const IB. */
 891       if (cs->const_ib.ib_mapped)
 892          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 893             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 894
 895       if (cs->const_preamble_ib.ib_mapped)
 896          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 897             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 898       break;
 899    case RING_UVD:
 900       while (rcs->cdw & 15)
 901          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 902       break;
 903    default:
 904       break;
 905    }
 906
 907    if (rcs->cdw > rcs->max_dw) {
 908       fprintf(stderr, "amdgpu: command stream overflowed\n");
 909    }
 910
 911    /* If the CS is not empty or overflowed.... */
 912    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw &&
 913        !debug_get_option_noop()) {
 914       struct amdgpu_cs_context *cur = cs->csc;
 915       unsigned i, num_buffers = cur->num_buffers;
 916
 917       /* Set IB sizes. */
 918       cur->ib[IB_MAIN].size = cs->main.base.cdw;
 919       cs->main.used_ib_space += cs->main.base.cdw * 4;
 920       cs->main.max_ib_size = MAX2(cs->main.max_ib_size, cs->main.base.cdw);
 921
 922       if (cs->const_ib.ib_mapped) {
 923          cur->ib[IB_CONST].size = cs->const_ib.base.cdw;
 924          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 925          cs->const_ib.max_ib_size = MAX2(cs->const_ib.max_ib_size, cs->const_ib.base.cdw);
 926       }
 927
 928       if (cs->const_preamble_ib.ib_mapped) {
 929          cur->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 930          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 931          cs->const_preamble_ib.max_ib_size =
 932             MAX2(cs->const_preamble_ib.max_ib_size, cs->const_preamble_ib.base.cdw);
 933       }
 934
 935       /* Create a fence. */
 936       amdgpu_fence_reference(&cur->fence, NULL);
 937       cur->fence = amdgpu_fence_create(cs->ctx,
 938                                            cur->request.ip_type,
 939                                            cur->request.ip_instance,
 940                                            cur->request.ring);
 941       if (fence)
 942          amdgpu_fence_reference(fence, cur->fence);
 943
 944       /* Prepare buffers. */
 945       pipe_mutex_lock(ws->bo_fence_lock);
 946       amdgpu_add_fence_dependencies(cs);
 947       for (i = 0; i < num_buffers; i++) {
 948          p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls);
 949          amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type],
 950                                 cur->fence);
 951       }
 952       pipe_mutex_unlock(ws->bo_fence_lock);
 953
 954       amdgpu_cs_sync_flush(rcs);
 955
 956       /* Swap command streams. "cst" is going to be submitted. */
 957       cs->csc = cs->cst;
 958       cs->cst = cur;
 959
 960       /* Submit. */
 961       if (ws->thread && (flags & RADEON_FLUSH_ASYNC)) {
 962          /* Set the semaphore to "busy". */
 963          pipe_semaphore_wait(&cs->flush_completed);
 964          amdgpu_ws_queue_cs(ws, cs);
 965       } else {
 966          amdgpu_cs_submit_ib(cs);
 967       }
 968    } else {
 969       amdgpu_cs_context_cleanup(cs->csc);
 970    }
 971
 972    amdgpu_get_new_ib(&ws->base, cs, IB_MAIN);
 973    if (cs->const_ib.ib_mapped)
 974       amdgpu_get_new_ib(&ws->base, cs, IB_CONST);
 975    if (cs->const_preamble_ib.ib_mapped)
 976       amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE);
 977
 978    ws->num_cs_flushes++;
 979 }
 980
 981 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 982 {
 983    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 984
 985    amdgpu_cs_sync_flush(rcs);
 986    pipe_semaphore_destroy(&cs->flush_completed);
 987    p_atomic_dec(&cs->ctx->ws->num_cs);
 988    pb_reference(&cs->main.big_ib_buffer, NULL);
 989    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 990    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 991    amdgpu_destroy_cs_context(&cs->csc1);
 992    amdgpu_destroy_cs_context(&cs->csc2);
 993    FREE(cs);
 994 }
 995
 996 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 997                                        struct pb_buffer *_buf,
 998                                        enum radeon_bo_usage usage)
 999 {
1000    struct amdgpu_cs *cs = amdgpu_cs(rcs);
1001    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
1002
1003    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
1004 }
1005
1006 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
1007 {
1008    ws->base.ctx_create = amdgpu_ctx_create;
1009    ws->base.ctx_destroy = amdgpu_ctx_destroy;
1010    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
1011    ws->base.cs_create = amdgpu_cs_create;
1012    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
1013    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
1014    ws->base.cs_destroy = amdgpu_cs_destroy;
1015    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
1016    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
1017    ws->base.cs_validate = amdgpu_cs_validate;
1018    ws->base.cs_check_space = amdgpu_cs_check_space;
1019    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
1020    ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
1021    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
1022    ws->base.cs_flush = amdgpu_cs_flush;
1023    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
1024    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
1025    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
1026    ws->base.fence_reference = amdgpu_fence_reference;
1027 }