2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "../../../drivers/radeonsi/sid.h"
42 static struct pipe_fence_handle
*
43 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
44 unsigned ip_instance
, unsigned ring
)
46 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
48 fence
->reference
.count
= 1;
50 fence
->fence
.context
= ctx
->ctx
;
51 fence
->fence
.ip_type
= ip_type
;
52 fence
->fence
.ip_instance
= ip_instance
;
53 fence
->fence
.ring
= ring
;
54 fence
->submission_in_progress
= true;
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
60 struct amdgpu_cs_request
* request
,
61 uint64_t *user_fence_cpu_address
)
63 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
65 rfence
->fence
.fence
= request
->seq_no
;
66 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
67 rfence
->submission_in_progress
= false;
70 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
72 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
74 rfence
->signalled
= true;
75 rfence
->submission_in_progress
= false;
78 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
81 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
84 uint64_t *user_fence_cpu
;
87 if (rfence
->signalled
)
91 abs_timeout
= timeout
;
93 abs_timeout
= os_time_get_absolute_timeout(timeout
);
95 /* The fence might not have a number assigned if its IB is being
96 * submitted in the other thread right now. Wait until the submission
98 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
102 user_fence_cpu
= rfence
->user_fence_cpu_address
;
103 if (user_fence_cpu
) {
104 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
105 rfence
->signalled
= true;
109 /* No timeout, just query: no need for the ioctl. */
110 if (!absolute
&& !timeout
)
114 /* Now use the libdrm query. */
115 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
117 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
120 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
125 /* This variable can only transition from false to true, so it doesn't
126 * matter if threads race for it. */
127 rfence
->signalled
= true;
133 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
134 struct pipe_fence_handle
*fence
,
137 return amdgpu_fence_wait(fence
, timeout
, false);
142 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
144 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
146 struct amdgpu_bo_alloc_request alloc_buffer
= {};
147 amdgpu_bo_handle buf_handle
;
152 ctx
->ws
= amdgpu_winsys(ws
);
155 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
157 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
161 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
162 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
163 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
165 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
167 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
168 goto error_user_fence_alloc
;
171 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
173 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
174 goto error_user_fence_map
;
177 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
178 ctx
->user_fence_bo
= buf_handle
;
180 return (struct radeon_winsys_ctx
*)ctx
;
182 error_user_fence_map
:
183 amdgpu_bo_free(buf_handle
);
184 error_user_fence_alloc
:
185 amdgpu_cs_ctx_free(ctx
->ctx
);
191 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
193 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
196 static enum pipe_reset_status
197 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
199 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
200 uint32_t result
, hangs
;
203 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
205 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
206 return PIPE_NO_RESET
;
210 case AMDGPU_CTX_GUILTY_RESET
:
211 return PIPE_GUILTY_CONTEXT_RESET
;
212 case AMDGPU_CTX_INNOCENT_RESET
:
213 return PIPE_INNOCENT_CONTEXT_RESET
;
214 case AMDGPU_CTX_UNKNOWN_RESET
:
215 return PIPE_UNKNOWN_CONTEXT_RESET
;
216 case AMDGPU_CTX_NO_RESET
:
218 return PIPE_NO_RESET
;
222 /* COMMAND SUBMISSION */
224 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
226 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
227 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
230 static bool amdgpu_cs_has_chaining(enum ring_type ring_type
)
232 return ring_type
== RING_GFX
;
235 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
237 if (ring_type
== RING_GFX
)
238 return 4; /* for chaining */
243 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
245 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
246 int i
= cs
->buffer_indices_hashlist
[hash
];
248 /* not found or found */
249 if (i
== -1 || cs
->buffers
[i
].bo
== bo
)
252 /* Hash collision, look for the BO in the list of buffers linearly. */
253 for (i
= cs
->num_buffers
- 1; i
>= 0; i
--) {
254 if (cs
->buffers
[i
].bo
== bo
) {
255 /* Put this buffer in the hash list.
256 * This will prevent additional hash collisions if there are
257 * several consecutive lookup_buffer calls for the same buffer.
259 * Example: Assuming buffers A,B,C collide in the hash list,
260 * the following sequence of buffers:
261 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
262 * will collide here: ^ and here: ^,
263 * meaning that we should get very few collisions in the end. */
264 cs
->buffer_indices_hashlist
[hash
] = i
;
271 static unsigned amdgpu_add_buffer(struct amdgpu_cs
*acs
,
272 struct amdgpu_winsys_bo
*bo
,
273 enum radeon_bo_usage usage
,
274 enum radeon_bo_domain domains
,
276 enum radeon_bo_domain
*added_domains
)
278 struct amdgpu_cs_context
*cs
= acs
->csc
;
279 struct amdgpu_cs_buffer
*buffer
;
280 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
283 assert(priority
< 64);
286 i
= amdgpu_lookup_buffer(cs
, bo
);
289 buffer
= &cs
->buffers
[i
];
290 buffer
->priority_usage
|= 1llu << priority
;
291 buffer
->usage
|= usage
;
292 *added_domains
= domains
& ~buffer
->domains
;
293 buffer
->domains
|= domains
;
294 cs
->flags
[i
] = MAX2(cs
->flags
[i
], priority
/ 4);
298 /* New buffer, check if the backing array is large enough. */
299 if (cs
->num_buffers
>= cs
->max_num_buffers
) {
301 cs
->max_num_buffers
+= 10;
303 size
= cs
->max_num_buffers
* sizeof(struct amdgpu_cs_buffer
);
304 cs
->buffers
= realloc(cs
->buffers
, size
);
306 size
= cs
->max_num_buffers
* sizeof(amdgpu_bo_handle
);
307 cs
->handles
= realloc(cs
->handles
, size
);
309 cs
->flags
= realloc(cs
->flags
, cs
->max_num_buffers
);
312 /* Initialize the new buffer. */
313 cs
->buffers
[cs
->num_buffers
].bo
= NULL
;
314 amdgpu_winsys_bo_reference(&cs
->buffers
[cs
->num_buffers
].bo
, bo
);
315 cs
->handles
[cs
->num_buffers
] = bo
->bo
;
316 cs
->flags
[cs
->num_buffers
] = priority
/ 4;
317 p_atomic_inc(&bo
->num_cs_references
);
318 buffer
= &cs
->buffers
[cs
->num_buffers
];
320 buffer
->priority_usage
= 1llu << priority
;
321 buffer
->usage
= usage
;
322 buffer
->domains
= domains
;
324 cs
->buffer_indices_hashlist
[hash
] = cs
->num_buffers
;
326 *added_domains
= domains
;
327 return cs
->num_buffers
++;
330 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
331 struct pb_buffer
*buf
,
332 enum radeon_bo_usage usage
,
333 enum radeon_bo_domain domains
,
334 enum radeon_bo_priority priority
)
336 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
337 * the buffer placement during command submission.
339 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
340 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
341 enum radeon_bo_domain added_domains
;
342 unsigned index
= amdgpu_add_buffer(cs
, bo
, usage
, bo
->initial_domain
,
343 priority
, &added_domains
);
345 if (added_domains
& RADEON_DOMAIN_VRAM
)
346 cs
->csc
->used_vram
+= bo
->base
.size
;
347 else if (added_domains
& RADEON_DOMAIN_GTT
)
348 cs
->csc
->used_gart
+= bo
->base
.size
;
353 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
355 struct pb_buffer
*pb
;
357 unsigned buffer_size
;
359 /* Always create a buffer that is at least as large as the maximum seen IB
360 * size, aligned to a power of two (and multiplied by 4 to reduce internal
361 * fragmentation if chaining is not available). Limit to 512k dwords, which
362 * is the largest power of two that fits into the size field of the
363 * INDIRECT_BUFFER packet.
365 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)->ring_type
))
366 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
368 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
370 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
372 switch (ib
->ib_type
) {
373 case IB_CONST_PREAMBLE
:
374 buffer_size
= MAX2(buffer_size
, 4 * 1024);
377 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
380 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
383 unreachable("unhandled IB type");
386 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
387 ws
->info
.gart_page_size
,
389 RADEON_FLAG_CPU_ACCESS
);
393 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
395 pb_reference(&pb
, NULL
);
399 pb_reference(&ib
->big_ib_buffer
, pb
);
400 pb_reference(&pb
, NULL
);
402 ib
->ib_mapped
= mapped
;
403 ib
->used_ib_space
= 0;
408 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
412 /* Smaller submits means the GPU gets busy sooner and there is less
413 * waiting for buffers and fences. Proof:
414 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
417 case IB_CONST_PREAMBLE
:
419 /* There isn't really any reason to limit CE IB size beyond the natural
420 * limit implied by the main IB, except perhaps GTT size. Just return
421 * an extremely large value that we never get anywhere close to.
423 return 16 * 1024 * 1024;
425 unreachable("bad ib_type");
429 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
430 enum ib_type ib_type
)
432 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
433 /* Small IBs are better than big IBs, because the GPU goes idle quicker
434 * and there is less waiting for buffers and fences. Proof:
435 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
437 struct amdgpu_ib
*ib
= NULL
;
438 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
439 unsigned ib_size
= 0;
442 case IB_CONST_PREAMBLE
:
443 ib
= &cs
->const_preamble_ib
;
448 ib_size
= 8 * 1024 * 4;
452 ib_size
= 4 * 1024 * 4;
455 unreachable("unhandled IB type");
458 if (!amdgpu_cs_has_chaining(cs
->ring_type
)) {
459 ib_size
= MAX2(ib_size
,
460 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
461 amdgpu_ib_max_submit_dwords(ib_type
)));
464 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
466 ib
->base
.prev_dw
= 0;
467 ib
->base
.num_prev
= 0;
468 ib
->base
.current
.cdw
= 0;
469 ib
->base
.current
.buf
= NULL
;
471 /* Allocate a new buffer for IBs if the current buffer is all used. */
472 if (!ib
->big_ib_buffer
||
473 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
474 if (!amdgpu_ib_new_buffer(aws
, ib
))
478 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
481 ib
->ptr_ib_size
= &info
->size
;
483 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
484 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
486 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
488 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
489 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
493 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
495 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
496 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
497 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
500 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
501 enum ring_type ring_type
)
507 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
511 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
515 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
519 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
524 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
528 cs
->max_num_buffers
= 512;
529 cs
->buffers
= (struct amdgpu_cs_buffer
*)
530 CALLOC(1, cs
->max_num_buffers
* sizeof(struct amdgpu_cs_buffer
));
535 cs
->handles
= CALLOC(1, cs
->max_num_buffers
* sizeof(amdgpu_bo_handle
));
541 cs
->flags
= CALLOC(1, cs
->max_num_buffers
);
548 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
549 cs
->buffer_indices_hashlist
[i
] = -1;
552 cs
->request
.number_of_ibs
= 1;
553 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
555 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
556 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
557 AMDGPU_IB_FLAG_PREAMBLE
;
562 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
566 for (i
= 0; i
< cs
->num_buffers
; i
++) {
567 p_atomic_dec(&cs
->buffers
[i
].bo
->num_cs_references
);
568 amdgpu_winsys_bo_reference(&cs
->buffers
[i
].bo
, NULL
);
569 cs
->handles
[i
] = NULL
;
576 amdgpu_fence_reference(&cs
->fence
, NULL
);
578 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
579 cs
->buffer_indices_hashlist
[i
] = -1;
583 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
585 amdgpu_cs_context_cleanup(cs
);
589 FREE(cs
->request
.dependencies
);
593 static struct radeon_winsys_cs
*
594 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
595 enum ring_type ring_type
,
596 void (*flush
)(void *ctx
, unsigned flags
,
597 struct pipe_fence_handle
**fence
),
600 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
601 struct amdgpu_cs
*cs
;
603 cs
= CALLOC_STRUCT(amdgpu_cs
);
608 util_queue_fence_init(&cs
->flush_completed
);
611 cs
->flush_cs
= flush
;
612 cs
->flush_data
= flush_ctx
;
613 cs
->ring_type
= ring_type
;
615 cs
->main
.ib_type
= IB_MAIN
;
616 cs
->const_ib
.ib_type
= IB_CONST
;
617 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
619 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
624 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
625 amdgpu_destroy_cs_context(&cs
->csc1
);
630 /* Set the first submission context as current. */
634 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
635 amdgpu_destroy_cs_context(&cs
->csc2
);
636 amdgpu_destroy_cs_context(&cs
->csc1
);
641 p_atomic_inc(&ctx
->ws
->num_cs
);
642 return &cs
->main
.base
;
645 static struct radeon_winsys_cs
*
646 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
648 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
649 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
651 /* only one const IB can be added */
652 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
655 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
658 cs
->csc
->request
.number_of_ibs
= 2;
659 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
661 cs
->cst
->request
.number_of_ibs
= 2;
662 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
664 return &cs
->const_ib
.base
;
667 static struct radeon_winsys_cs
*
668 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
670 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
671 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
673 /* only one const preamble IB can be added and only when the const IB has
674 * also been mapped */
675 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
676 cs
->const_preamble_ib
.ib_mapped
)
679 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
682 cs
->csc
->request
.number_of_ibs
= 3;
683 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
685 cs
->cst
->request
.number_of_ibs
= 3;
686 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
688 return &cs
->const_preamble_ib
.base
;
691 #define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value)
693 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs
*rcs
,
694 struct pb_buffer
*buf
)
696 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
698 return amdgpu_lookup_buffer(cs
->csc
, (struct amdgpu_winsys_bo
*)buf
);
701 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
706 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
708 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
709 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
710 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
712 uint32_t *new_ptr_ib_size
;
714 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
716 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
719 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
721 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
724 if (!amdgpu_cs_has_chaining(cs
->ring_type
))
727 /* Allocate a new chunk */
728 if (rcs
->num_prev
>= rcs
->max_prev
) {
729 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
730 struct radeon_winsys_cs_chunk
*new_prev
;
732 new_prev
= REALLOC(rcs
->prev
,
733 sizeof(*new_prev
) * rcs
->max_prev
,
734 sizeof(*new_prev
) * new_max_prev
);
738 rcs
->prev
= new_prev
;
739 rcs
->max_prev
= new_max_prev
;
742 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
745 assert(ib
->used_ib_space
== 0);
746 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
748 /* This space was originally reserved. */
749 rcs
->current
.max_dw
+= 4;
750 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
752 /* Pad with NOPs and add INDIRECT_BUFFER packet */
753 while ((rcs
->current
.cdw
& 7) != 4)
754 OUT_CS(rcs
, 0xffff1000); /* type3 nop packet */
756 OUT_CS(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
757 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
759 OUT_CS(rcs
, va
>> 32);
760 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
761 OUT_CS(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
763 assert((rcs
->current
.cdw
& 7) == 0);
764 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
766 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
767 ib
->ptr_ib_size
= new_ptr_ib_size
;
769 /* Hook up the new chunk */
770 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
771 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
772 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
775 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
776 ib
->base
.current
.cdw
= 0;
778 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
779 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
781 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
782 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
787 static bool amdgpu_cs_memory_below_limit(struct radeon_winsys_cs
*rcs
,
788 uint64_t vram
, uint64_t gtt
)
790 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
791 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
793 vram
+= cs
->csc
->used_vram
;
794 gtt
+= cs
->csc
->used_gart
;
796 /* Anything that goes above the VRAM size should go to GTT. */
797 if (vram
> ws
->info
.vram_size
)
798 gtt
+= vram
- ws
->info
.vram_size
;
800 /* Now we just need to check if we have enough GTT. */
801 return gtt
< ws
->info
.gart_size
* 0.7;
804 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs
*rcs
)
806 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
808 return cs
->used_vram
+ cs
->used_gart
;
811 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
812 struct radeon_bo_list_item
*list
)
814 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
818 for (i
= 0; i
< cs
->num_buffers
; i
++) {
819 list
[i
].bo_size
= cs
->buffers
[i
].bo
->base
.size
;
820 list
[i
].vm_address
= cs
->buffers
[i
].bo
->va
;
821 list
[i
].priority_usage
= cs
->buffers
[i
].priority_usage
;
824 return cs
->num_buffers
;
827 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
829 /* Since the kernel driver doesn't synchronize execution between different
830 * rings automatically, we have to add fence dependencies manually.
832 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
834 struct amdgpu_cs_context
*cs
= acs
->csc
;
837 cs
->request
.number_of_dependencies
= 0;
839 for (i
= 0; i
< cs
->num_buffers
; i
++) {
840 for (j
= 0; j
< RING_LAST
; j
++) {
841 struct amdgpu_cs_fence
*dep
;
844 struct amdgpu_fence
*bo_fence
= (void *)cs
->buffers
[i
].bo
->fence
[j
];
848 if (bo_fence
->ctx
== acs
->ctx
&&
849 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
850 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
851 bo_fence
->fence
.ring
== cs
->request
.ring
)
854 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
857 if (bo_fence
->submission_in_progress
)
858 os_wait_until_zero(&bo_fence
->submission_in_progress
,
859 PIPE_TIMEOUT_INFINITE
);
861 idx
= cs
->request
.number_of_dependencies
++;
862 if (idx
>= cs
->max_dependencies
) {
865 cs
->max_dependencies
= idx
+ 8;
866 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
867 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
870 dep
= &cs
->request
.dependencies
[idx
];
871 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
876 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
878 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
879 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
880 struct amdgpu_cs_context
*cs
= acs
->cst
;
883 cs
->request
.fence_info
.handle
= NULL
;
884 if (amdgpu_cs_has_user_fence(cs
)) {
885 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
886 cs
->request
.fence_info
.offset
= acs
->ring_type
;
889 /* Create the buffer list.
890 * Use a buffer list containing all allocated buffers if requested.
892 if (debug_get_option_all_bos()) {
893 struct amdgpu_winsys_bo
*bo
;
894 amdgpu_bo_handle
*handles
;
897 pipe_mutex_lock(ws
->global_bo_list_lock
);
899 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
901 pipe_mutex_unlock(ws
->global_bo_list_lock
);
902 amdgpu_cs_context_cleanup(cs
);
903 cs
->error_code
= -ENOMEM
;
907 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
908 assert(num
< ws
->num_buffers
);
909 handles
[num
++] = bo
->bo
;
912 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
914 &cs
->request
.resources
);
916 pipe_mutex_unlock(ws
->global_bo_list_lock
);
918 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
,
919 cs
->handles
, cs
->flags
,
920 &cs
->request
.resources
);
924 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
925 cs
->request
.resources
= NULL
;
926 amdgpu_fence_signalled(cs
->fence
);
931 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
935 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
937 fprintf(stderr
, "amdgpu: The CS has been rejected, "
938 "see dmesg for more information.\n");
940 amdgpu_fence_signalled(cs
->fence
);
943 uint64_t *user_fence
= NULL
;
944 if (amdgpu_cs_has_user_fence(cs
))
945 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
946 cs
->request
.fence_info
.offset
;
947 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
951 if (cs
->request
.resources
)
952 amdgpu_bo_list_destroy(cs
->request
.resources
);
955 for (i
= 0; i
< cs
->num_buffers
; i
++)
956 p_atomic_dec(&cs
->buffers
[i
].bo
->num_active_ioctls
);
958 amdgpu_cs_context_cleanup(cs
);
961 /* Make sure the previous submission is completed. */
962 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
964 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
965 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
967 /* Wait for any pending ioctl of this CS to complete. */
968 if (util_queue_is_initialized(&ws
->cs_queue
))
969 util_queue_job_wait(&cs
->flush_completed
);
972 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
974 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
976 struct pipe_fence_handle
**fence
)
978 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
979 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
982 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
984 switch (cs
->ring_type
) {
986 /* pad DMA ring to 8 DWs */
987 while (rcs
->current
.cdw
& 7)
988 OUT_CS(rcs
, 0x00000000); /* NOP packet */
991 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
992 while (rcs
->current
.cdw
& 7)
993 OUT_CS(rcs
, 0xffff1000); /* type3 nop packet */
995 /* Also pad the const IB. */
996 if (cs
->const_ib
.ib_mapped
)
997 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
998 OUT_CS(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1000 if (cs
->const_preamble_ib
.ib_mapped
)
1001 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1002 OUT_CS(&cs
->const_preamble_ib
.base
, 0xffff1000);
1005 while (rcs
->current
.cdw
& 15)
1006 OUT_CS(rcs
, 0x80000000); /* type2 nop packet */
1012 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1013 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1016 /* If the CS is not empty or overflowed.... */
1017 if (radeon_emitted(&cs
->main
.base
, 0) &&
1018 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1019 !debug_get_option_noop()) {
1020 struct amdgpu_cs_context
*cur
= cs
->csc
;
1021 unsigned i
, num_buffers
= cur
->num_buffers
;
1024 amdgpu_ib_finalize(&cs
->main
);
1026 if (cs
->const_ib
.ib_mapped
)
1027 amdgpu_ib_finalize(&cs
->const_ib
);
1029 if (cs
->const_preamble_ib
.ib_mapped
)
1030 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1032 /* Create a fence. */
1033 amdgpu_fence_reference(&cur
->fence
, NULL
);
1034 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1035 cur
->request
.ip_type
,
1036 cur
->request
.ip_instance
,
1039 amdgpu_fence_reference(fence
, cur
->fence
);
1041 /* Prepare buffers. */
1042 pipe_mutex_lock(ws
->bo_fence_lock
);
1043 amdgpu_add_fence_dependencies(cs
);
1044 for (i
= 0; i
< num_buffers
; i
++) {
1045 p_atomic_inc(&cur
->buffers
[i
].bo
->num_active_ioctls
);
1046 amdgpu_fence_reference(&cur
->buffers
[i
].bo
->fence
[cs
->ring_type
],
1049 pipe_mutex_unlock(ws
->bo_fence_lock
);
1051 amdgpu_cs_sync_flush(rcs
);
1053 /* Swap command streams. "cst" is going to be submitted. */
1058 if ((flags
& RADEON_FLUSH_ASYNC
) &&
1059 util_queue_is_initialized(&ws
->cs_queue
)) {
1060 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1061 amdgpu_cs_submit_ib
);
1063 amdgpu_cs_submit_ib(cs
, 0);
1064 error_code
= cs
->cst
->error_code
;
1067 amdgpu_cs_context_cleanup(cs
->csc
);
1070 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1071 if (cs
->const_ib
.ib_mapped
)
1072 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1073 if (cs
->const_preamble_ib
.ib_mapped
)
1074 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1076 ws
->num_cs_flushes
++;
1080 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1082 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1084 amdgpu_cs_sync_flush(rcs
);
1085 util_queue_fence_destroy(&cs
->flush_completed
);
1086 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1087 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1088 FREE(cs
->main
.base
.prev
);
1089 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1090 FREE(cs
->const_ib
.base
.prev
);
1091 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1092 FREE(cs
->const_preamble_ib
.base
.prev
);
1093 amdgpu_destroy_cs_context(&cs
->csc1
);
1094 amdgpu_destroy_cs_context(&cs
->csc2
);
1098 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1099 struct pb_buffer
*_buf
,
1100 enum radeon_bo_usage usage
)
1102 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1103 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1105 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1108 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1110 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1111 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1112 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1113 ws
->base
.cs_create
= amdgpu_cs_create
;
1114 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1115 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1116 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1117 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1118 ws
->base
.cs_lookup_buffer
= amdgpu_cs_lookup_buffer
;
1119 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1120 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1121 ws
->base
.cs_memory_below_limit
= amdgpu_cs_memory_below_limit
;
1122 ws
->base
.cs_query_memory_usage
= amdgpu_cs_query_memory_usage
;
1123 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1124 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1125 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1126 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1127 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1128 ws
->base
.fence_reference
= amdgpu_fence_reference
;