2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
41 static struct pipe_fence_handle
*
42 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
43 unsigned ip_instance
, unsigned ring
)
45 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
47 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 fence
->submission_in_progress
= true;
54 p_atomic_inc(&ctx
->refcount
);
55 return (struct pipe_fence_handle
*)fence
;
58 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
59 struct amdgpu_cs_request
* request
,
60 uint64_t *user_fence_cpu_address
)
62 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
64 rfence
->fence
.fence
= request
->seq_no
;
65 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
66 rfence
->submission_in_progress
= false;
69 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
71 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
73 rfence
->signalled
= true;
74 rfence
->submission_in_progress
= false;
77 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
80 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
83 uint64_t *user_fence_cpu
;
86 if (rfence
->signalled
)
90 abs_timeout
= timeout
;
92 abs_timeout
= os_time_get_absolute_timeout(timeout
);
94 /* The fence might not have a number assigned if its IB is being
95 * submitted in the other thread right now. Wait until the submission
97 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
101 user_fence_cpu
= rfence
->user_fence_cpu_address
;
102 if (user_fence_cpu
) {
103 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
104 rfence
->signalled
= true;
108 /* No timeout, just query: no need for the ioctl. */
109 if (!absolute
&& !timeout
)
113 /* Now use the libdrm query. */
114 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
116 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
119 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
124 /* This variable can only transition from false to true, so it doesn't
125 * matter if threads race for it. */
126 rfence
->signalled
= true;
132 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
133 struct pipe_fence_handle
*fence
,
136 return amdgpu_fence_wait(fence
, timeout
, false);
141 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
143 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
145 struct amdgpu_bo_alloc_request alloc_buffer
= {};
146 amdgpu_bo_handle buf_handle
;
151 ctx
->ws
= amdgpu_winsys(ws
);
154 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
156 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
160 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
161 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
162 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
164 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
166 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
167 goto error_user_fence_alloc
;
170 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
172 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
173 goto error_user_fence_map
;
176 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
177 ctx
->user_fence_bo
= buf_handle
;
179 return (struct radeon_winsys_ctx
*)ctx
;
181 error_user_fence_map
:
182 amdgpu_bo_free(buf_handle
);
183 error_user_fence_alloc
:
184 amdgpu_cs_ctx_free(ctx
->ctx
);
190 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
192 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
195 static enum pipe_reset_status
196 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
198 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
199 uint32_t result
, hangs
;
202 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
204 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
205 return PIPE_NO_RESET
;
209 case AMDGPU_CTX_GUILTY_RESET
:
210 return PIPE_GUILTY_CONTEXT_RESET
;
211 case AMDGPU_CTX_INNOCENT_RESET
:
212 return PIPE_INNOCENT_CONTEXT_RESET
;
213 case AMDGPU_CTX_UNKNOWN_RESET
:
214 return PIPE_UNKNOWN_CONTEXT_RESET
;
215 case AMDGPU_CTX_NO_RESET
:
217 return PIPE_NO_RESET
;
221 /* COMMAND SUBMISSION */
223 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
225 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
226 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
229 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
231 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
232 int i
= cs
->buffer_indices_hashlist
[hash
];
234 /* not found or found */
235 if (i
== -1 || cs
->buffers
[i
].bo
== bo
)
238 /* Hash collision, look for the BO in the list of buffers linearly. */
239 for (i
= cs
->num_buffers
- 1; i
>= 0; i
--) {
240 if (cs
->buffers
[i
].bo
== bo
) {
241 /* Put this buffer in the hash list.
242 * This will prevent additional hash collisions if there are
243 * several consecutive lookup_buffer calls for the same buffer.
245 * Example: Assuming buffers A,B,C collide in the hash list,
246 * the following sequence of buffers:
247 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
248 * will collide here: ^ and here: ^,
249 * meaning that we should get very few collisions in the end. */
250 cs
->buffer_indices_hashlist
[hash
] = i
;
257 static unsigned amdgpu_add_buffer(struct amdgpu_cs
*acs
,
258 struct amdgpu_winsys_bo
*bo
,
259 enum radeon_bo_usage usage
,
260 enum radeon_bo_domain domains
,
262 enum radeon_bo_domain
*added_domains
)
264 struct amdgpu_cs_context
*cs
= acs
->csc
;
265 struct amdgpu_cs_buffer
*buffer
;
266 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
269 assert(priority
< 64);
272 i
= amdgpu_lookup_buffer(cs
, bo
);
275 buffer
= &cs
->buffers
[i
];
276 buffer
->priority_usage
|= 1llu << priority
;
277 buffer
->usage
|= usage
;
278 *added_domains
= domains
& ~buffer
->domains
;
279 buffer
->domains
|= domains
;
280 cs
->flags
[i
] = MAX2(cs
->flags
[i
], priority
/ 4);
284 /* New buffer, check if the backing array is large enough. */
285 if (cs
->num_buffers
>= cs
->max_num_buffers
) {
287 cs
->max_num_buffers
+= 10;
289 size
= cs
->max_num_buffers
* sizeof(struct amdgpu_cs_buffer
);
290 cs
->buffers
= realloc(cs
->buffers
, size
);
292 size
= cs
->max_num_buffers
* sizeof(amdgpu_bo_handle
);
293 cs
->handles
= realloc(cs
->handles
, size
);
295 cs
->flags
= realloc(cs
->flags
, cs
->max_num_buffers
);
298 /* Initialize the new buffer. */
299 cs
->buffers
[cs
->num_buffers
].bo
= NULL
;
300 amdgpu_winsys_bo_reference(&cs
->buffers
[cs
->num_buffers
].bo
, bo
);
301 cs
->handles
[cs
->num_buffers
] = bo
->bo
;
302 cs
->flags
[cs
->num_buffers
] = priority
/ 4;
303 p_atomic_inc(&bo
->num_cs_references
);
304 buffer
= &cs
->buffers
[cs
->num_buffers
];
306 buffer
->priority_usage
= 1llu << priority
;
307 buffer
->usage
= usage
;
308 buffer
->domains
= domains
;
310 cs
->buffer_indices_hashlist
[hash
] = cs
->num_buffers
;
312 *added_domains
= domains
;
313 return cs
->num_buffers
++;
316 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
317 struct pb_buffer
*buf
,
318 enum radeon_bo_usage usage
,
319 enum radeon_bo_domain domains
,
320 enum radeon_bo_priority priority
)
322 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
323 * the buffer placement during command submission.
325 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
326 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
327 enum radeon_bo_domain added_domains
;
328 unsigned index
= amdgpu_add_buffer(cs
, bo
, usage
, bo
->initial_domain
,
329 priority
, &added_domains
);
331 if (added_domains
& RADEON_DOMAIN_VRAM
)
332 cs
->csc
->used_vram
+= bo
->base
.size
;
333 else if (added_domains
& RADEON_DOMAIN_GTT
)
334 cs
->csc
->used_gart
+= bo
->base
.size
;
339 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
341 struct pb_buffer
*pb
;
343 unsigned buffer_size
;
345 /* Always create a buffer that is 4 times larger than the maximum seen IB
346 * size, aligned to a power of two. Limit to 512k dwords, which is the
347 * largest power of two that fits into the size field of the INDIRECT_BUFFER
350 buffer_size
= 4 * MIN2(util_next_power_of_two(4 * ib
->max_ib_size
),
353 switch (ib
->ib_type
) {
354 case IB_CONST_PREAMBLE
:
355 buffer_size
= MAX2(buffer_size
, 4 * 1024);
358 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
361 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
364 unreachable("unhandled IB type");
367 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
368 ws
->info
.gart_page_size
,
370 RADEON_FLAG_CPU_ACCESS
);
374 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
376 pb_reference(&pb
, NULL
);
380 pb_reference(&ib
->big_ib_buffer
, pb
);
381 pb_reference(&pb
, NULL
);
383 ib
->ib_mapped
= mapped
;
384 ib
->used_ib_space
= 0;
389 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
393 /* Smaller submits means the GPU gets busy sooner and there is less
394 * waiting for buffers and fences. Proof:
395 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
398 case IB_CONST_PREAMBLE
:
400 /* There isn't really any reason to limit CE IB size beyond the natural
401 * limit implied by the main IB, except perhaps GTT size. Just return
402 * an extremely large value that we never get anywhere close to.
404 return 16 * 1024 * 1024;
406 unreachable("bad ib_type");
410 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
411 enum ib_type ib_type
)
413 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
414 /* Small IBs are better than big IBs, because the GPU goes idle quicker
415 * and there is less waiting for buffers and fences. Proof:
416 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
418 struct amdgpu_ib
*ib
= NULL
;
419 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
420 unsigned ib_size
= 0;
423 case IB_CONST_PREAMBLE
:
424 ib
= &cs
->const_preamble_ib
;
429 ib_size
= 8 * 1024 * 4;
433 ib_size
= 4 * 1024 * 4;
436 unreachable("unhandled IB type");
439 ib_size
= MAX2(ib_size
,
440 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
441 amdgpu_ib_max_submit_dwords(ib_type
)));
443 ib
->base
.prev_dw
= 0;
444 ib
->base
.num_prev
= 0;
445 ib
->base
.current
.cdw
= 0;
446 ib
->base
.current
.buf
= NULL
;
448 /* Allocate a new buffer for IBs if the current buffer is all used. */
449 if (!ib
->big_ib_buffer
||
450 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
451 if (!amdgpu_ib_new_buffer(aws
, ib
))
455 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
457 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
458 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
460 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
462 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
463 ib
->base
.current
.max_dw
= ib_size
/ 4;
467 static boolean
amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
468 enum ring_type ring_type
)
474 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
478 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
482 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
486 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
491 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
495 cs
->max_num_buffers
= 512;
496 cs
->buffers
= (struct amdgpu_cs_buffer
*)
497 CALLOC(1, cs
->max_num_buffers
* sizeof(struct amdgpu_cs_buffer
));
502 cs
->handles
= CALLOC(1, cs
->max_num_buffers
* sizeof(amdgpu_bo_handle
));
508 cs
->flags
= CALLOC(1, cs
->max_num_buffers
);
515 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
516 cs
->buffer_indices_hashlist
[i
] = -1;
519 cs
->request
.number_of_ibs
= 1;
520 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
522 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
523 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
524 AMDGPU_IB_FLAG_PREAMBLE
;
529 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
533 for (i
= 0; i
< cs
->num_buffers
; i
++) {
534 p_atomic_dec(&cs
->buffers
[i
].bo
->num_cs_references
);
535 amdgpu_winsys_bo_reference(&cs
->buffers
[i
].bo
, NULL
);
536 cs
->handles
[i
] = NULL
;
543 amdgpu_fence_reference(&cs
->fence
, NULL
);
545 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
546 cs
->buffer_indices_hashlist
[i
] = -1;
550 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
552 amdgpu_cs_context_cleanup(cs
);
556 FREE(cs
->request
.dependencies
);
560 static struct radeon_winsys_cs
*
561 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
562 enum ring_type ring_type
,
563 void (*flush
)(void *ctx
, unsigned flags
,
564 struct pipe_fence_handle
**fence
),
567 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
568 struct amdgpu_cs
*cs
;
570 cs
= CALLOC_STRUCT(amdgpu_cs
);
575 pipe_semaphore_init(&cs
->flush_completed
, 1);
578 cs
->flush_cs
= flush
;
579 cs
->flush_data
= flush_ctx
;
580 cs
->ring_type
= ring_type
;
582 cs
->main
.ib_type
= IB_MAIN
;
583 cs
->const_ib
.ib_type
= IB_CONST
;
584 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
586 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
591 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
592 amdgpu_destroy_cs_context(&cs
->csc1
);
597 /* Set the first submission context as current. */
601 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
602 amdgpu_destroy_cs_context(&cs
->csc2
);
603 amdgpu_destroy_cs_context(&cs
->csc1
);
608 p_atomic_inc(&ctx
->ws
->num_cs
);
609 return &cs
->main
.base
;
612 static struct radeon_winsys_cs
*
613 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
615 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
616 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
618 /* only one const IB can be added */
619 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
622 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
625 cs
->csc
->request
.number_of_ibs
= 2;
626 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
628 cs
->cst
->request
.number_of_ibs
= 2;
629 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
631 return &cs
->const_ib
.base
;
634 static struct radeon_winsys_cs
*
635 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
637 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
638 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
640 /* only one const preamble IB can be added and only when the const IB has
641 * also been mapped */
642 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
643 cs
->const_preamble_ib
.ib_mapped
)
646 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
649 cs
->csc
->request
.number_of_ibs
= 3;
650 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
652 cs
->cst
->request
.number_of_ibs
= 3;
653 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
655 return &cs
->const_preamble_ib
.base
;
658 #define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value)
660 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs
*rcs
,
661 struct pb_buffer
*buf
)
663 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
665 return amdgpu_lookup_buffer(cs
->csc
, (struct amdgpu_winsys_bo
*)buf
);
668 static boolean
amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
673 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
675 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
676 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
677 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
679 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
681 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
684 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
686 return rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
;
689 static boolean
amdgpu_cs_memory_below_limit(struct radeon_winsys_cs
*rcs
, uint64_t vram
, uint64_t gtt
)
691 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
692 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
694 vram
+= cs
->csc
->used_vram
;
695 gtt
+= cs
->csc
->used_gart
;
697 /* Anything that goes above the VRAM size should go to GTT. */
698 if (vram
> ws
->info
.vram_size
)
699 gtt
+= vram
- ws
->info
.vram_size
;
701 /* Now we just need to check if we have enough GTT. */
702 return gtt
< ws
->info
.gart_size
* 0.7;
705 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs
*rcs
)
707 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
709 return cs
->used_vram
+ cs
->used_gart
;
712 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
713 struct radeon_bo_list_item
*list
)
715 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
719 for (i
= 0; i
< cs
->num_buffers
; i
++) {
720 pb_reference(&list
[i
].buf
, &cs
->buffers
[i
].bo
->base
);
721 list
[i
].vm_address
= cs
->buffers
[i
].bo
->va
;
722 list
[i
].priority_usage
= cs
->buffers
[i
].priority_usage
;
725 return cs
->num_buffers
;
728 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", FALSE
)
730 /* Since the kernel driver doesn't synchronize execution between different
731 * rings automatically, we have to add fence dependencies manually.
733 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
735 struct amdgpu_cs_context
*cs
= acs
->csc
;
738 cs
->request
.number_of_dependencies
= 0;
740 for (i
= 0; i
< cs
->num_buffers
; i
++) {
741 for (j
= 0; j
< RING_LAST
; j
++) {
742 struct amdgpu_cs_fence
*dep
;
745 struct amdgpu_fence
*bo_fence
= (void *)cs
->buffers
[i
].bo
->fence
[j
];
749 if (bo_fence
->ctx
== acs
->ctx
&&
750 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
751 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
752 bo_fence
->fence
.ring
== cs
->request
.ring
)
755 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
758 if (bo_fence
->submission_in_progress
)
759 os_wait_until_zero(&bo_fence
->submission_in_progress
,
760 PIPE_TIMEOUT_INFINITE
);
762 idx
= cs
->request
.number_of_dependencies
++;
763 if (idx
>= cs
->max_dependencies
) {
766 cs
->max_dependencies
= idx
+ 8;
767 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
768 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
771 dep
= &cs
->request
.dependencies
[idx
];
772 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
777 void amdgpu_cs_submit_ib(struct amdgpu_cs
*acs
)
779 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
780 struct amdgpu_cs_context
*cs
= acs
->cst
;
783 cs
->request
.fence_info
.handle
= NULL
;
784 if (amdgpu_cs_has_user_fence(cs
)) {
785 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
786 cs
->request
.fence_info
.offset
= acs
->ring_type
;
789 /* Create the buffer list.
790 * Use a buffer list containing all allocated buffers if requested.
792 if (debug_get_option_all_bos()) {
793 struct amdgpu_winsys_bo
*bo
;
794 amdgpu_bo_handle
*handles
;
797 pipe_mutex_lock(ws
->global_bo_list_lock
);
799 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
801 pipe_mutex_unlock(ws
->global_bo_list_lock
);
802 amdgpu_cs_context_cleanup(cs
);
806 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, global_list_item
) {
807 assert(num
< ws
->num_buffers
);
808 handles
[num
++] = bo
->bo
;
811 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
813 &cs
->request
.resources
);
815 pipe_mutex_unlock(ws
->global_bo_list_lock
);
817 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_buffers
,
818 cs
->handles
, cs
->flags
,
819 &cs
->request
.resources
);
823 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
824 cs
->request
.resources
= NULL
;
825 amdgpu_fence_signalled(cs
->fence
);
829 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
832 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
834 fprintf(stderr
, "amdgpu: The CS has been rejected, "
835 "see dmesg for more information.\n");
837 amdgpu_fence_signalled(cs
->fence
);
840 uint64_t *user_fence
= NULL
;
841 if (amdgpu_cs_has_user_fence(cs
))
842 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
843 cs
->request
.fence_info
.offset
;
844 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
848 if (cs
->request
.resources
)
849 amdgpu_bo_list_destroy(cs
->request
.resources
);
852 for (i
= 0; i
< cs
->num_buffers
; i
++)
853 p_atomic_dec(&cs
->buffers
[i
].bo
->num_active_ioctls
);
855 amdgpu_cs_context_cleanup(cs
);
858 /* Make sure the previous submission is completed. */
859 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
861 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
863 /* Wait for any pending ioctl of this CS to complete. */
864 if (cs
->ctx
->ws
->thread
) {
865 /* wait and set the semaphore to "busy" */
866 pipe_semaphore_wait(&cs
->flush_completed
);
867 /* set the semaphore to "idle" */
868 pipe_semaphore_signal(&cs
->flush_completed
);
872 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", FALSE
)
874 static void amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
876 struct pipe_fence_handle
**fence
)
878 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
879 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
881 switch (cs
->ring_type
) {
883 /* pad DMA ring to 8 DWs */
884 while (rcs
->current
.cdw
& 7)
885 OUT_CS(rcs
, 0x00000000); /* NOP packet */
888 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
889 while (rcs
->current
.cdw
& 7)
890 OUT_CS(rcs
, 0xffff1000); /* type3 nop packet */
892 /* Also pad the const IB. */
893 if (cs
->const_ib
.ib_mapped
)
894 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
895 OUT_CS(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
897 if (cs
->const_preamble_ib
.ib_mapped
)
898 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
899 OUT_CS(&cs
->const_preamble_ib
.base
, 0xffff1000);
902 while (rcs
->current
.cdw
& 15)
903 OUT_CS(rcs
, 0x80000000); /* type2 nop packet */
909 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
910 fprintf(stderr
, "amdgpu: command stream overflowed\n");
913 /* If the CS is not empty or overflowed.... */
914 if (radeon_emitted(&cs
->main
.base
, 0) &&
915 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
916 !debug_get_option_noop()) {
917 struct amdgpu_cs_context
*cur
= cs
->csc
;
918 unsigned i
, num_buffers
= cur
->num_buffers
;
921 cur
->ib
[IB_MAIN
].size
= cs
->main
.base
.current
.cdw
;
922 cs
->main
.used_ib_space
+= cs
->main
.base
.current
.cdw
* 4;
923 cs
->main
.max_ib_size
= MAX2(cs
->main
.max_ib_size
, cs
->main
.base
.prev_dw
+ cs
->main
.base
.current
.cdw
);
925 if (cs
->const_ib
.ib_mapped
) {
926 cur
->ib
[IB_CONST
].size
= cs
->const_ib
.base
.current
.cdw
;
927 cs
->const_ib
.used_ib_space
+= cs
->const_ib
.base
.current
.cdw
* 4;
928 cs
->const_ib
.max_ib_size
=
929 MAX2(cs
->const_ib
.max_ib_size
, cs
->main
.base
.prev_dw
+ cs
->const_ib
.base
.current
.cdw
);
932 if (cs
->const_preamble_ib
.ib_mapped
) {
933 cur
->ib
[IB_CONST_PREAMBLE
].size
= cs
->const_preamble_ib
.base
.current
.cdw
;
934 cs
->const_preamble_ib
.used_ib_space
+= cs
->const_preamble_ib
.base
.current
.cdw
* 4;
935 cs
->const_preamble_ib
.max_ib_size
=
936 MAX2(cs
->const_preamble_ib
.max_ib_size
,
937 cs
->const_preamble_ib
.base
.prev_dw
+ cs
->const_preamble_ib
.base
.current
.cdw
);
940 /* Create a fence. */
941 amdgpu_fence_reference(&cur
->fence
, NULL
);
942 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
943 cur
->request
.ip_type
,
944 cur
->request
.ip_instance
,
947 amdgpu_fence_reference(fence
, cur
->fence
);
949 /* Prepare buffers. */
950 pipe_mutex_lock(ws
->bo_fence_lock
);
951 amdgpu_add_fence_dependencies(cs
);
952 for (i
= 0; i
< num_buffers
; i
++) {
953 p_atomic_inc(&cur
->buffers
[i
].bo
->num_active_ioctls
);
954 amdgpu_fence_reference(&cur
->buffers
[i
].bo
->fence
[cs
->ring_type
],
957 pipe_mutex_unlock(ws
->bo_fence_lock
);
959 amdgpu_cs_sync_flush(rcs
);
961 /* Swap command streams. "cst" is going to be submitted. */
966 if (ws
->thread
&& (flags
& RADEON_FLUSH_ASYNC
)) {
967 /* Set the semaphore to "busy". */
968 pipe_semaphore_wait(&cs
->flush_completed
);
969 amdgpu_ws_queue_cs(ws
, cs
);
971 amdgpu_cs_submit_ib(cs
);
974 amdgpu_cs_context_cleanup(cs
->csc
);
977 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
978 if (cs
->const_ib
.ib_mapped
)
979 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
980 if (cs
->const_preamble_ib
.ib_mapped
)
981 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
983 ws
->num_cs_flushes
++;
986 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
988 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
990 amdgpu_cs_sync_flush(rcs
);
991 pipe_semaphore_destroy(&cs
->flush_completed
);
992 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
993 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
994 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
995 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
996 amdgpu_destroy_cs_context(&cs
->csc1
);
997 amdgpu_destroy_cs_context(&cs
->csc2
);
1001 static boolean
amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1002 struct pb_buffer
*_buf
,
1003 enum radeon_bo_usage usage
)
1005 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1006 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1008 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1011 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1013 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1014 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1015 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1016 ws
->base
.cs_create
= amdgpu_cs_create
;
1017 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1018 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1019 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1020 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1021 ws
->base
.cs_lookup_buffer
= amdgpu_cs_lookup_buffer
;
1022 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1023 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1024 ws
->base
.cs_memory_below_limit
= amdgpu_cs_memory_below_limit
;
1025 ws
->base
.cs_query_memory_usage
= amdgpu_cs_query_memory_usage
;
1026 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1027 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1028 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1029 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1030 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1031 ws
->base
.fence_reference
= amdgpu_fence_reference
;