src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    fence->submission_in_progress = true;
  54    p_atomic_inc(&ctx->refcount);
  55    return (struct pipe_fence_handle *)fence;
  56 }
  57
  58 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  59                                 struct amdgpu_cs_request* request,
  60                                 uint64_t *user_fence_cpu_address)
  61 {
  62    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  63
  64    rfence->fence.fence = request->seq_no;
  65    rfence->user_fence_cpu_address = user_fence_cpu_address;
  66    rfence->submission_in_progress = false;
  67 }
  68
  69 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  70 {
  71    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  72
  73    rfence->signalled = true;
  74    rfence->submission_in_progress = false;
  75 }
  76
  77 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  78                        bool absolute)
  79 {
  80    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  81    uint32_t expired;
  82    int64_t abs_timeout;
  83    uint64_t *user_fence_cpu;
  84    int r;
  85
  86    if (rfence->signalled)
  87       return true;
  88
  89    if (absolute)
  90       abs_timeout = timeout;
  91    else
  92       abs_timeout = os_time_get_absolute_timeout(timeout);
  93
  94    /* The fence might not have a number assigned if its IB is being
  95     * submitted in the other thread right now. Wait until the submission
  96     * is done. */
  97    if (!os_wait_until_zero_abs_timeout(&rfence->submission_in_progress,
  98                                        abs_timeout))
  99       return false;
 100
 101    user_fence_cpu = rfence->user_fence_cpu_address;
 102    if (user_fence_cpu) {
 103       if (*user_fence_cpu >= rfence->fence.fence) {
 104          rfence->signalled = true;
 105          return true;
 106       }
 107
 108       /* No timeout, just query: no need for the ioctl. */
 109       if (!absolute && !timeout)
 110          return false;
 111    }
 112
 113    /* Now use the libdrm query. */
 114    r = amdgpu_cs_query_fence_status(&rfence->fence,
 115                                     abs_timeout,
 116                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 117                                     &expired);
 118    if (r) {
 119       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 120       return FALSE;
 121    }
 122
 123    if (expired) {
 124       /* This variable can only transition from false to true, so it doesn't
 125        * matter if threads race for it. */
 126       rfence->signalled = true;
 127       return true;
 128    }
 129    return false;
 130 }
 131
 132 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 133                                           struct pipe_fence_handle *fence,
 134                                           uint64_t timeout)
 135 {
 136    return amdgpu_fence_wait(fence, timeout, false);
 137 }
 138
 139 /* CONTEXTS */
 140
 141 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 142 {
 143    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 144    int r;
 145    struct amdgpu_bo_alloc_request alloc_buffer = {};
 146    amdgpu_bo_handle buf_handle;
 147
 148    if (!ctx)
 149       return NULL;
 150
 151    ctx->ws = amdgpu_winsys(ws);
 152    ctx->refcount = 1;
 153
 154    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 155    if (r) {
 156       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 157       goto error_create;
 158    }
 159
 160    alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
 161    alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
 162    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 163
 164    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 165    if (r) {
 166       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 167       goto error_user_fence_alloc;
 168    }
 169
 170    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 171    if (r) {
 172       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 173       goto error_user_fence_map;
 174    }
 175
 176    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 177    ctx->user_fence_bo = buf_handle;
 178
 179    return (struct radeon_winsys_ctx*)ctx;
 180
 181 error_user_fence_map:
 182    amdgpu_bo_free(buf_handle);
 183 error_user_fence_alloc:
 184    amdgpu_cs_ctx_free(ctx->ctx);
 185 error_create:
 186    FREE(ctx);
 187    return NULL;
 188 }
 189
 190 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 191 {
 192    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 193 }
 194
 195 static enum pipe_reset_status
 196 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 197 {
 198    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 199    uint32_t result, hangs;
 200    int r;
 201
 202    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 203    if (r) {
 204       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 205       return PIPE_NO_RESET;
 206    }
 207
 208    switch (result) {
 209    case AMDGPU_CTX_GUILTY_RESET:
 210       return PIPE_GUILTY_CONTEXT_RESET;
 211    case AMDGPU_CTX_INNOCENT_RESET:
 212       return PIPE_INNOCENT_CONTEXT_RESET;
 213    case AMDGPU_CTX_UNKNOWN_RESET:
 214       return PIPE_UNKNOWN_CONTEXT_RESET;
 215    case AMDGPU_CTX_NO_RESET:
 216    default:
 217       return PIPE_NO_RESET;
 218    }
 219 }
 220
 221 /* COMMAND SUBMISSION */
 222
 223 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
 224 {
 225    return cs->request.ip_type != AMDGPU_HW_IP_UVD &&
 226           cs->request.ip_type != AMDGPU_HW_IP_VCE;
 227 }
 228
 229 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
 230                               enum ib_type ib_type)
 231 {
 232    struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
 233    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 234     * and there is less waiting for buffers and fences. Proof:
 235     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 236     */
 237    struct amdgpu_ib *ib = NULL;
 238    struct amdgpu_cs_ib_info *info = &cs->csc->ib[ib_type];
 239    unsigned buffer_size, ib_size;
 240
 241    switch (ib_type) {
 242    case IB_CONST_PREAMBLE:
 243       ib = &cs->const_preamble_ib;
 244       buffer_size = 4 * 1024 * 4;
 245       ib_size = 1024 * 4;
 246       break;
 247    case IB_CONST:
 248       ib = &cs->const_ib;
 249       buffer_size = 512 * 1024 * 4;
 250       ib_size = 128 * 1024 * 4;
 251       break;
 252    case IB_MAIN:
 253       ib = &cs->main;
 254       buffer_size = 128 * 1024 * 4;
 255       ib_size = 20 * 1024 * 4;
 256       break;
 257    default:
 258       unreachable("unhandled IB type");
 259    }
 260
 261    ib->base.cdw = 0;
 262    ib->base.buf = NULL;
 263
 264    /* Allocate a new buffer for IBs if the current buffer is all used. */
 265    if (!ib->big_ib_buffer ||
 266        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 267
 268       pb_reference(&ib->big_ib_buffer, NULL);
 269       ib->ib_mapped = NULL;
 270       ib->used_ib_space = 0;
 271
 272       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 273                                             aws->info.gart_page_size,
 274                                             RADEON_DOMAIN_GTT,
 275                                             RADEON_FLAG_CPU_ACCESS);
 276       if (!ib->big_ib_buffer)
 277          return false;
 278
 279       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 280                                      PIPE_TRANSFER_WRITE);
 281       if (!ib->ib_mapped) {
 282          pb_reference(&ib->big_ib_buffer, NULL);
 283          return false;
 284       }
 285    }
 286
 287    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 288                          ib->used_ib_space;
 289    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 290    ib->base.max_dw = ib_size / 4;
 291    return true;
 292 }
 293
 294 static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
 295                                       enum ring_type ring_type)
 296 {
 297    int i;
 298
 299    switch (ring_type) {
 300    case RING_DMA:
 301       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 302       break;
 303
 304    case RING_UVD:
 305       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 306       break;
 307
 308    case RING_VCE:
 309       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 310       break;
 311
 312    case RING_COMPUTE:
 313       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 314       break;
 315
 316    default:
 317    case RING_GFX:
 318       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 319       break;
 320    }
 321
 322    cs->max_num_buffers = 512;
 323    cs->buffers = (struct amdgpu_cs_buffer*)
 324                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 325    if (!cs->buffers) {
 326       return FALSE;
 327    }
 328
 329    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 330    if (!cs->handles) {
 331       FREE(cs->buffers);
 332       return FALSE;
 333    }
 334
 335    cs->flags = CALLOC(1, cs->max_num_buffers);
 336    if (!cs->flags) {
 337       FREE(cs->handles);
 338       FREE(cs->buffers);
 339       return FALSE;
 340    }
 341
 342    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 343       cs->buffer_indices_hashlist[i] = -1;
 344    }
 345
 346    cs->request.number_of_ibs = 1;
 347    cs->request.ibs = &cs->ib[IB_MAIN];
 348
 349    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 350    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE |
 351                                      AMDGPU_IB_FLAG_PREAMBLE;
 352
 353    return TRUE;
 354 }
 355
 356 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs)
 357 {
 358    unsigned i;
 359
 360    for (i = 0; i < cs->num_buffers; i++) {
 361       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 362       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 363       cs->handles[i] = NULL;
 364       cs->flags[i] = 0;
 365    }
 366
 367    cs->num_buffers = 0;
 368    cs->used_gart = 0;
 369    cs->used_vram = 0;
 370    amdgpu_fence_reference(&cs->fence, NULL);
 371
 372    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 373       cs->buffer_indices_hashlist[i] = -1;
 374    }
 375 }
 376
 377 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs)
 378 {
 379    amdgpu_cs_context_cleanup(cs);
 380    FREE(cs->flags);
 381    FREE(cs->buffers);
 382    FREE(cs->handles);
 383    FREE(cs->request.dependencies);
 384 }
 385
 386
 387 static struct radeon_winsys_cs *
 388 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 389                  enum ring_type ring_type,
 390                  void (*flush)(void *ctx, unsigned flags,
 391                                struct pipe_fence_handle **fence),
 392                  void *flush_ctx)
 393 {
 394    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 395    struct amdgpu_cs *cs;
 396
 397    cs = CALLOC_STRUCT(amdgpu_cs);
 398    if (!cs) {
 399       return NULL;
 400    }
 401
 402    pipe_semaphore_init(&cs->flush_completed, 1);
 403
 404    cs->ctx = ctx;
 405    cs->flush_cs = flush;
 406    cs->flush_data = flush_ctx;
 407    cs->ring_type = ring_type;
 408
 409    if (!amdgpu_init_cs_context(&cs->csc1, ring_type)) {
 410       FREE(cs);
 411       return NULL;
 412    }
 413
 414    if (!amdgpu_init_cs_context(&cs->csc2, ring_type)) {
 415       amdgpu_destroy_cs_context(&cs->csc1);
 416       FREE(cs);
 417       return NULL;
 418    }
 419
 420    /* Set the first submission context as current. */
 421    cs->csc = &cs->csc1;
 422    cs->cst = &cs->csc2;
 423
 424    if (!amdgpu_get_new_ib(&ctx->ws->base, cs, IB_MAIN)) {
 425       amdgpu_destroy_cs_context(&cs->csc2);
 426       amdgpu_destroy_cs_context(&cs->csc1);
 427       FREE(cs);
 428       return NULL;
 429    }
 430
 431    p_atomic_inc(&ctx->ws->num_cs);
 432    return &cs->main.base;
 433 }
 434
 435 static struct radeon_winsys_cs *
 436 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 437 {
 438    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 439    struct amdgpu_winsys *ws = cs->ctx->ws;
 440
 441    /* only one const IB can be added */
 442    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 443       return NULL;
 444
 445    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST))
 446       return NULL;
 447
 448    cs->csc->request.number_of_ibs = 2;
 449    cs->csc->request.ibs = &cs->csc->ib[IB_CONST];
 450
 451    cs->cst->request.number_of_ibs = 2;
 452    cs->cst->request.ibs = &cs->cst->ib[IB_CONST];
 453
 454    return &cs->const_ib.base;
 455 }
 456
 457 static struct radeon_winsys_cs *
 458 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 459 {
 460    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 461    struct amdgpu_winsys *ws = cs->ctx->ws;
 462
 463    /* only one const preamble IB can be added and only when the const IB has
 464     * also been mapped */
 465    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 466        cs->const_preamble_ib.ib_mapped)
 467       return NULL;
 468
 469    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE))
 470       return NULL;
 471
 472    cs->csc->request.number_of_ibs = 3;
 473    cs->csc->request.ibs = &cs->csc->ib[IB_CONST_PREAMBLE];
 474
 475    cs->cst->request.number_of_ibs = 3;
 476    cs->cst->request.ibs = &cs->cst->ib[IB_CONST_PREAMBLE];
 477
 478    return &cs->const_preamble_ib.base;
 479 }
 480
 481 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 482
 483 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo)
 484 {
 485    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 486    int i = cs->buffer_indices_hashlist[hash];
 487
 488    /* not found or found */
 489    if (i == -1 || cs->buffers[i].bo == bo)
 490       return i;
 491
 492    /* Hash collision, look for the BO in the list of buffers linearly. */
 493    for (i = cs->num_buffers - 1; i >= 0; i--) {
 494       if (cs->buffers[i].bo == bo) {
 495          /* Put this buffer in the hash list.
 496           * This will prevent additional hash collisions if there are
 497           * several consecutive lookup_buffer calls for the same buffer.
 498           *
 499           * Example: Assuming buffers A,B,C collide in the hash list,
 500           * the following sequence of buffers:
 501           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 502           * will collide here: ^ and here:   ^,
 503           * meaning that we should get very few collisions in the end. */
 504          cs->buffer_indices_hashlist[hash] = i;
 505          return i;
 506       }
 507    }
 508    return -1;
 509 }
 510
 511 static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
 512                                  struct amdgpu_winsys_bo *bo,
 513                                  enum radeon_bo_usage usage,
 514                                  enum radeon_bo_domain domains,
 515                                  unsigned priority,
 516                                  enum radeon_bo_domain *added_domains)
 517 {
 518    struct amdgpu_cs_context *cs = acs->csc;
 519    struct amdgpu_cs_buffer *buffer;
 520    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 521    int i = -1;
 522
 523    assert(priority < 64);
 524    *added_domains = 0;
 525
 526    i = amdgpu_lookup_buffer(cs, bo);
 527
 528    if (i >= 0) {
 529       buffer = &cs->buffers[i];
 530       buffer->priority_usage |= 1llu << priority;
 531       buffer->usage |= usage;
 532       *added_domains = domains & ~buffer->domains;
 533       buffer->domains |= domains;
 534       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 535       return i;
 536    }
 537
 538    /* New buffer, check if the backing array is large enough. */
 539    if (cs->num_buffers >= cs->max_num_buffers) {
 540       uint32_t size;
 541       cs->max_num_buffers += 10;
 542
 543       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 544       cs->buffers = realloc(cs->buffers, size);
 545
 546       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 547       cs->handles = realloc(cs->handles, size);
 548
 549       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 550    }
 551
 552    /* Initialize the new buffer. */
 553    cs->buffers[cs->num_buffers].bo = NULL;
 554    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 555    cs->handles[cs->num_buffers] = bo->bo;
 556    cs->flags[cs->num_buffers] = priority / 4;
 557    p_atomic_inc(&bo->num_cs_references);
 558    buffer = &cs->buffers[cs->num_buffers];
 559    buffer->bo = bo;
 560    buffer->priority_usage = 1llu << priority;
 561    buffer->usage = usage;
 562    buffer->domains = domains;
 563
 564    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 565
 566    *added_domains = domains;
 567    return cs->num_buffers++;
 568 }
 569
 570 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 571                                     struct pb_buffer *buf,
 572                                     enum radeon_bo_usage usage,
 573                                     enum radeon_bo_domain domains,
 574                                     enum radeon_bo_priority priority)
 575 {
 576    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 577     * the buffer placement during command submission.
 578     */
 579    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 580    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 581    enum radeon_bo_domain added_domains;
 582    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 583                                      priority, &added_domains);
 584
 585    if (added_domains & RADEON_DOMAIN_VRAM)
 586       cs->csc->used_vram += bo->base.size;
 587    else if (added_domains & RADEON_DOMAIN_GTT)
 588       cs->csc->used_gart += bo->base.size;
 589
 590    return index;
 591 }
 592
 593 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 594                                struct pb_buffer *buf)
 595 {
 596    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 597
 598    return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
 599 }
 600
 601 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 602 {
 603    return TRUE;
 604 }
 605
 606 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 607 {
 608    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 609    struct amdgpu_winsys *ws = cs->ctx->ws;
 610
 611    vram += cs->csc->used_vram;
 612    gtt += cs->csc->used_gart;
 613
 614    /* Anything that goes above the VRAM size should go to GTT. */
 615    if (vram > ws->info.vram_size)
 616        gtt += vram - ws->info.vram_size;
 617
 618    /* Now we just need to check if we have enough GTT. */
 619    return gtt < ws->info.gart_size * 0.7;
 620 }
 621
 622 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
 623 {
 624    struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 625
 626    return cs->used_vram + cs->used_gart;
 627 }
 628
 629 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 630                                           struct radeon_bo_list_item *list)
 631 {
 632     struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 633     int i;
 634
 635     if (list) {
 636         for (i = 0; i < cs->num_buffers; i++) {
 637             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 638             list[i].vm_address = cs->buffers[i].bo->va;
 639             list[i].priority_usage = cs->buffers[i].priority_usage;
 640         }
 641     }
 642     return cs->num_buffers;
 643 }
 644
 645 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 646
 647 /* Since the kernel driver doesn't synchronize execution between different
 648  * rings automatically, we have to add fence dependencies manually.
 649  */
 650 static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs)
 651 {
 652    struct amdgpu_cs_context *cs = acs->csc;
 653    int i, j;
 654
 655    cs->request.number_of_dependencies = 0;
 656
 657    for (i = 0; i < cs->num_buffers; i++) {
 658       for (j = 0; j < RING_LAST; j++) {
 659          struct amdgpu_cs_fence *dep;
 660          unsigned idx;
 661
 662          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 663          if (!bo_fence)
 664             continue;
 665
 666          if (bo_fence->ctx == acs->ctx &&
 667              bo_fence->fence.ip_type == cs->request.ip_type &&
 668              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 669              bo_fence->fence.ring == cs->request.ring)
 670             continue;
 671
 672          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 673             continue;
 674
 675          if (bo_fence->submission_in_progress)
 676             os_wait_until_zero(&bo_fence->submission_in_progress,
 677                                PIPE_TIMEOUT_INFINITE);
 678
 679          idx = cs->request.number_of_dependencies++;
 680          if (idx >= cs->max_dependencies) {
 681             unsigned size;
 682
 683             cs->max_dependencies = idx + 8;
 684             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 685             cs->request.dependencies = realloc(cs->request.dependencies, size);
 686          }
 687
 688          dep = &cs->request.dependencies[idx];
 689          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 690       }
 691    }
 692 }
 693
 694 void amdgpu_cs_submit_ib(struct amdgpu_cs *acs)
 695 {
 696    struct amdgpu_winsys *ws = acs->ctx->ws;
 697    struct amdgpu_cs_context *cs = acs->cst;
 698    int i, r;
 699
 700    cs->request.fence_info.handle = NULL;
 701    if (amdgpu_cs_has_user_fence(cs)) {
 702         cs->request.fence_info.handle = acs->ctx->user_fence_bo;
 703         cs->request.fence_info.offset = acs->ring_type;
 704    }
 705
 706    /* Create the buffer list.
 707     * Use a buffer list containing all allocated buffers if requested.
 708     */
 709    if (debug_get_option_all_bos()) {
 710       struct amdgpu_winsys_bo *bo;
 711       amdgpu_bo_handle *handles;
 712       unsigned num = 0;
 713
 714       pipe_mutex_lock(ws->global_bo_list_lock);
 715
 716       handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 717       if (!handles) {
 718          pipe_mutex_unlock(ws->global_bo_list_lock);
 719          amdgpu_cs_context_cleanup(cs);
 720          return;
 721       }
 722
 723       LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 724          assert(num < ws->num_buffers);
 725          handles[num++] = bo->bo;
 726       }
 727
 728       r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 729                                 handles, NULL,
 730                                 &cs->request.resources);
 731       free(handles);
 732       pipe_mutex_unlock(ws->global_bo_list_lock);
 733    } else {
 734       r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 735                                 cs->handles, cs->flags,
 736                                 &cs->request.resources);
 737    }
 738
 739    if (r) {
 740       fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
 741       cs->request.resources = NULL;
 742       amdgpu_fence_signalled(cs->fence);
 743       goto cleanup;
 744    }
 745
 746    r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1);
 747    if (r) {
 748       if (r == -ENOMEM)
 749          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 750       else
 751          fprintf(stderr, "amdgpu: The CS has been rejected, "
 752                  "see dmesg for more information.\n");
 753
 754       amdgpu_fence_signalled(cs->fence);
 755    } else {
 756       /* Success. */
 757       uint64_t *user_fence = NULL;
 758       if (amdgpu_cs_has_user_fence(cs))
 759          user_fence = acs->ctx->user_fence_cpu_address_base +
 760                       cs->request.fence_info.offset;
 761       amdgpu_fence_submitted(cs->fence, &cs->request, user_fence);
 762    }
 763
 764    /* Cleanup. */
 765    if (cs->request.resources)
 766       amdgpu_bo_list_destroy(cs->request.resources);
 767
 768 cleanup:
 769    for (i = 0; i < cs->num_buffers; i++)
 770       p_atomic_dec(&cs->buffers[i].bo->num_active_ioctls);
 771
 772    amdgpu_cs_context_cleanup(cs);
 773 }
 774
 775 /* Make sure the previous submission is completed. */
 776 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 777 {
 778    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 779
 780    /* Wait for any pending ioctl of this CS to complete. */
 781    if (cs->ctx->ws->thread) {
 782       /* wait and set the semaphore to "busy" */
 783       pipe_semaphore_wait(&cs->flush_completed);
 784       /* set the semaphore to "idle" */
 785       pipe_semaphore_signal(&cs->flush_completed);
 786    }
 787 }
 788
 789 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 790
 791 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 792                             unsigned flags,
 793                             struct pipe_fence_handle **fence)
 794 {
 795    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 796    struct amdgpu_winsys *ws = cs->ctx->ws;
 797
 798    switch (cs->ring_type) {
 799    case RING_DMA:
 800       /* pad DMA ring to 8 DWs */
 801       while (rcs->cdw & 7)
 802          OUT_CS(rcs, 0x00000000); /* NOP packet */
 803       break;
 804    case RING_GFX:
 805       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 806       while (rcs->cdw & 7)
 807          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 808
 809       /* Also pad the const IB. */
 810       if (cs->const_ib.ib_mapped)
 811          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 812             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 813
 814       if (cs->const_preamble_ib.ib_mapped)
 815          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 816             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 817       break;
 818    case RING_UVD:
 819       while (rcs->cdw & 15)
 820          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 821       break;
 822    default:
 823       break;
 824    }
 825
 826    if (rcs->cdw > rcs->max_dw) {
 827       fprintf(stderr, "amdgpu: command stream overflowed\n");
 828    }
 829
 830    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 831                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 832
 833    if (cs->const_ib.ib_mapped)
 834       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 835                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 836
 837    if (cs->const_preamble_ib.ib_mapped)
 838       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 839                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 840
 841    /* If the CS is not empty or overflowed.... */
 842    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw &&
 843        !debug_get_option_noop()) {
 844       struct amdgpu_cs_context *cur = cs->csc;
 845       unsigned i, num_buffers = cur->num_buffers;
 846
 847       /* Set IB sizes. */
 848       cur->ib[IB_MAIN].size = cs->main.base.cdw;
 849       cs->main.used_ib_space += cs->main.base.cdw * 4;
 850
 851       if (cs->const_ib.ib_mapped) {
 852          cur->ib[IB_CONST].size = cs->const_ib.base.cdw;
 853          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 854       }
 855
 856       if (cs->const_preamble_ib.ib_mapped) {
 857          cur->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 858          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 859       }
 860
 861       /* Create a fence. */
 862       amdgpu_fence_reference(&cur->fence, NULL);
 863       cur->fence = amdgpu_fence_create(cs->ctx,
 864                                            cur->request.ip_type,
 865                                            cur->request.ip_instance,
 866                                            cur->request.ring);
 867       if (fence)
 868          amdgpu_fence_reference(fence, cur->fence);
 869
 870       /* Prepare buffers. */
 871       pipe_mutex_lock(ws->bo_fence_lock);
 872       amdgpu_add_fence_dependencies(cs);
 873       for (i = 0; i < num_buffers; i++) {
 874          p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls);
 875          amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type],
 876                                 cur->fence);
 877       }
 878       pipe_mutex_unlock(ws->bo_fence_lock);
 879
 880       amdgpu_cs_sync_flush(rcs);
 881
 882       /* Swap command streams. "cst" is going to be submitted. */
 883       cs->csc = cs->cst;
 884       cs->cst = cur;
 885
 886       /* Submit. */
 887       if (ws->thread && (flags & RADEON_FLUSH_ASYNC)) {
 888          /* Set the semaphore to "busy". */
 889          pipe_semaphore_wait(&cs->flush_completed);
 890          amdgpu_ws_queue_cs(ws, cs);
 891       } else {
 892          amdgpu_cs_submit_ib(cs);
 893       }
 894    } else {
 895       amdgpu_cs_context_cleanup(cs->csc);
 896    }
 897
 898    amdgpu_get_new_ib(&ws->base, cs, IB_MAIN);
 899    if (cs->const_ib.ib_mapped)
 900       amdgpu_get_new_ib(&ws->base, cs, IB_CONST);
 901    if (cs->const_preamble_ib.ib_mapped)
 902       amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE);
 903
 904    ws->num_cs_flushes++;
 905 }
 906
 907 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 908 {
 909    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 910
 911    amdgpu_cs_sync_flush(rcs);
 912    pipe_semaphore_destroy(&cs->flush_completed);
 913    p_atomic_dec(&cs->ctx->ws->num_cs);
 914    pb_reference(&cs->main.big_ib_buffer, NULL);
 915    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 916    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 917    amdgpu_destroy_cs_context(&cs->csc1);
 918    amdgpu_destroy_cs_context(&cs->csc2);
 919    FREE(cs);
 920 }
 921
 922 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 923                                        struct pb_buffer *_buf,
 924                                        enum radeon_bo_usage usage)
 925 {
 926    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 927    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 928
 929    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 930 }
 931
 932 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 933 {
 934    ws->base.ctx_create = amdgpu_ctx_create;
 935    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 936    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 937    ws->base.cs_create = amdgpu_cs_create;
 938    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 939    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 940    ws->base.cs_destroy = amdgpu_cs_destroy;
 941    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 942    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 943    ws->base.cs_validate = amdgpu_cs_validate;
 944    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 945    ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
 946    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 947    ws->base.cs_flush = amdgpu_cs_flush;
 948    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 949    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 950    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 951    ws->base.fence_reference = amdgpu_fence_reference;
 952 }