src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu && *user_fence_cpu >= rfence->fence.fence) {
  93         rfence->signalled = true;
  94         return true;
  95    }
  96    /* Now use the libdrm query. */
  97    r = amdgpu_cs_query_fence_status(&rfence->fence,
  98                                     abs_timeout,
  99                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 100                                     &expired);
 101    if (r) {
 102       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 103       return FALSE;
 104    }
 105
 106    if (expired) {
 107       /* This variable can only transition from false to true, so it doesn't
 108        * matter if threads race for it. */
 109       rfence->signalled = true;
 110       return true;
 111    }
 112    return false;
 113 }
 114
 115 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 116                                           struct pipe_fence_handle *fence,
 117                                           uint64_t timeout)
 118 {
 119    return amdgpu_fence_wait(fence, timeout, false);
 120 }
 121
 122 /* CONTEXTS */
 123
 124 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 125 {
 126    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 127    int r;
 128    struct amdgpu_bo_alloc_request alloc_buffer = {};
 129    amdgpu_bo_handle buf_handle;
 130
 131    ctx->ws = amdgpu_winsys(ws);
 132    ctx->refcount = 1;
 133
 134    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 137       FREE(ctx);
 138       return NULL;
 139    }
 140
 141    alloc_buffer.alloc_size = 4 * 1024;
 142    alloc_buffer.phys_alignment = 4 *1024;
 143    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 144
 145    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 148       amdgpu_cs_ctx_free(ctx->ctx);
 149       FREE(ctx);
 150       return NULL;
 151    }
 152
 153    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 154    if (r) {
 155       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 156       amdgpu_bo_free(buf_handle);
 157       amdgpu_cs_ctx_free(ctx->ctx);
 158       FREE(ctx);
 159       return NULL;
 160    }
 161
 162    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 163    ctx->user_fence_bo = buf_handle;
 164
 165    return (struct radeon_winsys_ctx*)ctx;
 166 }
 167
 168 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 169 {
 170    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 171 }
 172
 173 static enum pipe_reset_status
 174 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 175 {
 176    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 177    uint32_t result, hangs;
 178    int r;
 179
 180    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 181    if (r) {
 182       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 183       return PIPE_NO_RESET;
 184    }
 185
 186    switch (result) {
 187    case AMDGPU_CTX_GUILTY_RESET:
 188       return PIPE_GUILTY_CONTEXT_RESET;
 189    case AMDGPU_CTX_INNOCENT_RESET:
 190       return PIPE_INNOCENT_CONTEXT_RESET;
 191    case AMDGPU_CTX_UNKNOWN_RESET:
 192       return PIPE_UNKNOWN_CONTEXT_RESET;
 193    case AMDGPU_CTX_NO_RESET:
 194    default:
 195       return PIPE_NO_RESET;
 196    }
 197 }
 198
 199 /* COMMAND SUBMISSION */
 200
 201 static bool amdgpu_get_new_ib(struct amdgpu_cs *cs)
 202 {
 203    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 204     * and there is less waiting for buffers and fences. Proof:
 205     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 206     */
 207    const unsigned buffer_size = 128 * 1024 * 4;
 208    const unsigned ib_size = 20 * 1024 * 4;
 209
 210    cs->base.cdw = 0;
 211    cs->base.buf = NULL;
 212
 213    /* Allocate a new buffer for IBs if the current buffer is all used. */
 214    if (!cs->big_ib_buffer ||
 215        cs->used_ib_space + ib_size > cs->big_ib_buffer->size) {
 216       struct radeon_winsys *ws = &cs->ctx->ws->base;
 217
 218       pb_reference(&cs->big_ib_buffer, NULL);
 219       cs->big_ib_winsys_buffer = NULL;
 220       cs->ib_mapped = NULL;
 221       cs->used_ib_space = 0;
 222
 223       cs->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 224                                             4096, true,
 225                                             RADEON_DOMAIN_GTT,
 226                                             RADEON_FLAG_CPU_ACCESS);
 227       if (!cs->big_ib_buffer)
 228          return false;
 229
 230       cs->ib_mapped = ws->buffer_map(cs->big_ib_buffer, NULL,
 231                                      PIPE_TRANSFER_WRITE);
 232       if (!cs->ib_mapped) {
 233          pb_reference(&cs->big_ib_buffer, NULL);
 234          return false;
 235       }
 236
 237       cs->big_ib_winsys_buffer = (struct amdgpu_winsys_bo*)cs->big_ib_buffer;
 238    }
 239
 240    cs->ib.ib_mc_address = cs->big_ib_winsys_buffer->va + cs->used_ib_space;
 241    cs->base.buf = (uint32_t*)(cs->ib_mapped + cs->used_ib_space);
 242    cs->base.max_dw = ib_size / 4;
 243    return true;
 244 }
 245
 246 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 247                                       enum ring_type ring_type)
 248 {
 249    int i;
 250
 251    switch (ring_type) {
 252    case RING_DMA:
 253       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 254       break;
 255
 256    case RING_UVD:
 257       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 258       break;
 259
 260    case RING_VCE:
 261       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 262       break;
 263
 264    case RING_COMPUTE:
 265       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 266       break;
 267
 268    default:
 269    case RING_GFX:
 270       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 271       break;
 272    }
 273
 274    cs->request.number_of_ibs = 1;
 275    cs->request.ibs = &cs->ib;
 276
 277    cs->max_num_buffers = 512;
 278    cs->buffers = (struct amdgpu_cs_buffer*)
 279                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 280    if (!cs->buffers) {
 281       return FALSE;
 282    }
 283
 284    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 285    if (!cs->handles) {
 286       FREE(cs->buffers);
 287       return FALSE;
 288    }
 289
 290    cs->flags = CALLOC(1, cs->max_num_buffers);
 291    if (!cs->flags) {
 292       FREE(cs->handles);
 293       FREE(cs->buffers);
 294       return FALSE;
 295    }
 296
 297    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 298       cs->buffer_indices_hashlist[i] = -1;
 299    }
 300    return TRUE;
 301 }
 302
 303 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 304 {
 305    unsigned i;
 306
 307    for (i = 0; i < cs->num_buffers; i++) {
 308       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 309       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 310       cs->handles[i] = NULL;
 311       cs->flags[i] = 0;
 312    }
 313
 314    cs->num_buffers = 0;
 315    cs->used_gart = 0;
 316    cs->used_vram = 0;
 317
 318    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 319       cs->buffer_indices_hashlist[i] = -1;
 320    }
 321 }
 322
 323 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 324 {
 325    amdgpu_cs_context_cleanup(cs);
 326    FREE(cs->flags);
 327    FREE(cs->buffers);
 328    FREE(cs->handles);
 329    FREE(cs->request.dependencies);
 330 }
 331
 332
 333 static struct radeon_winsys_cs *
 334 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 335                  enum ring_type ring_type,
 336                  void (*flush)(void *ctx, unsigned flags,
 337                                struct pipe_fence_handle **fence),
 338                  void *flush_ctx,
 339                  struct pb_buffer *trace_buf)
 340 {
 341    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 342    struct amdgpu_cs *cs;
 343
 344    cs = CALLOC_STRUCT(amdgpu_cs);
 345    if (!cs) {
 346       return NULL;
 347    }
 348
 349    cs->ctx = ctx;
 350    cs->flush_cs = flush;
 351    cs->flush_data = flush_ctx;
 352    cs->base.ring_type = ring_type;
 353
 354    if (!amdgpu_init_cs_context(cs, ring_type)) {
 355       FREE(cs);
 356       return NULL;
 357    }
 358
 359    if (!amdgpu_get_new_ib(cs)) {
 360       amdgpu_destroy_cs_context(cs);
 361       FREE(cs);
 362       return NULL;
 363    }
 364
 365    p_atomic_inc(&ctx->ws->num_cs);
 366    return &cs->base;
 367 }
 368
 369 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 370
 371 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 372 {
 373    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 374    int i = cs->buffer_indices_hashlist[hash];
 375
 376    /* not found or found */
 377    if (i == -1 || cs->buffers[i].bo == bo)
 378       return i;
 379
 380    /* Hash collision, look for the BO in the list of buffers linearly. */
 381    for (i = cs->num_buffers - 1; i >= 0; i--) {
 382       if (cs->buffers[i].bo == bo) {
 383          /* Put this buffer in the hash list.
 384           * This will prevent additional hash collisions if there are
 385           * several consecutive lookup_buffer calls for the same buffer.
 386           *
 387           * Example: Assuming buffers A,B,C collide in the hash list,
 388           * the following sequence of buffers:
 389           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 390           * will collide here: ^ and here:   ^,
 391           * meaning that we should get very few collisions in the end. */
 392          cs->buffer_indices_hashlist[hash] = i;
 393          return i;
 394       }
 395    }
 396    return -1;
 397 }
 398
 399 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 400                                  struct amdgpu_winsys_bo *bo,
 401                                  enum radeon_bo_usage usage,
 402                                  enum radeon_bo_domain domains,
 403                                  unsigned priority,
 404                                  enum radeon_bo_domain *added_domains)
 405 {
 406    struct amdgpu_cs_buffer *buffer;
 407    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 408    int i = -1;
 409
 410    assert(priority < 64);
 411    *added_domains = 0;
 412
 413    i = amdgpu_lookup_buffer(cs, bo);
 414
 415    if (i >= 0) {
 416       buffer = &cs->buffers[i];
 417       buffer->priority_usage |= 1llu << priority;
 418       buffer->usage |= usage;
 419       *added_domains = domains & ~buffer->domains;
 420       buffer->domains |= domains;
 421       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 422       return i;
 423    }
 424
 425    /* New buffer, check if the backing array is large enough. */
 426    if (cs->num_buffers >= cs->max_num_buffers) {
 427       uint32_t size;
 428       cs->max_num_buffers += 10;
 429
 430       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 431       cs->buffers = realloc(cs->buffers, size);
 432
 433       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 434       cs->handles = realloc(cs->handles, size);
 435
 436       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 437    }
 438
 439    /* Initialize the new buffer. */
 440    cs->buffers[cs->num_buffers].bo = NULL;
 441    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 442    cs->handles[cs->num_buffers] = bo->bo;
 443    cs->flags[cs->num_buffers] = priority / 4;
 444    p_atomic_inc(&bo->num_cs_references);
 445    buffer = &cs->buffers[cs->num_buffers];
 446    buffer->bo = bo;
 447    buffer->priority_usage = 1llu << priority;
 448    buffer->usage = usage;
 449    buffer->domains = domains;
 450
 451    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 452
 453    *added_domains = domains;
 454    return cs->num_buffers++;
 455 }
 456
 457 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 458                                     struct pb_buffer *buf,
 459                                     enum radeon_bo_usage usage,
 460                                     enum radeon_bo_domain domains,
 461                                     enum radeon_bo_priority priority)
 462 {
 463    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 464     * the buffer placement during command submission.
 465     */
 466    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 467    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 468    enum radeon_bo_domain added_domains;
 469    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 470                                      priority, &added_domains);
 471
 472    if (added_domains & RADEON_DOMAIN_GTT)
 473       cs->used_gart += bo->base.size;
 474    if (added_domains & RADEON_DOMAIN_VRAM)
 475       cs->used_vram += bo->base.size;
 476
 477    return index;
 478 }
 479
 480 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 481                                struct pb_buffer *buf)
 482 {
 483    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 484
 485    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 486 }
 487
 488 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 489 {
 490    return TRUE;
 491 }
 492
 493 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 494 {
 495    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 496    boolean status =
 497          (cs->used_gart + gtt) < cs->ctx->ws->info.gart_size * 0.7 &&
 498          (cs->used_vram + vram) < cs->ctx->ws->info.vram_size * 0.7;
 499
 500    return status;
 501 }
 502
 503 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 504                                           struct radeon_bo_list_item *list)
 505 {
 506     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 507     int i;
 508
 509     if (list) {
 510         for (i = 0; i < cs->num_buffers; i++) {
 511             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 512             list[i].vm_address = cs->buffers[i].bo->va;
 513             list[i].priority_usage = cs->buffers[i].priority_usage;
 514         }
 515     }
 516     return cs->num_buffers;
 517 }
 518
 519 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 520                                     struct pipe_fence_handle **out_fence)
 521 {
 522    struct amdgpu_winsys *ws = cs->ctx->ws;
 523    struct pipe_fence_handle *fence;
 524    int i, j, r;
 525
 526    /* Create a fence. */
 527    fence = amdgpu_fence_create(cs->ctx,
 528                                cs->request.ip_type,
 529                                cs->request.ip_instance,
 530                                cs->request.ring);
 531    if (out_fence)
 532       amdgpu_fence_reference(out_fence, fence);
 533
 534    cs->request.number_of_dependencies = 0;
 535
 536    /* Since the kernel driver doesn't synchronize execution between different
 537     * rings automatically, we have to add fence dependencies manually. */
 538    pipe_mutex_lock(ws->bo_fence_lock);
 539    for (i = 0; i < cs->num_buffers; i++) {
 540       for (j = 0; j < RING_LAST; j++) {
 541          struct amdgpu_cs_fence *dep;
 542          unsigned idx;
 543
 544          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 545          if (!bo_fence)
 546             continue;
 547
 548          if (bo_fence->ctx == cs->ctx &&
 549              bo_fence->fence.ip_type == cs->request.ip_type &&
 550              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 551              bo_fence->fence.ring == cs->request.ring)
 552             continue;
 553
 554          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 555             continue;
 556
 557          idx = cs->request.number_of_dependencies++;
 558          if (idx >= cs->max_dependencies) {
 559             unsigned size;
 560
 561             cs->max_dependencies = idx + 8;
 562             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 563             cs->request.dependencies = realloc(cs->request.dependencies, size);
 564          }
 565
 566          dep = &cs->request.dependencies[idx];
 567          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 568       }
 569    }
 570
 571    cs->request.fence_info.handle = NULL;
 572    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 573         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 574         cs->request.fence_info.offset = cs->base.ring_type;
 575    }
 576
 577    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 578    if (r) {
 579       if (r == -ENOMEM)
 580          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 581       else
 582          fprintf(stderr, "amdgpu: The CS has been rejected, "
 583                  "see dmesg for more information.\n");
 584
 585       amdgpu_fence_signalled(fence);
 586    } else {
 587       /* Success. */
 588       uint64_t *user_fence = NULL;
 589       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 590          user_fence = cs->ctx->user_fence_cpu_address_base +
 591                       cs->request.fence_info.offset;
 592       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 593
 594       for (i = 0; i < cs->num_buffers; i++)
 595          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->base.ring_type],
 596                                 fence);
 597    }
 598    pipe_mutex_unlock(ws->bo_fence_lock);
 599    amdgpu_fence_reference(&fence, NULL);
 600 }
 601
 602 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 603 {
 604    /* no-op */
 605 }
 606
 607 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 608 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 609
 610 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 611                             unsigned flags,
 612                             struct pipe_fence_handle **fence,
 613                             uint32_t cs_trace_id)
 614 {
 615    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 616    struct amdgpu_winsys *ws = cs->ctx->ws;
 617
 618    switch (cs->base.ring_type) {
 619    case RING_DMA:
 620       /* pad DMA ring to 8 DWs */
 621       while (rcs->cdw & 7)
 622          OUT_CS(&cs->base, 0x00000000); /* NOP packet */
 623       break;
 624    case RING_GFX:
 625       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 626       while (rcs->cdw & 7)
 627          OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
 628       break;
 629    case RING_UVD:
 630       while (rcs->cdw & 15)
 631          OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
 632       break;
 633    default:
 634       break;
 635    }
 636
 637    if (rcs->cdw > rcs->max_dw) {
 638       fprintf(stderr, "amdgpu: command stream overflowed\n");
 639    }
 640
 641    amdgpu_cs_add_buffer(rcs, (void*)cs->big_ib_winsys_buffer,
 642                        RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 643
 644    /* If the CS is not empty or overflowed.... */
 645    if (cs->base.cdw && cs->base.cdw <= cs->base.max_dw && !debug_get_option_noop()) {
 646       int r;
 647
 648       /* Use a buffer list containing all allocated buffers if requested. */
 649       if (debug_get_option_all_bos()) {
 650          struct amdgpu_winsys_bo *bo;
 651          amdgpu_bo_handle *handles;
 652          unsigned num = 0;
 653
 654          pipe_mutex_lock(ws->global_bo_list_lock);
 655
 656          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 657          if (!handles) {
 658             pipe_mutex_unlock(ws->global_bo_list_lock);
 659             goto cleanup;
 660          }
 661
 662          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 663             assert(num < ws->num_buffers);
 664             handles[num++] = bo->bo;
 665          }
 666
 667          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 668                                    handles, NULL,
 669                                    &cs->request.resources);
 670          free(handles);
 671          pipe_mutex_unlock(ws->global_bo_list_lock);
 672       } else {
 673          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 674                                    cs->handles, cs->flags,
 675                                    &cs->request.resources);
 676       }
 677
 678       if (r) {
 679          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 680          cs->request.resources = NULL;
 681          goto cleanup;
 682       }
 683
 684       cs->ib.size = cs->base.cdw;
 685       cs->used_ib_space += cs->base.cdw * 4;
 686
 687       amdgpu_cs_do_submission(cs, fence);
 688
 689       /* Cleanup. */
 690       if (cs->request.resources)
 691          amdgpu_bo_list_destroy(cs->request.resources);
 692    }
 693
 694 cleanup:
 695    amdgpu_cs_context_cleanup(cs);
 696    amdgpu_get_new_ib(cs);
 697
 698    ws->num_cs_flushes++;
 699 }
 700
 701 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 702 {
 703    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 704
 705    amdgpu_destroy_cs_context(cs);
 706    p_atomic_dec(&cs->ctx->ws->num_cs);
 707    pb_reference(&cs->big_ib_buffer, NULL);
 708    FREE(cs);
 709 }
 710
 711 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 712                                        struct pb_buffer *_buf,
 713                                        enum radeon_bo_usage usage)
 714 {
 715    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 716    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 717
 718    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 719 }
 720
 721 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 722 {
 723    ws->base.ctx_create = amdgpu_ctx_create;
 724    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 725    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 726    ws->base.cs_create = amdgpu_cs_create;
 727    ws->base.cs_destroy = amdgpu_cs_destroy;
 728    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 729    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 730    ws->base.cs_validate = amdgpu_cs_validate;
 731    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 732    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 733    ws->base.cs_flush = amdgpu_cs_flush;
 734    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 735    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 736    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 737    ws->base.fence_reference = amdgpu_fence_reference;
 738 }