src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    fence->submission_in_progress = true;
  54    p_atomic_inc(&ctx->refcount);
  55    return (struct pipe_fence_handle *)fence;
  56 }
  57
  58 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  59                                 struct amdgpu_cs_request* request,
  60                                 uint64_t *user_fence_cpu_address)
  61 {
  62    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  63
  64    rfence->fence.fence = request->seq_no;
  65    rfence->user_fence_cpu_address = user_fence_cpu_address;
  66    rfence->submission_in_progress = false;
  67 }
  68
  69 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  70 {
  71    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  72
  73    rfence->signalled = true;
  74    rfence->submission_in_progress = false;
  75 }
  76
  77 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  78                        bool absolute)
  79 {
  80    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  81    uint32_t expired;
  82    int64_t abs_timeout;
  83    uint64_t *user_fence_cpu;
  84    int r;
  85
  86    if (rfence->signalled)
  87       return true;
  88
  89    if (absolute)
  90       abs_timeout = timeout;
  91    else
  92       abs_timeout = os_time_get_absolute_timeout(timeout);
  93
  94    /* The fence might not have a number assigned if its IB is being
  95     * submitted in the other thread right now. Wait until the submission
  96     * is done. */
  97    if (!os_wait_until_zero_abs_timeout(&rfence->submission_in_progress,
  98                                        abs_timeout))
  99       return false;
 100
 101    user_fence_cpu = rfence->user_fence_cpu_address;
 102    if (user_fence_cpu) {
 103       if (*user_fence_cpu >= rfence->fence.fence) {
 104          rfence->signalled = true;
 105          return true;
 106       }
 107
 108       /* No timeout, just query: no need for the ioctl. */
 109       if (!absolute && !timeout)
 110          return false;
 111    }
 112
 113    /* Now use the libdrm query. */
 114    r = amdgpu_cs_query_fence_status(&rfence->fence,
 115                                     abs_timeout,
 116                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 117                                     &expired);
 118    if (r) {
 119       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 120       return FALSE;
 121    }
 122
 123    if (expired) {
 124       /* This variable can only transition from false to true, so it doesn't
 125        * matter if threads race for it. */
 126       rfence->signalled = true;
 127       return true;
 128    }
 129    return false;
 130 }
 131
 132 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 133                                           struct pipe_fence_handle *fence,
 134                                           uint64_t timeout)
 135 {
 136    return amdgpu_fence_wait(fence, timeout, false);
 137 }
 138
 139 /* CONTEXTS */
 140
 141 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 142 {
 143    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 144    int r;
 145    struct amdgpu_bo_alloc_request alloc_buffer = {};
 146    amdgpu_bo_handle buf_handle;
 147
 148    if (!ctx)
 149       return NULL;
 150
 151    ctx->ws = amdgpu_winsys(ws);
 152    ctx->refcount = 1;
 153
 154    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 155    if (r) {
 156       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 157       goto error_create;
 158    }
 159
 160    alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
 161    alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
 162    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 163
 164    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 165    if (r) {
 166       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 167       goto error_user_fence_alloc;
 168    }
 169
 170    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 171    if (r) {
 172       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 173       goto error_user_fence_map;
 174    }
 175
 176    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 177    ctx->user_fence_bo = buf_handle;
 178
 179    return (struct radeon_winsys_ctx*)ctx;
 180
 181 error_user_fence_map:
 182    amdgpu_bo_free(buf_handle);
 183 error_user_fence_alloc:
 184    amdgpu_cs_ctx_free(ctx->ctx);
 185 error_create:
 186    FREE(ctx);
 187    return NULL;
 188 }
 189
 190 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 191 {
 192    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 193 }
 194
 195 static enum pipe_reset_status
 196 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 197 {
 198    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 199    uint32_t result, hangs;
 200    int r;
 201
 202    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 203    if (r) {
 204       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 205       return PIPE_NO_RESET;
 206    }
 207
 208    switch (result) {
 209    case AMDGPU_CTX_GUILTY_RESET:
 210       return PIPE_GUILTY_CONTEXT_RESET;
 211    case AMDGPU_CTX_INNOCENT_RESET:
 212       return PIPE_INNOCENT_CONTEXT_RESET;
 213    case AMDGPU_CTX_UNKNOWN_RESET:
 214       return PIPE_UNKNOWN_CONTEXT_RESET;
 215    case AMDGPU_CTX_NO_RESET:
 216    default:
 217       return PIPE_NO_RESET;
 218    }
 219 }
 220
 221 /* COMMAND SUBMISSION */
 222
 223 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
 224 {
 225    return cs->request.ip_type != AMDGPU_HW_IP_UVD &&
 226           cs->request.ip_type != AMDGPU_HW_IP_VCE;
 227 }
 228
 229 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo)
 230 {
 231    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 232    int i = cs->buffer_indices_hashlist[hash];
 233
 234    /* not found or found */
 235    if (i == -1 || cs->buffers[i].bo == bo)
 236       return i;
 237
 238    /* Hash collision, look for the BO in the list of buffers linearly. */
 239    for (i = cs->num_buffers - 1; i >= 0; i--) {
 240       if (cs->buffers[i].bo == bo) {
 241          /* Put this buffer in the hash list.
 242           * This will prevent additional hash collisions if there are
 243           * several consecutive lookup_buffer calls for the same buffer.
 244           *
 245           * Example: Assuming buffers A,B,C collide in the hash list,
 246           * the following sequence of buffers:
 247           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 248           * will collide here: ^ and here:   ^,
 249           * meaning that we should get very few collisions in the end. */
 250          cs->buffer_indices_hashlist[hash] = i;
 251          return i;
 252       }
 253    }
 254    return -1;
 255 }
 256
 257 static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
 258                                  struct amdgpu_winsys_bo *bo,
 259                                  enum radeon_bo_usage usage,
 260                                  enum radeon_bo_domain domains,
 261                                  unsigned priority,
 262                                  enum radeon_bo_domain *added_domains)
 263 {
 264    struct amdgpu_cs_context *cs = acs->csc;
 265    struct amdgpu_cs_buffer *buffer;
 266    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 267    int i = -1;
 268
 269    assert(priority < 64);
 270    *added_domains = 0;
 271
 272    i = amdgpu_lookup_buffer(cs, bo);
 273
 274    if (i >= 0) {
 275       buffer = &cs->buffers[i];
 276       buffer->priority_usage |= 1llu << priority;
 277       buffer->usage |= usage;
 278       *added_domains = domains & ~buffer->domains;
 279       buffer->domains |= domains;
 280       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 281       return i;
 282    }
 283
 284    /* New buffer, check if the backing array is large enough. */
 285    if (cs->num_buffers >= cs->max_num_buffers) {
 286       uint32_t size;
 287       cs->max_num_buffers += 10;
 288
 289       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 290       cs->buffers = realloc(cs->buffers, size);
 291
 292       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 293       cs->handles = realloc(cs->handles, size);
 294
 295       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 296    }
 297
 298    /* Initialize the new buffer. */
 299    cs->buffers[cs->num_buffers].bo = NULL;
 300    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 301    cs->handles[cs->num_buffers] = bo->bo;
 302    cs->flags[cs->num_buffers] = priority / 4;
 303    p_atomic_inc(&bo->num_cs_references);
 304    buffer = &cs->buffers[cs->num_buffers];
 305    buffer->bo = bo;
 306    buffer->priority_usage = 1llu << priority;
 307    buffer->usage = usage;
 308    buffer->domains = domains;
 309
 310    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 311
 312    *added_domains = domains;
 313    return cs->num_buffers++;
 314 }
 315
 316 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 317                                     struct pb_buffer *buf,
 318                                     enum radeon_bo_usage usage,
 319                                     enum radeon_bo_domain domains,
 320                                     enum radeon_bo_priority priority)
 321 {
 322    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 323     * the buffer placement during command submission.
 324     */
 325    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 326    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 327    enum radeon_bo_domain added_domains;
 328    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 329                                      priority, &added_domains);
 330
 331    if (added_domains & RADEON_DOMAIN_VRAM)
 332       cs->csc->used_vram += bo->base.size;
 333    else if (added_domains & RADEON_DOMAIN_GTT)
 334       cs->csc->used_gart += bo->base.size;
 335
 336    return index;
 337 }
 338
 339 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib,
 340                                  unsigned buffer_size)
 341 {
 342    struct pb_buffer *pb;
 343    uint8_t *mapped;
 344
 345    pb = ws->base.buffer_create(&ws->base, buffer_size,
 346                                ws->info.gart_page_size,
 347                                RADEON_DOMAIN_GTT,
 348                                RADEON_FLAG_CPU_ACCESS);
 349    if (!pb)
 350       return false;
 351
 352    mapped = ws->base.buffer_map(pb, NULL, PIPE_TRANSFER_WRITE);
 353    if (!mapped) {
 354       pb_reference(&pb, NULL);
 355       return false;
 356    }
 357
 358    pb_reference(&ib->big_ib_buffer, pb);
 359    pb_reference(&pb, NULL);
 360
 361    ib->ib_mapped = mapped;
 362    ib->used_ib_space = 0;
 363
 364    return true;
 365 }
 366
 367 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
 368                               enum ib_type ib_type)
 369 {
 370    struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
 371    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 372     * and there is less waiting for buffers and fences. Proof:
 373     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 374     */
 375    struct amdgpu_ib *ib = NULL;
 376    struct amdgpu_cs_ib_info *info = &cs->csc->ib[ib_type];
 377    unsigned buffer_size, ib_size;
 378
 379    switch (ib_type) {
 380    case IB_CONST_PREAMBLE:
 381       ib = &cs->const_preamble_ib;
 382       buffer_size = 4 * 1024 * 4;
 383       ib_size = 1024 * 4;
 384       break;
 385    case IB_CONST:
 386       ib = &cs->const_ib;
 387       buffer_size = 512 * 1024 * 4;
 388       ib_size = 128 * 1024 * 4;
 389       break;
 390    case IB_MAIN:
 391       ib = &cs->main;
 392       buffer_size = 128 * 1024 * 4;
 393       ib_size = 20 * 1024 * 4;
 394       break;
 395    default:
 396       unreachable("unhandled IB type");
 397    }
 398
 399    ib->base.cdw = 0;
 400    ib->base.buf = NULL;
 401
 402    /* Allocate a new buffer for IBs if the current buffer is all used. */
 403    if (!ib->big_ib_buffer ||
 404        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 405       if (!amdgpu_ib_new_buffer(aws, ib, buffer_size))
 406          return false;
 407    }
 408
 409    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 410                          ib->used_ib_space;
 411    amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
 412                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 413
 414    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 415    ib->base.max_dw = ib_size / 4;
 416    return true;
 417 }
 418
 419 static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
 420                                       enum ring_type ring_type)
 421 {
 422    int i;
 423
 424    switch (ring_type) {
 425    case RING_DMA:
 426       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 427       break;
 428
 429    case RING_UVD:
 430       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 431       break;
 432
 433    case RING_VCE:
 434       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 435       break;
 436
 437    case RING_COMPUTE:
 438       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 439       break;
 440
 441    default:
 442    case RING_GFX:
 443       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 444       break;
 445    }
 446
 447    cs->max_num_buffers = 512;
 448    cs->buffers = (struct amdgpu_cs_buffer*)
 449                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 450    if (!cs->buffers) {
 451       return FALSE;
 452    }
 453
 454    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 455    if (!cs->handles) {
 456       FREE(cs->buffers);
 457       return FALSE;
 458    }
 459
 460    cs->flags = CALLOC(1, cs->max_num_buffers);
 461    if (!cs->flags) {
 462       FREE(cs->handles);
 463       FREE(cs->buffers);
 464       return FALSE;
 465    }
 466
 467    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 468       cs->buffer_indices_hashlist[i] = -1;
 469    }
 470
 471    cs->request.number_of_ibs = 1;
 472    cs->request.ibs = &cs->ib[IB_MAIN];
 473
 474    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 475    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE |
 476                                      AMDGPU_IB_FLAG_PREAMBLE;
 477
 478    return TRUE;
 479 }
 480
 481 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs)
 482 {
 483    unsigned i;
 484
 485    for (i = 0; i < cs->num_buffers; i++) {
 486       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 487       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 488       cs->handles[i] = NULL;
 489       cs->flags[i] = 0;
 490    }
 491
 492    cs->num_buffers = 0;
 493    cs->used_gart = 0;
 494    cs->used_vram = 0;
 495    amdgpu_fence_reference(&cs->fence, NULL);
 496
 497    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 498       cs->buffer_indices_hashlist[i] = -1;
 499    }
 500 }
 501
 502 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs)
 503 {
 504    amdgpu_cs_context_cleanup(cs);
 505    FREE(cs->flags);
 506    FREE(cs->buffers);
 507    FREE(cs->handles);
 508    FREE(cs->request.dependencies);
 509 }
 510
 511
 512 static struct radeon_winsys_cs *
 513 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 514                  enum ring_type ring_type,
 515                  void (*flush)(void *ctx, unsigned flags,
 516                                struct pipe_fence_handle **fence),
 517                  void *flush_ctx)
 518 {
 519    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 520    struct amdgpu_cs *cs;
 521
 522    cs = CALLOC_STRUCT(amdgpu_cs);
 523    if (!cs) {
 524       return NULL;
 525    }
 526
 527    pipe_semaphore_init(&cs->flush_completed, 1);
 528
 529    cs->ctx = ctx;
 530    cs->flush_cs = flush;
 531    cs->flush_data = flush_ctx;
 532    cs->ring_type = ring_type;
 533
 534    if (!amdgpu_init_cs_context(&cs->csc1, ring_type)) {
 535       FREE(cs);
 536       return NULL;
 537    }
 538
 539    if (!amdgpu_init_cs_context(&cs->csc2, ring_type)) {
 540       amdgpu_destroy_cs_context(&cs->csc1);
 541       FREE(cs);
 542       return NULL;
 543    }
 544
 545    /* Set the first submission context as current. */
 546    cs->csc = &cs->csc1;
 547    cs->cst = &cs->csc2;
 548
 549    if (!amdgpu_get_new_ib(&ctx->ws->base, cs, IB_MAIN)) {
 550       amdgpu_destroy_cs_context(&cs->csc2);
 551       amdgpu_destroy_cs_context(&cs->csc1);
 552       FREE(cs);
 553       return NULL;
 554    }
 555
 556    p_atomic_inc(&ctx->ws->num_cs);
 557    return &cs->main.base;
 558 }
 559
 560 static struct radeon_winsys_cs *
 561 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 562 {
 563    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 564    struct amdgpu_winsys *ws = cs->ctx->ws;
 565
 566    /* only one const IB can be added */
 567    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 568       return NULL;
 569
 570    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST))
 571       return NULL;
 572
 573    cs->csc->request.number_of_ibs = 2;
 574    cs->csc->request.ibs = &cs->csc->ib[IB_CONST];
 575
 576    cs->cst->request.number_of_ibs = 2;
 577    cs->cst->request.ibs = &cs->cst->ib[IB_CONST];
 578
 579    return &cs->const_ib.base;
 580 }
 581
 582 static struct radeon_winsys_cs *
 583 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 584 {
 585    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 586    struct amdgpu_winsys *ws = cs->ctx->ws;
 587
 588    /* only one const preamble IB can be added and only when the const IB has
 589     * also been mapped */
 590    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 591        cs->const_preamble_ib.ib_mapped)
 592       return NULL;
 593
 594    if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE))
 595       return NULL;
 596
 597    cs->csc->request.number_of_ibs = 3;
 598    cs->csc->request.ibs = &cs->csc->ib[IB_CONST_PREAMBLE];
 599
 600    cs->cst->request.number_of_ibs = 3;
 601    cs->cst->request.ibs = &cs->cst->ib[IB_CONST_PREAMBLE];
 602
 603    return &cs->const_preamble_ib.base;
 604 }
 605
 606 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 607
 608 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 609                                struct pb_buffer *buf)
 610 {
 611    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 612
 613    return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
 614 }
 615
 616 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 617 {
 618    return TRUE;
 619 }
 620
 621 static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw)
 622 {
 623    assert(rcs->cdw <= rcs->max_dw);
 624    return rcs->max_dw - rcs->cdw >= dw;
 625 }
 626
 627 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 628 {
 629    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 630    struct amdgpu_winsys *ws = cs->ctx->ws;
 631
 632    vram += cs->csc->used_vram;
 633    gtt += cs->csc->used_gart;
 634
 635    /* Anything that goes above the VRAM size should go to GTT. */
 636    if (vram > ws->info.vram_size)
 637        gtt += vram - ws->info.vram_size;
 638
 639    /* Now we just need to check if we have enough GTT. */
 640    return gtt < ws->info.gart_size * 0.7;
 641 }
 642
 643 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
 644 {
 645    struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 646
 647    return cs->used_vram + cs->used_gart;
 648 }
 649
 650 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 651                                           struct radeon_bo_list_item *list)
 652 {
 653     struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
 654     int i;
 655
 656     if (list) {
 657         for (i = 0; i < cs->num_buffers; i++) {
 658             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 659             list[i].vm_address = cs->buffers[i].bo->va;
 660             list[i].priority_usage = cs->buffers[i].priority_usage;
 661         }
 662     }
 663     return cs->num_buffers;
 664 }
 665
 666 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 667
 668 /* Since the kernel driver doesn't synchronize execution between different
 669  * rings automatically, we have to add fence dependencies manually.
 670  */
 671 static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs)
 672 {
 673    struct amdgpu_cs_context *cs = acs->csc;
 674    int i, j;
 675
 676    cs->request.number_of_dependencies = 0;
 677
 678    for (i = 0; i < cs->num_buffers; i++) {
 679       for (j = 0; j < RING_LAST; j++) {
 680          struct amdgpu_cs_fence *dep;
 681          unsigned idx;
 682
 683          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 684          if (!bo_fence)
 685             continue;
 686
 687          if (bo_fence->ctx == acs->ctx &&
 688              bo_fence->fence.ip_type == cs->request.ip_type &&
 689              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 690              bo_fence->fence.ring == cs->request.ring)
 691             continue;
 692
 693          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 694             continue;
 695
 696          if (bo_fence->submission_in_progress)
 697             os_wait_until_zero(&bo_fence->submission_in_progress,
 698                                PIPE_TIMEOUT_INFINITE);
 699
 700          idx = cs->request.number_of_dependencies++;
 701          if (idx >= cs->max_dependencies) {
 702             unsigned size;
 703
 704             cs->max_dependencies = idx + 8;
 705             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 706             cs->request.dependencies = realloc(cs->request.dependencies, size);
 707          }
 708
 709          dep = &cs->request.dependencies[idx];
 710          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 711       }
 712    }
 713 }
 714
 715 void amdgpu_cs_submit_ib(struct amdgpu_cs *acs)
 716 {
 717    struct amdgpu_winsys *ws = acs->ctx->ws;
 718    struct amdgpu_cs_context *cs = acs->cst;
 719    int i, r;
 720
 721    cs->request.fence_info.handle = NULL;
 722    if (amdgpu_cs_has_user_fence(cs)) {
 723         cs->request.fence_info.handle = acs->ctx->user_fence_bo;
 724         cs->request.fence_info.offset = acs->ring_type;
 725    }
 726
 727    /* Create the buffer list.
 728     * Use a buffer list containing all allocated buffers if requested.
 729     */
 730    if (debug_get_option_all_bos()) {
 731       struct amdgpu_winsys_bo *bo;
 732       amdgpu_bo_handle *handles;
 733       unsigned num = 0;
 734
 735       pipe_mutex_lock(ws->global_bo_list_lock);
 736
 737       handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 738       if (!handles) {
 739          pipe_mutex_unlock(ws->global_bo_list_lock);
 740          amdgpu_cs_context_cleanup(cs);
 741          return;
 742       }
 743
 744       LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 745          assert(num < ws->num_buffers);
 746          handles[num++] = bo->bo;
 747       }
 748
 749       r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 750                                 handles, NULL,
 751                                 &cs->request.resources);
 752       free(handles);
 753       pipe_mutex_unlock(ws->global_bo_list_lock);
 754    } else {
 755       r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 756                                 cs->handles, cs->flags,
 757                                 &cs->request.resources);
 758    }
 759
 760    if (r) {
 761       fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
 762       cs->request.resources = NULL;
 763       amdgpu_fence_signalled(cs->fence);
 764       goto cleanup;
 765    }
 766
 767    r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1);
 768    if (r) {
 769       if (r == -ENOMEM)
 770          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 771       else
 772          fprintf(stderr, "amdgpu: The CS has been rejected, "
 773                  "see dmesg for more information.\n");
 774
 775       amdgpu_fence_signalled(cs->fence);
 776    } else {
 777       /* Success. */
 778       uint64_t *user_fence = NULL;
 779       if (amdgpu_cs_has_user_fence(cs))
 780          user_fence = acs->ctx->user_fence_cpu_address_base +
 781                       cs->request.fence_info.offset;
 782       amdgpu_fence_submitted(cs->fence, &cs->request, user_fence);
 783    }
 784
 785    /* Cleanup. */
 786    if (cs->request.resources)
 787       amdgpu_bo_list_destroy(cs->request.resources);
 788
 789 cleanup:
 790    for (i = 0; i < cs->num_buffers; i++)
 791       p_atomic_dec(&cs->buffers[i].bo->num_active_ioctls);
 792
 793    amdgpu_cs_context_cleanup(cs);
 794 }
 795
 796 /* Make sure the previous submission is completed. */
 797 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 798 {
 799    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 800
 801    /* Wait for any pending ioctl of this CS to complete. */
 802    if (cs->ctx->ws->thread) {
 803       /* wait and set the semaphore to "busy" */
 804       pipe_semaphore_wait(&cs->flush_completed);
 805       /* set the semaphore to "idle" */
 806       pipe_semaphore_signal(&cs->flush_completed);
 807    }
 808 }
 809
 810 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 811
 812 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 813                             unsigned flags,
 814                             struct pipe_fence_handle **fence)
 815 {
 816    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 817    struct amdgpu_winsys *ws = cs->ctx->ws;
 818
 819    switch (cs->ring_type) {
 820    case RING_DMA:
 821       /* pad DMA ring to 8 DWs */
 822       while (rcs->cdw & 7)
 823          OUT_CS(rcs, 0x00000000); /* NOP packet */
 824       break;
 825    case RING_GFX:
 826       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 827       while (rcs->cdw & 7)
 828          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 829
 830       /* Also pad the const IB. */
 831       if (cs->const_ib.ib_mapped)
 832          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 833             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 834
 835       if (cs->const_preamble_ib.ib_mapped)
 836          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 837             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 838       break;
 839    case RING_UVD:
 840       while (rcs->cdw & 15)
 841          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 842       break;
 843    default:
 844       break;
 845    }
 846
 847    if (rcs->cdw > rcs->max_dw) {
 848       fprintf(stderr, "amdgpu: command stream overflowed\n");
 849    }
 850
 851    /* If the CS is not empty or overflowed.... */
 852    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw &&
 853        !debug_get_option_noop()) {
 854       struct amdgpu_cs_context *cur = cs->csc;
 855       unsigned i, num_buffers = cur->num_buffers;
 856
 857       /* Set IB sizes. */
 858       cur->ib[IB_MAIN].size = cs->main.base.cdw;
 859       cs->main.used_ib_space += cs->main.base.cdw * 4;
 860
 861       if (cs->const_ib.ib_mapped) {
 862          cur->ib[IB_CONST].size = cs->const_ib.base.cdw;
 863          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 864       }
 865
 866       if (cs->const_preamble_ib.ib_mapped) {
 867          cur->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 868          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 869       }
 870
 871       /* Create a fence. */
 872       amdgpu_fence_reference(&cur->fence, NULL);
 873       cur->fence = amdgpu_fence_create(cs->ctx,
 874                                            cur->request.ip_type,
 875                                            cur->request.ip_instance,
 876                                            cur->request.ring);
 877       if (fence)
 878          amdgpu_fence_reference(fence, cur->fence);
 879
 880       /* Prepare buffers. */
 881       pipe_mutex_lock(ws->bo_fence_lock);
 882       amdgpu_add_fence_dependencies(cs);
 883       for (i = 0; i < num_buffers; i++) {
 884          p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls);
 885          amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type],
 886                                 cur->fence);
 887       }
 888       pipe_mutex_unlock(ws->bo_fence_lock);
 889
 890       amdgpu_cs_sync_flush(rcs);
 891
 892       /* Swap command streams. "cst" is going to be submitted. */
 893       cs->csc = cs->cst;
 894       cs->cst = cur;
 895
 896       /* Submit. */
 897       if (ws->thread && (flags & RADEON_FLUSH_ASYNC)) {
 898          /* Set the semaphore to "busy". */
 899          pipe_semaphore_wait(&cs->flush_completed);
 900          amdgpu_ws_queue_cs(ws, cs);
 901       } else {
 902          amdgpu_cs_submit_ib(cs);
 903       }
 904    } else {
 905       amdgpu_cs_context_cleanup(cs->csc);
 906    }
 907
 908    amdgpu_get_new_ib(&ws->base, cs, IB_MAIN);
 909    if (cs->const_ib.ib_mapped)
 910       amdgpu_get_new_ib(&ws->base, cs, IB_CONST);
 911    if (cs->const_preamble_ib.ib_mapped)
 912       amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE);
 913
 914    ws->num_cs_flushes++;
 915 }
 916
 917 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 918 {
 919    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 920
 921    amdgpu_cs_sync_flush(rcs);
 922    pipe_semaphore_destroy(&cs->flush_completed);
 923    p_atomic_dec(&cs->ctx->ws->num_cs);
 924    pb_reference(&cs->main.big_ib_buffer, NULL);
 925    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 926    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 927    amdgpu_destroy_cs_context(&cs->csc1);
 928    amdgpu_destroy_cs_context(&cs->csc2);
 929    FREE(cs);
 930 }
 931
 932 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 933                                        struct pb_buffer *_buf,
 934                                        enum radeon_bo_usage usage)
 935 {
 936    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 937    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 938
 939    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 940 }
 941
 942 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 943 {
 944    ws->base.ctx_create = amdgpu_ctx_create;
 945    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 946    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 947    ws->base.cs_create = amdgpu_cs_create;
 948    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 949    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 950    ws->base.cs_destroy = amdgpu_cs_destroy;
 951    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 952    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 953    ws->base.cs_validate = amdgpu_cs_validate;
 954    ws->base.cs_check_space = amdgpu_cs_check_space;
 955    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 956    ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
 957    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 958    ws->base.cs_flush = amdgpu_cs_flush;
 959    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 960    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 961    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 962    ws->base.fence_reference = amdgpu_fence_reference;
 963 }