src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu && *user_fence_cpu >= rfence->fence.fence) {
  93         rfence->signalled = true;
  94         return true;
  95    }
  96    /* Now use the libdrm query. */
  97    r = amdgpu_cs_query_fence_status(&rfence->fence,
  98                                     abs_timeout,
  99                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 100                                     &expired);
 101    if (r) {
 102       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 103       return FALSE;
 104    }
 105
 106    if (expired) {
 107       /* This variable can only transition from false to true, so it doesn't
 108        * matter if threads race for it. */
 109       rfence->signalled = true;
 110       return true;
 111    }
 112    return false;
 113 }
 114
 115 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 116                                           struct pipe_fence_handle *fence,
 117                                           uint64_t timeout)
 118 {
 119    return amdgpu_fence_wait(fence, timeout, false);
 120 }
 121
 122 /* CONTEXTS */
 123
 124 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 125 {
 126    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 127    int r;
 128    struct amdgpu_bo_alloc_request alloc_buffer = {};
 129    amdgpu_bo_handle buf_handle;
 130
 131    ctx->ws = amdgpu_winsys(ws);
 132    ctx->refcount = 1;
 133
 134    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 137       FREE(ctx);
 138       return NULL;
 139    }
 140
 141    alloc_buffer.alloc_size = 4 * 1024;
 142    alloc_buffer.phys_alignment = 4 *1024;
 143    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 144
 145    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 148       amdgpu_cs_ctx_free(ctx->ctx);
 149       FREE(ctx);
 150       return NULL;
 151    }
 152
 153    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 154    if (r) {
 155       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 156       amdgpu_bo_free(buf_handle);
 157       amdgpu_cs_ctx_free(ctx->ctx);
 158       FREE(ctx);
 159       return NULL;
 160    }
 161
 162    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 163    ctx->user_fence_bo = buf_handle;
 164
 165    return (struct radeon_winsys_ctx*)ctx;
 166 }
 167
 168 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 169 {
 170    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 171 }
 172
 173 static enum pipe_reset_status
 174 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 175 {
 176    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 177    uint32_t result, hangs;
 178    int r;
 179
 180    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 181    if (r) {
 182       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 183       return PIPE_NO_RESET;
 184    }
 185
 186    switch (result) {
 187    case AMDGPU_CTX_GUILTY_RESET:
 188       return PIPE_GUILTY_CONTEXT_RESET;
 189    case AMDGPU_CTX_INNOCENT_RESET:
 190       return PIPE_INNOCENT_CONTEXT_RESET;
 191    case AMDGPU_CTX_UNKNOWN_RESET:
 192       return PIPE_UNKNOWN_CONTEXT_RESET;
 193    case AMDGPU_CTX_NO_RESET:
 194    default:
 195       return PIPE_NO_RESET;
 196    }
 197 }
 198
 199 /* COMMAND SUBMISSION */
 200
 201 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
 202                               struct amdgpu_cs_ib_info *info, unsigned ib_type)
 203 {
 204    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 205     * and there is less waiting for buffers and fences. Proof:
 206     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 207     */
 208    unsigned buffer_size, ib_size;
 209
 210    switch (ib_type) {
 211    case IB_CONST_PREAMBLE:
 212       buffer_size = 4 * 1024 * 4;
 213       ib_size = 1024 * 4;
 214       break;
 215    case IB_CONST:
 216       buffer_size = 512 * 1024 * 4;
 217       ib_size = 128 * 1024 * 4;
 218       break;
 219    case IB_MAIN:
 220       buffer_size = 128 * 1024 * 4;
 221       ib_size = 20 * 1024 * 4;
 222    }
 223
 224    ib->base.cdw = 0;
 225    ib->base.buf = NULL;
 226
 227    /* Allocate a new buffer for IBs if the current buffer is all used. */
 228    if (!ib->big_ib_buffer ||
 229        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 230
 231       pb_reference(&ib->big_ib_buffer, NULL);
 232       ib->ib_mapped = NULL;
 233       ib->used_ib_space = 0;
 234
 235       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 236                                             4096, true,
 237                                             RADEON_DOMAIN_GTT,
 238                                             RADEON_FLAG_CPU_ACCESS);
 239       if (!ib->big_ib_buffer)
 240          return false;
 241
 242       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 243                                      PIPE_TRANSFER_WRITE);
 244       if (!ib->ib_mapped) {
 245          pb_reference(&ib->big_ib_buffer, NULL);
 246          return false;
 247       }
 248    }
 249
 250    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 251                          ib->used_ib_space;
 252    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 253    ib->base.max_dw = ib_size / 4;
 254    return true;
 255 }
 256
 257 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 258                                       enum ring_type ring_type)
 259 {
 260    int i;
 261
 262    switch (ring_type) {
 263    case RING_DMA:
 264       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 265       break;
 266
 267    case RING_UVD:
 268       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 269       break;
 270
 271    case RING_VCE:
 272       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 273       break;
 274
 275    case RING_COMPUTE:
 276       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 277       break;
 278
 279    default:
 280    case RING_GFX:
 281       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 282       break;
 283    }
 284
 285    cs->max_num_buffers = 512;
 286    cs->buffers = (struct amdgpu_cs_buffer*)
 287                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 288    if (!cs->buffers) {
 289       return FALSE;
 290    }
 291
 292    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 293    if (!cs->handles) {
 294       FREE(cs->buffers);
 295       return FALSE;
 296    }
 297
 298    cs->flags = CALLOC(1, cs->max_num_buffers);
 299    if (!cs->flags) {
 300       FREE(cs->handles);
 301       FREE(cs->buffers);
 302       return FALSE;
 303    }
 304
 305    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 306       cs->buffer_indices_hashlist[i] = -1;
 307    }
 308    return TRUE;
 309 }
 310
 311 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 312 {
 313    unsigned i;
 314
 315    for (i = 0; i < cs->num_buffers; i++) {
 316       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 317       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 318       cs->handles[i] = NULL;
 319       cs->flags[i] = 0;
 320    }
 321
 322    cs->num_buffers = 0;
 323    cs->used_gart = 0;
 324    cs->used_vram = 0;
 325
 326    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 327       cs->buffer_indices_hashlist[i] = -1;
 328    }
 329 }
 330
 331 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 332 {
 333    amdgpu_cs_context_cleanup(cs);
 334    FREE(cs->flags);
 335    FREE(cs->buffers);
 336    FREE(cs->handles);
 337    FREE(cs->request.dependencies);
 338 }
 339
 340
 341 static struct radeon_winsys_cs *
 342 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 343                  enum ring_type ring_type,
 344                  void (*flush)(void *ctx, unsigned flags,
 345                                struct pipe_fence_handle **fence),
 346                  void *flush_ctx)
 347 {
 348    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 349    struct amdgpu_cs *cs;
 350
 351    cs = CALLOC_STRUCT(amdgpu_cs);
 352    if (!cs) {
 353       return NULL;
 354    }
 355
 356    cs->ctx = ctx;
 357    cs->flush_cs = flush;
 358    cs->flush_data = flush_ctx;
 359    cs->ring_type = ring_type;
 360
 361    if (!amdgpu_init_cs_context(cs, ring_type)) {
 362       FREE(cs);
 363       return NULL;
 364    }
 365
 366    if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
 367       amdgpu_destroy_cs_context(cs);
 368       FREE(cs);
 369       return NULL;
 370    }
 371
 372    cs->request.number_of_ibs = 1;
 373    cs->request.ibs = &cs->ib[IB_MAIN];
 374
 375    p_atomic_inc(&ctx->ws->num_cs);
 376    return &cs->main.base;
 377 }
 378
 379 static struct radeon_winsys_cs *
 380 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 381 {
 382    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 383    struct amdgpu_winsys *ws = cs->ctx->ws;
 384
 385    /* only one const IB can be added */
 386    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 387       return NULL;
 388
 389    if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
 390       return NULL;
 391
 392    cs->request.number_of_ibs = 2;
 393    cs->request.ibs = &cs->ib[IB_CONST];
 394    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 395
 396    return &cs->const_ib.base;
 397 }
 398
 399 static struct radeon_winsys_cs *
 400 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 401 {
 402    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 403    struct amdgpu_winsys *ws = cs->ctx->ws;
 404
 405    /* only one const preamble IB can be added and only when the const IB has
 406     * also been mapped */
 407    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 408        cs->const_preamble_ib.ib_mapped)
 409       return NULL;
 410
 411    if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 412                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
 413       return NULL;
 414
 415    cs->request.number_of_ibs = 3;
 416    cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE];
 417    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE;
 418
 419    return &cs->const_preamble_ib.base;
 420 }
 421
 422 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 423
 424 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 425 {
 426    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 427    int i = cs->buffer_indices_hashlist[hash];
 428
 429    /* not found or found */
 430    if (i == -1 || cs->buffers[i].bo == bo)
 431       return i;
 432
 433    /* Hash collision, look for the BO in the list of buffers linearly. */
 434    for (i = cs->num_buffers - 1; i >= 0; i--) {
 435       if (cs->buffers[i].bo == bo) {
 436          /* Put this buffer in the hash list.
 437           * This will prevent additional hash collisions if there are
 438           * several consecutive lookup_buffer calls for the same buffer.
 439           *
 440           * Example: Assuming buffers A,B,C collide in the hash list,
 441           * the following sequence of buffers:
 442           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 443           * will collide here: ^ and here:   ^,
 444           * meaning that we should get very few collisions in the end. */
 445          cs->buffer_indices_hashlist[hash] = i;
 446          return i;
 447       }
 448    }
 449    return -1;
 450 }
 451
 452 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 453                                  struct amdgpu_winsys_bo *bo,
 454                                  enum radeon_bo_usage usage,
 455                                  enum radeon_bo_domain domains,
 456                                  unsigned priority,
 457                                  enum radeon_bo_domain *added_domains)
 458 {
 459    struct amdgpu_cs_buffer *buffer;
 460    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 461    int i = -1;
 462
 463    assert(priority < 64);
 464    *added_domains = 0;
 465
 466    i = amdgpu_lookup_buffer(cs, bo);
 467
 468    if (i >= 0) {
 469       buffer = &cs->buffers[i];
 470       buffer->priority_usage |= 1llu << priority;
 471       buffer->usage |= usage;
 472       *added_domains = domains & ~buffer->domains;
 473       buffer->domains |= domains;
 474       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 475       return i;
 476    }
 477
 478    /* New buffer, check if the backing array is large enough. */
 479    if (cs->num_buffers >= cs->max_num_buffers) {
 480       uint32_t size;
 481       cs->max_num_buffers += 10;
 482
 483       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 484       cs->buffers = realloc(cs->buffers, size);
 485
 486       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 487       cs->handles = realloc(cs->handles, size);
 488
 489       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 490    }
 491
 492    /* Initialize the new buffer. */
 493    cs->buffers[cs->num_buffers].bo = NULL;
 494    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 495    cs->handles[cs->num_buffers] = bo->bo;
 496    cs->flags[cs->num_buffers] = priority / 4;
 497    p_atomic_inc(&bo->num_cs_references);
 498    buffer = &cs->buffers[cs->num_buffers];
 499    buffer->bo = bo;
 500    buffer->priority_usage = 1llu << priority;
 501    buffer->usage = usage;
 502    buffer->domains = domains;
 503
 504    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 505
 506    *added_domains = domains;
 507    return cs->num_buffers++;
 508 }
 509
 510 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 511                                     struct pb_buffer *buf,
 512                                     enum radeon_bo_usage usage,
 513                                     enum radeon_bo_domain domains,
 514                                     enum radeon_bo_priority priority)
 515 {
 516    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 517     * the buffer placement during command submission.
 518     */
 519    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 520    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 521    enum radeon_bo_domain added_domains;
 522    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 523                                      priority, &added_domains);
 524
 525    if (added_domains & RADEON_DOMAIN_GTT)
 526       cs->used_gart += bo->base.size;
 527    if (added_domains & RADEON_DOMAIN_VRAM)
 528       cs->used_vram += bo->base.size;
 529
 530    return index;
 531 }
 532
 533 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 534                                struct pb_buffer *buf)
 535 {
 536    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 537
 538    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 539 }
 540
 541 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 542 {
 543    return TRUE;
 544 }
 545
 546 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 547 {
 548    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 549    boolean status =
 550          (cs->used_gart + gtt) < cs->ctx->ws->info.gart_size * 0.7 &&
 551          (cs->used_vram + vram) < cs->ctx->ws->info.vram_size * 0.7;
 552
 553    return status;
 554 }
 555
 556 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 557                                           struct radeon_bo_list_item *list)
 558 {
 559     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 560     int i;
 561
 562     if (list) {
 563         for (i = 0; i < cs->num_buffers; i++) {
 564             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 565             list[i].vm_address = cs->buffers[i].bo->va;
 566             list[i].priority_usage = cs->buffers[i].priority_usage;
 567         }
 568     }
 569     return cs->num_buffers;
 570 }
 571
 572 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 573                                     struct pipe_fence_handle **out_fence)
 574 {
 575    struct amdgpu_winsys *ws = cs->ctx->ws;
 576    struct pipe_fence_handle *fence;
 577    int i, j, r;
 578
 579    /* Create a fence. */
 580    fence = amdgpu_fence_create(cs->ctx,
 581                                cs->request.ip_type,
 582                                cs->request.ip_instance,
 583                                cs->request.ring);
 584    if (out_fence)
 585       amdgpu_fence_reference(out_fence, fence);
 586
 587    cs->request.number_of_dependencies = 0;
 588
 589    /* Since the kernel driver doesn't synchronize execution between different
 590     * rings automatically, we have to add fence dependencies manually. */
 591    pipe_mutex_lock(ws->bo_fence_lock);
 592    for (i = 0; i < cs->num_buffers; i++) {
 593       for (j = 0; j < RING_LAST; j++) {
 594          struct amdgpu_cs_fence *dep;
 595          unsigned idx;
 596
 597          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 598          if (!bo_fence)
 599             continue;
 600
 601          if (bo_fence->ctx == cs->ctx &&
 602              bo_fence->fence.ip_type == cs->request.ip_type &&
 603              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 604              bo_fence->fence.ring == cs->request.ring)
 605             continue;
 606
 607          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 608             continue;
 609
 610          idx = cs->request.number_of_dependencies++;
 611          if (idx >= cs->max_dependencies) {
 612             unsigned size;
 613
 614             cs->max_dependencies = idx + 8;
 615             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 616             cs->request.dependencies = realloc(cs->request.dependencies, size);
 617          }
 618
 619          dep = &cs->request.dependencies[idx];
 620          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 621       }
 622    }
 623
 624    cs->request.fence_info.handle = NULL;
 625    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 626         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 627         cs->request.fence_info.offset = cs->ring_type;
 628    }
 629
 630    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 631    if (r) {
 632       if (r == -ENOMEM)
 633          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 634       else
 635          fprintf(stderr, "amdgpu: The CS has been rejected, "
 636                  "see dmesg for more information.\n");
 637
 638       amdgpu_fence_signalled(fence);
 639    } else {
 640       /* Success. */
 641       uint64_t *user_fence = NULL;
 642       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 643          user_fence = cs->ctx->user_fence_cpu_address_base +
 644                       cs->request.fence_info.offset;
 645       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 646
 647       for (i = 0; i < cs->num_buffers; i++)
 648          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
 649                                 fence);
 650    }
 651    pipe_mutex_unlock(ws->bo_fence_lock);
 652    amdgpu_fence_reference(&fence, NULL);
 653 }
 654
 655 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 656 {
 657    /* no-op */
 658 }
 659
 660 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 661 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 662
 663 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 664                             unsigned flags,
 665                             struct pipe_fence_handle **fence)
 666 {
 667    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 668    struct amdgpu_winsys *ws = cs->ctx->ws;
 669
 670    switch (cs->ring_type) {
 671    case RING_DMA:
 672       /* pad DMA ring to 8 DWs */
 673       while (rcs->cdw & 7)
 674          OUT_CS(rcs, 0x00000000); /* NOP packet */
 675       break;
 676    case RING_GFX:
 677       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 678       while (rcs->cdw & 7)
 679          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 680
 681       /* Also pad the const IB. */
 682       if (cs->const_ib.ib_mapped)
 683          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 684             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 685
 686       if (cs->const_preamble_ib.ib_mapped)
 687          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 688             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 689       break;
 690    case RING_UVD:
 691       while (rcs->cdw & 15)
 692          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 693       break;
 694    default:
 695       break;
 696    }
 697
 698    if (rcs->cdw > rcs->max_dw) {
 699       fprintf(stderr, "amdgpu: command stream overflowed\n");
 700    }
 701
 702    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 703                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 704
 705    if (cs->const_ib.ib_mapped)
 706       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 707                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 708
 709    if (cs->const_preamble_ib.ib_mapped)
 710       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 711                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 712
 713    /* If the CS is not empty or overflowed.... */
 714    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) {
 715       int r;
 716
 717       /* Use a buffer list containing all allocated buffers if requested. */
 718       if (debug_get_option_all_bos()) {
 719          struct amdgpu_winsys_bo *bo;
 720          amdgpu_bo_handle *handles;
 721          unsigned num = 0;
 722
 723          pipe_mutex_lock(ws->global_bo_list_lock);
 724
 725          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 726          if (!handles) {
 727             pipe_mutex_unlock(ws->global_bo_list_lock);
 728             goto cleanup;
 729          }
 730
 731          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 732             assert(num < ws->num_buffers);
 733             handles[num++] = bo->bo;
 734          }
 735
 736          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 737                                    handles, NULL,
 738                                    &cs->request.resources);
 739          free(handles);
 740          pipe_mutex_unlock(ws->global_bo_list_lock);
 741       } else {
 742          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 743                                    cs->handles, cs->flags,
 744                                    &cs->request.resources);
 745       }
 746
 747       if (r) {
 748          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 749          cs->request.resources = NULL;
 750          goto cleanup;
 751       }
 752
 753       cs->ib[IB_MAIN].size = cs->main.base.cdw;
 754       cs->main.used_ib_space += cs->main.base.cdw * 4;
 755
 756       if (cs->const_ib.ib_mapped) {
 757          cs->ib[IB_CONST].size = cs->const_ib.base.cdw;
 758          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 759       }
 760
 761       if (cs->const_preamble_ib.ib_mapped) {
 762          cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 763          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 764       }
 765
 766       amdgpu_cs_do_submission(cs, fence);
 767
 768       /* Cleanup. */
 769       if (cs->request.resources)
 770          amdgpu_bo_list_destroy(cs->request.resources);
 771    }
 772
 773 cleanup:
 774    amdgpu_cs_context_cleanup(cs);
 775
 776    amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
 777    if (cs->const_ib.ib_mapped)
 778       amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
 779    if (cs->const_preamble_ib.ib_mapped)
 780       amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 781                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
 782
 783    ws->num_cs_flushes++;
 784 }
 785
 786 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 787 {
 788    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 789
 790    amdgpu_destroy_cs_context(cs);
 791    p_atomic_dec(&cs->ctx->ws->num_cs);
 792    pb_reference(&cs->main.big_ib_buffer, NULL);
 793    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 794    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 795    FREE(cs);
 796 }
 797
 798 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 799                                        struct pb_buffer *_buf,
 800                                        enum radeon_bo_usage usage)
 801 {
 802    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 803    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 804
 805    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 806 }
 807
 808 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 809 {
 810    ws->base.ctx_create = amdgpu_ctx_create;
 811    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 812    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 813    ws->base.cs_create = amdgpu_cs_create;
 814    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 815    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 816    ws->base.cs_destroy = amdgpu_cs_destroy;
 817    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 818    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 819    ws->base.cs_validate = amdgpu_cs_validate;
 820    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 821    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 822    ws->base.cs_flush = amdgpu_cs_flush;
 823    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 824    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 825    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 826    ws->base.fence_reference = amdgpu_fence_reference;
 827 }