src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu && *user_fence_cpu >= rfence->fence.fence) {
  93         rfence->signalled = true;
  94         return true;
  95    }
  96    /* Now use the libdrm query. */
  97    r = amdgpu_cs_query_fence_status(&rfence->fence,
  98                                     abs_timeout,
  99                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 100                                     &expired);
 101    if (r) {
 102       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 103       return FALSE;
 104    }
 105
 106    if (expired) {
 107       /* This variable can only transition from false to true, so it doesn't
 108        * matter if threads race for it. */
 109       rfence->signalled = true;
 110       return true;
 111    }
 112    return false;
 113 }
 114
 115 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 116                                           struct pipe_fence_handle *fence,
 117                                           uint64_t timeout)
 118 {
 119    return amdgpu_fence_wait(fence, timeout, false);
 120 }
 121
 122 /* CONTEXTS */
 123
 124 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 125 {
 126    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 127    int r;
 128    struct amdgpu_bo_alloc_request alloc_buffer = {};
 129    amdgpu_bo_handle buf_handle;
 130
 131    ctx->ws = amdgpu_winsys(ws);
 132    ctx->refcount = 1;
 133
 134    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 135    if (r) {
 136       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 137       FREE(ctx);
 138       return NULL;
 139    }
 140
 141    alloc_buffer.alloc_size = 4 * 1024;
 142    alloc_buffer.phys_alignment = 4 *1024;
 143    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 144
 145    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 146    if (r) {
 147       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 148       amdgpu_cs_ctx_free(ctx->ctx);
 149       FREE(ctx);
 150       return NULL;
 151    }
 152
 153    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 154    if (r) {
 155       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 156       amdgpu_bo_free(buf_handle);
 157       amdgpu_cs_ctx_free(ctx->ctx);
 158       FREE(ctx);
 159       return NULL;
 160    }
 161
 162    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 163    ctx->user_fence_bo = buf_handle;
 164
 165    return (struct radeon_winsys_ctx*)ctx;
 166 }
 167
 168 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 169 {
 170    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 171 }
 172
 173 static enum pipe_reset_status
 174 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 175 {
 176    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 177    uint32_t result, hangs;
 178    int r;
 179
 180    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 181    if (r) {
 182       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 183       return PIPE_NO_RESET;
 184    }
 185
 186    switch (result) {
 187    case AMDGPU_CTX_GUILTY_RESET:
 188       return PIPE_GUILTY_CONTEXT_RESET;
 189    case AMDGPU_CTX_INNOCENT_RESET:
 190       return PIPE_INNOCENT_CONTEXT_RESET;
 191    case AMDGPU_CTX_UNKNOWN_RESET:
 192       return PIPE_UNKNOWN_CONTEXT_RESET;
 193    case AMDGPU_CTX_NO_RESET:
 194    default:
 195       return PIPE_NO_RESET;
 196    }
 197 }
 198
 199 /* COMMAND SUBMISSION */
 200
 201 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
 202                               struct amdgpu_cs_ib_info *info, unsigned ib_type)
 203 {
 204    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 205     * and there is less waiting for buffers and fences. Proof:
 206     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 207     */
 208    unsigned buffer_size, ib_size;
 209
 210    switch (ib_type) {
 211    case IB_CONST_PREAMBLE:
 212       buffer_size = 4 * 1024 * 4;
 213       ib_size = 1024 * 4;
 214       break;
 215    case IB_CONST:
 216       buffer_size = 512 * 1024 * 4;
 217       ib_size = 128 * 1024 * 4;
 218       break;
 219    case IB_MAIN:
 220       buffer_size = 128 * 1024 * 4;
 221       ib_size = 20 * 1024 * 4;
 222       break;
 223    default:
 224       unreachable("unhandled IB type");
 225    }
 226
 227    ib->base.cdw = 0;
 228    ib->base.buf = NULL;
 229
 230    /* Allocate a new buffer for IBs if the current buffer is all used. */
 231    if (!ib->big_ib_buffer ||
 232        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 233
 234       pb_reference(&ib->big_ib_buffer, NULL);
 235       ib->ib_mapped = NULL;
 236       ib->used_ib_space = 0;
 237
 238       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 239                                             4096,
 240                                             RADEON_DOMAIN_GTT,
 241                                             RADEON_FLAG_CPU_ACCESS);
 242       if (!ib->big_ib_buffer)
 243          return false;
 244
 245       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 246                                      PIPE_TRANSFER_WRITE);
 247       if (!ib->ib_mapped) {
 248          pb_reference(&ib->big_ib_buffer, NULL);
 249          return false;
 250       }
 251    }
 252
 253    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 254                          ib->used_ib_space;
 255    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 256    ib->base.max_dw = ib_size / 4;
 257    return true;
 258 }
 259
 260 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 261                                       enum ring_type ring_type)
 262 {
 263    int i;
 264
 265    switch (ring_type) {
 266    case RING_DMA:
 267       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 268       break;
 269
 270    case RING_UVD:
 271       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 272       break;
 273
 274    case RING_VCE:
 275       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 276       break;
 277
 278    case RING_COMPUTE:
 279       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 280       break;
 281
 282    default:
 283    case RING_GFX:
 284       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 285       break;
 286    }
 287
 288    cs->max_num_buffers = 512;
 289    cs->buffers = (struct amdgpu_cs_buffer*)
 290                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 291    if (!cs->buffers) {
 292       return FALSE;
 293    }
 294
 295    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 296    if (!cs->handles) {
 297       FREE(cs->buffers);
 298       return FALSE;
 299    }
 300
 301    cs->flags = CALLOC(1, cs->max_num_buffers);
 302    if (!cs->flags) {
 303       FREE(cs->handles);
 304       FREE(cs->buffers);
 305       return FALSE;
 306    }
 307
 308    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 309       cs->buffer_indices_hashlist[i] = -1;
 310    }
 311    return TRUE;
 312 }
 313
 314 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 315 {
 316    unsigned i;
 317
 318    for (i = 0; i < cs->num_buffers; i++) {
 319       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 320       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 321       cs->handles[i] = NULL;
 322       cs->flags[i] = 0;
 323    }
 324
 325    cs->num_buffers = 0;
 326    cs->used_gart = 0;
 327    cs->used_vram = 0;
 328
 329    for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
 330       cs->buffer_indices_hashlist[i] = -1;
 331    }
 332 }
 333
 334 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 335 {
 336    amdgpu_cs_context_cleanup(cs);
 337    FREE(cs->flags);
 338    FREE(cs->buffers);
 339    FREE(cs->handles);
 340    FREE(cs->request.dependencies);
 341 }
 342
 343
 344 static struct radeon_winsys_cs *
 345 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 346                  enum ring_type ring_type,
 347                  void (*flush)(void *ctx, unsigned flags,
 348                                struct pipe_fence_handle **fence),
 349                  void *flush_ctx)
 350 {
 351    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 352    struct amdgpu_cs *cs;
 353
 354    cs = CALLOC_STRUCT(amdgpu_cs);
 355    if (!cs) {
 356       return NULL;
 357    }
 358
 359    cs->ctx = ctx;
 360    cs->flush_cs = flush;
 361    cs->flush_data = flush_ctx;
 362    cs->ring_type = ring_type;
 363
 364    if (!amdgpu_init_cs_context(cs, ring_type)) {
 365       FREE(cs);
 366       return NULL;
 367    }
 368
 369    if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
 370       amdgpu_destroy_cs_context(cs);
 371       FREE(cs);
 372       return NULL;
 373    }
 374
 375    cs->request.number_of_ibs = 1;
 376    cs->request.ibs = &cs->ib[IB_MAIN];
 377
 378    p_atomic_inc(&ctx->ws->num_cs);
 379    return &cs->main.base;
 380 }
 381
 382 static struct radeon_winsys_cs *
 383 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 384 {
 385    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 386    struct amdgpu_winsys *ws = cs->ctx->ws;
 387
 388    /* only one const IB can be added */
 389    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 390       return NULL;
 391
 392    if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
 393       return NULL;
 394
 395    cs->request.number_of_ibs = 2;
 396    cs->request.ibs = &cs->ib[IB_CONST];
 397    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 398
 399    return &cs->const_ib.base;
 400 }
 401
 402 static struct radeon_winsys_cs *
 403 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 404 {
 405    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 406    struct amdgpu_winsys *ws = cs->ctx->ws;
 407
 408    /* only one const preamble IB can be added and only when the const IB has
 409     * also been mapped */
 410    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 411        cs->const_preamble_ib.ib_mapped)
 412       return NULL;
 413
 414    if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 415                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
 416       return NULL;
 417
 418    cs->request.number_of_ibs = 3;
 419    cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE];
 420    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE;
 421
 422    return &cs->const_preamble_ib.base;
 423 }
 424
 425 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 426
 427 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 428 {
 429    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 430    int i = cs->buffer_indices_hashlist[hash];
 431
 432    /* not found or found */
 433    if (i == -1 || cs->buffers[i].bo == bo)
 434       return i;
 435
 436    /* Hash collision, look for the BO in the list of buffers linearly. */
 437    for (i = cs->num_buffers - 1; i >= 0; i--) {
 438       if (cs->buffers[i].bo == bo) {
 439          /* Put this buffer in the hash list.
 440           * This will prevent additional hash collisions if there are
 441           * several consecutive lookup_buffer calls for the same buffer.
 442           *
 443           * Example: Assuming buffers A,B,C collide in the hash list,
 444           * the following sequence of buffers:
 445           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 446           * will collide here: ^ and here:   ^,
 447           * meaning that we should get very few collisions in the end. */
 448          cs->buffer_indices_hashlist[hash] = i;
 449          return i;
 450       }
 451    }
 452    return -1;
 453 }
 454
 455 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 456                                  struct amdgpu_winsys_bo *bo,
 457                                  enum radeon_bo_usage usage,
 458                                  enum radeon_bo_domain domains,
 459                                  unsigned priority,
 460                                  enum radeon_bo_domain *added_domains)
 461 {
 462    struct amdgpu_cs_buffer *buffer;
 463    unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
 464    int i = -1;
 465
 466    assert(priority < 64);
 467    *added_domains = 0;
 468
 469    i = amdgpu_lookup_buffer(cs, bo);
 470
 471    if (i >= 0) {
 472       buffer = &cs->buffers[i];
 473       buffer->priority_usage |= 1llu << priority;
 474       buffer->usage |= usage;
 475       *added_domains = domains & ~buffer->domains;
 476       buffer->domains |= domains;
 477       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 478       return i;
 479    }
 480
 481    /* New buffer, check if the backing array is large enough. */
 482    if (cs->num_buffers >= cs->max_num_buffers) {
 483       uint32_t size;
 484       cs->max_num_buffers += 10;
 485
 486       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 487       cs->buffers = realloc(cs->buffers, size);
 488
 489       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 490       cs->handles = realloc(cs->handles, size);
 491
 492       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 493    }
 494
 495    /* Initialize the new buffer. */
 496    cs->buffers[cs->num_buffers].bo = NULL;
 497    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 498    cs->handles[cs->num_buffers] = bo->bo;
 499    cs->flags[cs->num_buffers] = priority / 4;
 500    p_atomic_inc(&bo->num_cs_references);
 501    buffer = &cs->buffers[cs->num_buffers];
 502    buffer->bo = bo;
 503    buffer->priority_usage = 1llu << priority;
 504    buffer->usage = usage;
 505    buffer->domains = domains;
 506
 507    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 508
 509    *added_domains = domains;
 510    return cs->num_buffers++;
 511 }
 512
 513 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 514                                     struct pb_buffer *buf,
 515                                     enum radeon_bo_usage usage,
 516                                     enum radeon_bo_domain domains,
 517                                     enum radeon_bo_priority priority)
 518 {
 519    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 520     * the buffer placement during command submission.
 521     */
 522    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 523    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 524    enum radeon_bo_domain added_domains;
 525    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 526                                      priority, &added_domains);
 527
 528    if (added_domains & RADEON_DOMAIN_GTT)
 529       cs->used_gart += bo->base.size;
 530    if (added_domains & RADEON_DOMAIN_VRAM)
 531       cs->used_vram += bo->base.size;
 532
 533    return index;
 534 }
 535
 536 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 537                                struct pb_buffer *buf)
 538 {
 539    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 540
 541    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 542 }
 543
 544 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 545 {
 546    return TRUE;
 547 }
 548
 549 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 550 {
 551    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 552    struct amdgpu_winsys *ws = cs->ctx->ws;
 553
 554    vram += cs->used_vram;
 555    gtt += cs->used_gart;
 556
 557    /* Anything that goes above the VRAM size should go to GTT. */
 558    if (vram > ws->info.vram_size)
 559        gtt += vram - ws->info.vram_size;
 560
 561    /* Now we just need to check if we have enough GTT. */
 562    return gtt < ws->info.gart_size * 0.7;
 563 }
 564
 565 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 566                                           struct radeon_bo_list_item *list)
 567 {
 568     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 569     int i;
 570
 571     if (list) {
 572         for (i = 0; i < cs->num_buffers; i++) {
 573             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 574             list[i].vm_address = cs->buffers[i].bo->va;
 575             list[i].priority_usage = cs->buffers[i].priority_usage;
 576         }
 577     }
 578     return cs->num_buffers;
 579 }
 580
 581 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 582                                     struct pipe_fence_handle **out_fence)
 583 {
 584    struct amdgpu_winsys *ws = cs->ctx->ws;
 585    struct pipe_fence_handle *fence;
 586    int i, j, r;
 587
 588    /* Create a fence. */
 589    fence = amdgpu_fence_create(cs->ctx,
 590                                cs->request.ip_type,
 591                                cs->request.ip_instance,
 592                                cs->request.ring);
 593    if (out_fence)
 594       amdgpu_fence_reference(out_fence, fence);
 595
 596    cs->request.number_of_dependencies = 0;
 597
 598    /* Since the kernel driver doesn't synchronize execution between different
 599     * rings automatically, we have to add fence dependencies manually. */
 600    pipe_mutex_lock(ws->bo_fence_lock);
 601    for (i = 0; i < cs->num_buffers; i++) {
 602       for (j = 0; j < RING_LAST; j++) {
 603          struct amdgpu_cs_fence *dep;
 604          unsigned idx;
 605
 606          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 607          if (!bo_fence)
 608             continue;
 609
 610          if (bo_fence->ctx == cs->ctx &&
 611              bo_fence->fence.ip_type == cs->request.ip_type &&
 612              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 613              bo_fence->fence.ring == cs->request.ring)
 614             continue;
 615
 616          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 617             continue;
 618
 619          idx = cs->request.number_of_dependencies++;
 620          if (idx >= cs->max_dependencies) {
 621             unsigned size;
 622
 623             cs->max_dependencies = idx + 8;
 624             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 625             cs->request.dependencies = realloc(cs->request.dependencies, size);
 626          }
 627
 628          dep = &cs->request.dependencies[idx];
 629          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 630       }
 631    }
 632
 633    cs->request.fence_info.handle = NULL;
 634    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 635         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 636         cs->request.fence_info.offset = cs->ring_type;
 637    }
 638
 639    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 640    if (r) {
 641       if (r == -ENOMEM)
 642          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 643       else
 644          fprintf(stderr, "amdgpu: The CS has been rejected, "
 645                  "see dmesg for more information.\n");
 646
 647       amdgpu_fence_signalled(fence);
 648    } else {
 649       /* Success. */
 650       uint64_t *user_fence = NULL;
 651       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 652          user_fence = cs->ctx->user_fence_cpu_address_base +
 653                       cs->request.fence_info.offset;
 654       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 655
 656       for (i = 0; i < cs->num_buffers; i++)
 657          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
 658                                 fence);
 659    }
 660    pipe_mutex_unlock(ws->bo_fence_lock);
 661    amdgpu_fence_reference(&fence, NULL);
 662 }
 663
 664 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 665 {
 666    /* no-op */
 667 }
 668
 669 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 670 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 671
 672 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 673                             unsigned flags,
 674                             struct pipe_fence_handle **fence)
 675 {
 676    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 677    struct amdgpu_winsys *ws = cs->ctx->ws;
 678
 679    switch (cs->ring_type) {
 680    case RING_DMA:
 681       /* pad DMA ring to 8 DWs */
 682       while (rcs->cdw & 7)
 683          OUT_CS(rcs, 0x00000000); /* NOP packet */
 684       break;
 685    case RING_GFX:
 686       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 687       while (rcs->cdw & 7)
 688          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 689
 690       /* Also pad the const IB. */
 691       if (cs->const_ib.ib_mapped)
 692          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 693             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 694
 695       if (cs->const_preamble_ib.ib_mapped)
 696          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 697             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 698       break;
 699    case RING_UVD:
 700       while (rcs->cdw & 15)
 701          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 702       break;
 703    default:
 704       break;
 705    }
 706
 707    if (rcs->cdw > rcs->max_dw) {
 708       fprintf(stderr, "amdgpu: command stream overflowed\n");
 709    }
 710
 711    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 712                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 713
 714    if (cs->const_ib.ib_mapped)
 715       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 716                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 717
 718    if (cs->const_preamble_ib.ib_mapped)
 719       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 720                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 721
 722    /* If the CS is not empty or overflowed.... */
 723    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) {
 724       int r;
 725
 726       /* Use a buffer list containing all allocated buffers if requested. */
 727       if (debug_get_option_all_bos()) {
 728          struct amdgpu_winsys_bo *bo;
 729          amdgpu_bo_handle *handles;
 730          unsigned num = 0;
 731
 732          pipe_mutex_lock(ws->global_bo_list_lock);
 733
 734          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 735          if (!handles) {
 736             pipe_mutex_unlock(ws->global_bo_list_lock);
 737             goto cleanup;
 738          }
 739
 740          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 741             assert(num < ws->num_buffers);
 742             handles[num++] = bo->bo;
 743          }
 744
 745          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 746                                    handles, NULL,
 747                                    &cs->request.resources);
 748          free(handles);
 749          pipe_mutex_unlock(ws->global_bo_list_lock);
 750       } else {
 751          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 752                                    cs->handles, cs->flags,
 753                                    &cs->request.resources);
 754       }
 755
 756       if (r) {
 757          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 758          cs->request.resources = NULL;
 759          goto cleanup;
 760       }
 761
 762       cs->ib[IB_MAIN].size = cs->main.base.cdw;
 763       cs->main.used_ib_space += cs->main.base.cdw * 4;
 764
 765       if (cs->const_ib.ib_mapped) {
 766          cs->ib[IB_CONST].size = cs->const_ib.base.cdw;
 767          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 768       }
 769
 770       if (cs->const_preamble_ib.ib_mapped) {
 771          cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 772          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 773       }
 774
 775       amdgpu_cs_do_submission(cs, fence);
 776
 777       /* Cleanup. */
 778       if (cs->request.resources)
 779          amdgpu_bo_list_destroy(cs->request.resources);
 780    }
 781
 782 cleanup:
 783    amdgpu_cs_context_cleanup(cs);
 784
 785    amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
 786    if (cs->const_ib.ib_mapped)
 787       amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
 788    if (cs->const_preamble_ib.ib_mapped)
 789       amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 790                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
 791
 792    ws->num_cs_flushes++;
 793 }
 794
 795 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 796 {
 797    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 798
 799    amdgpu_destroy_cs_context(cs);
 800    p_atomic_dec(&cs->ctx->ws->num_cs);
 801    pb_reference(&cs->main.big_ib_buffer, NULL);
 802    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 803    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 804    FREE(cs);
 805 }
 806
 807 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 808                                        struct pb_buffer *_buf,
 809                                        enum radeon_bo_usage usage)
 810 {
 811    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 812    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 813
 814    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 815 }
 816
 817 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 818 {
 819    ws->base.ctx_create = amdgpu_ctx_create;
 820    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 821    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 822    ws->base.cs_create = amdgpu_cs_create;
 823    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 824    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 825    ws->base.cs_destroy = amdgpu_cs_destroy;
 826    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 827    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 828    ws->base.cs_validate = amdgpu_cs_validate;
 829    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 830    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 831    ws->base.cs_flush = amdgpu_cs_flush;
 832    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 833    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 834    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 835    ws->base.fence_reference = amdgpu_fence_reference;
 836 }