src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

   1 /*
   2  * Copyright © 2008 Jérôme Glisse
   3  * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright © 2015 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  19  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * The above copyright notice and this permission notice (including the
  25  * next paragraph) shall be included in all copies or substantial portions
  26  * of the Software.
  27  */
  28 /*
  29  * Authors:
  30  *      Marek Olšák <maraeo@gmail.com>
  31  */
  32
  33 #include "amdgpu_cs.h"
  34 #include "os/os_time.h"
  35 #include <stdio.h>
  36 #include <amdgpu_drm.h>
  37
  38
  39 /* FENCES */
  40
  41 static struct pipe_fence_handle *
  42 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
  43                     unsigned ip_instance, unsigned ring)
  44 {
  45    struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
  46
  47    fence->reference.count = 1;
  48    fence->ctx = ctx;
  49    fence->fence.context = ctx->ctx;
  50    fence->fence.ip_type = ip_type;
  51    fence->fence.ip_instance = ip_instance;
  52    fence->fence.ring = ring;
  53    p_atomic_inc(&ctx->refcount);
  54    return (struct pipe_fence_handle *)fence;
  55 }
  56
  57 static void amdgpu_fence_submitted(struct pipe_fence_handle *fence,
  58                                 struct amdgpu_cs_request* request,
  59                                 uint64_t *user_fence_cpu_address)
  60 {
  61    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  62
  63    rfence->fence.fence = request->seq_no;
  64    rfence->user_fence_cpu_address = user_fence_cpu_address;
  65 }
  66
  67 static void amdgpu_fence_signalled(struct pipe_fence_handle *fence)
  68 {
  69    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  70
  71    rfence->signalled = true;
  72 }
  73
  74 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
  75                        bool absolute)
  76 {
  77    struct amdgpu_fence *rfence = (struct amdgpu_fence*)fence;
  78    uint32_t expired;
  79    int64_t abs_timeout;
  80    uint64_t *user_fence_cpu;
  81    int r;
  82
  83    if (rfence->signalled)
  84       return true;
  85
  86    if (absolute)
  87       abs_timeout = timeout;
  88    else
  89       abs_timeout = os_time_get_absolute_timeout(timeout);
  90
  91    user_fence_cpu = rfence->user_fence_cpu_address;
  92    if (user_fence_cpu) {
  93       if (*user_fence_cpu >= rfence->fence.fence) {
  94          rfence->signalled = true;
  95          return true;
  96       }
  97
  98       /* No timeout, just query: no need for the ioctl. */
  99       if (!absolute && !timeout)
 100          return false;
 101    }
 102
 103    /* Now use the libdrm query. */
 104    r = amdgpu_cs_query_fence_status(&rfence->fence,
 105                                     abs_timeout,
 106                                     AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE,
 107                                     &expired);
 108    if (r) {
 109       fprintf(stderr, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
 110       return FALSE;
 111    }
 112
 113    if (expired) {
 114       /* This variable can only transition from false to true, so it doesn't
 115        * matter if threads race for it. */
 116       rfence->signalled = true;
 117       return true;
 118    }
 119    return false;
 120 }
 121
 122 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws,
 123                                           struct pipe_fence_handle *fence,
 124                                           uint64_t timeout)
 125 {
 126    return amdgpu_fence_wait(fence, timeout, false);
 127 }
 128
 129 /* CONTEXTS */
 130
 131 static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
 132 {
 133    struct amdgpu_ctx *ctx = CALLOC_STRUCT(amdgpu_ctx);
 134    int r;
 135    struct amdgpu_bo_alloc_request alloc_buffer = {};
 136    amdgpu_bo_handle buf_handle;
 137
 138    ctx->ws = amdgpu_winsys(ws);
 139    ctx->refcount = 1;
 140
 141    r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
 142    if (r) {
 143       fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r);
 144       FREE(ctx);
 145       return NULL;
 146    }
 147
 148    alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
 149    alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
 150    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 151
 152    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
 153    if (r) {
 154       fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
 155       amdgpu_cs_ctx_free(ctx->ctx);
 156       FREE(ctx);
 157       return NULL;
 158    }
 159
 160    r = amdgpu_bo_cpu_map(buf_handle, (void**)&ctx->user_fence_cpu_address_base);
 161    if (r) {
 162       fprintf(stderr, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r);
 163       amdgpu_bo_free(buf_handle);
 164       amdgpu_cs_ctx_free(ctx->ctx);
 165       FREE(ctx);
 166       return NULL;
 167    }
 168
 169    memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
 170    ctx->user_fence_bo = buf_handle;
 171
 172    return (struct radeon_winsys_ctx*)ctx;
 173 }
 174
 175 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
 176 {
 177    amdgpu_ctx_unref((struct amdgpu_ctx*)rwctx);
 178 }
 179
 180 static enum pipe_reset_status
 181 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 182 {
 183    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 184    uint32_t result, hangs;
 185    int r;
 186
 187    r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
 188    if (r) {
 189       fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
 190       return PIPE_NO_RESET;
 191    }
 192
 193    switch (result) {
 194    case AMDGPU_CTX_GUILTY_RESET:
 195       return PIPE_GUILTY_CONTEXT_RESET;
 196    case AMDGPU_CTX_INNOCENT_RESET:
 197       return PIPE_INNOCENT_CONTEXT_RESET;
 198    case AMDGPU_CTX_UNKNOWN_RESET:
 199       return PIPE_UNKNOWN_CONTEXT_RESET;
 200    case AMDGPU_CTX_NO_RESET:
 201    default:
 202       return PIPE_NO_RESET;
 203    }
 204 }
 205
 206 /* COMMAND SUBMISSION */
 207
 208 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
 209                               struct amdgpu_cs_ib_info *info, unsigned ib_type)
 210 {
 211    struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
 212    /* Small IBs are better than big IBs, because the GPU goes idle quicker
 213     * and there is less waiting for buffers and fences. Proof:
 214     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
 215     */
 216    unsigned buffer_size, ib_size;
 217
 218    switch (ib_type) {
 219    case IB_CONST_PREAMBLE:
 220       buffer_size = 4 * 1024 * 4;
 221       ib_size = 1024 * 4;
 222       break;
 223    case IB_CONST:
 224       buffer_size = 512 * 1024 * 4;
 225       ib_size = 128 * 1024 * 4;
 226       break;
 227    case IB_MAIN:
 228       buffer_size = 128 * 1024 * 4;
 229       ib_size = 20 * 1024 * 4;
 230       break;
 231    default:
 232       unreachable("unhandled IB type");
 233    }
 234
 235    ib->base.cdw = 0;
 236    ib->base.buf = NULL;
 237
 238    /* Allocate a new buffer for IBs if the current buffer is all used. */
 239    if (!ib->big_ib_buffer ||
 240        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
 241
 242       pb_reference(&ib->big_ib_buffer, NULL);
 243       ib->ib_mapped = NULL;
 244       ib->used_ib_space = 0;
 245
 246       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
 247                                             aws->info.gart_page_size,
 248                                             RADEON_DOMAIN_GTT,
 249                                             RADEON_FLAG_CPU_ACCESS);
 250       if (!ib->big_ib_buffer)
 251          return false;
 252
 253       ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
 254                                      PIPE_TRANSFER_WRITE);
 255       if (!ib->ib_mapped) {
 256          pb_reference(&ib->big_ib_buffer, NULL);
 257          return false;
 258       }
 259    }
 260
 261    info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
 262                          ib->used_ib_space;
 263    ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 264    ib->base.max_dw = ib_size / 4;
 265    return true;
 266 }
 267
 268 static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
 269                                       enum ring_type ring_type)
 270 {
 271    int i;
 272
 273    switch (ring_type) {
 274    case RING_DMA:
 275       cs->request.ip_type = AMDGPU_HW_IP_DMA;
 276       break;
 277
 278    case RING_UVD:
 279       cs->request.ip_type = AMDGPU_HW_IP_UVD;
 280       break;
 281
 282    case RING_VCE:
 283       cs->request.ip_type = AMDGPU_HW_IP_VCE;
 284       break;
 285
 286    case RING_COMPUTE:
 287       cs->request.ip_type = AMDGPU_HW_IP_COMPUTE;
 288       break;
 289
 290    default:
 291    case RING_GFX:
 292       cs->request.ip_type = AMDGPU_HW_IP_GFX;
 293       break;
 294    }
 295
 296    cs->max_num_buffers = 512;
 297    cs->buffers = (struct amdgpu_cs_buffer*)
 298                   CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer));
 299    if (!cs->buffers) {
 300       return FALSE;
 301    }
 302
 303    cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
 304    if (!cs->handles) {
 305       FREE(cs->buffers);
 306       return FALSE;
 307    }
 308
 309    cs->flags = CALLOC(1, cs->max_num_buffers);
 310    if (!cs->flags) {
 311       FREE(cs->handles);
 312       FREE(cs->buffers);
 313       return FALSE;
 314    }
 315
 316    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 317       cs->buffer_indices_hashlist[i] = -1;
 318    }
 319    return TRUE;
 320 }
 321
 322 static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
 323 {
 324    unsigned i;
 325
 326    for (i = 0; i < cs->num_buffers; i++) {
 327       p_atomic_dec(&cs->buffers[i].bo->num_cs_references);
 328       amdgpu_winsys_bo_reference(&cs->buffers[i].bo, NULL);
 329       cs->handles[i] = NULL;
 330       cs->flags[i] = 0;
 331    }
 332
 333    cs->num_buffers = 0;
 334    cs->used_gart = 0;
 335    cs->used_vram = 0;
 336
 337    for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
 338       cs->buffer_indices_hashlist[i] = -1;
 339    }
 340 }
 341
 342 static void amdgpu_destroy_cs_context(struct amdgpu_cs *cs)
 343 {
 344    amdgpu_cs_context_cleanup(cs);
 345    FREE(cs->flags);
 346    FREE(cs->buffers);
 347    FREE(cs->handles);
 348    FREE(cs->request.dependencies);
 349 }
 350
 351
 352 static struct radeon_winsys_cs *
 353 amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 354                  enum ring_type ring_type,
 355                  void (*flush)(void *ctx, unsigned flags,
 356                                struct pipe_fence_handle **fence),
 357                  void *flush_ctx)
 358 {
 359    struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
 360    struct amdgpu_cs *cs;
 361
 362    cs = CALLOC_STRUCT(amdgpu_cs);
 363    if (!cs) {
 364       return NULL;
 365    }
 366
 367    cs->ctx = ctx;
 368    cs->flush_cs = flush;
 369    cs->flush_data = flush_ctx;
 370    cs->ring_type = ring_type;
 371
 372    if (!amdgpu_init_cs_context(cs, ring_type)) {
 373       FREE(cs);
 374       return NULL;
 375    }
 376
 377    if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
 378       amdgpu_destroy_cs_context(cs);
 379       FREE(cs);
 380       return NULL;
 381    }
 382
 383    cs->request.number_of_ibs = 1;
 384    cs->request.ibs = &cs->ib[IB_MAIN];
 385
 386    p_atomic_inc(&ctx->ws->num_cs);
 387    return &cs->main.base;
 388 }
 389
 390 static struct radeon_winsys_cs *
 391 amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
 392 {
 393    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 394    struct amdgpu_winsys *ws = cs->ctx->ws;
 395
 396    /* only one const IB can be added */
 397    if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
 398       return NULL;
 399
 400    if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
 401       return NULL;
 402
 403    cs->request.number_of_ibs = 2;
 404    cs->request.ibs = &cs->ib[IB_CONST];
 405    cs->ib[IB_CONST].flags = AMDGPU_IB_FLAG_CE;
 406
 407    return &cs->const_ib.base;
 408 }
 409
 410 static struct radeon_winsys_cs *
 411 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 412 {
 413    struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
 414    struct amdgpu_winsys *ws = cs->ctx->ws;
 415
 416    /* only one const preamble IB can be added and only when the const IB has
 417     * also been mapped */
 418    if (cs->ring_type != RING_GFX || !cs->const_ib.ib_mapped ||
 419        cs->const_preamble_ib.ib_mapped)
 420       return NULL;
 421
 422    if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 423                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
 424       return NULL;
 425
 426    cs->request.number_of_ibs = 3;
 427    cs->request.ibs = &cs->ib[IB_CONST_PREAMBLE];
 428    cs->ib[IB_CONST_PREAMBLE].flags = AMDGPU_IB_FLAG_CE | AMDGPU_IB_FLAG_PREAMBLE;
 429
 430    return &cs->const_preamble_ib.base;
 431 }
 432
 433 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 434
 435 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 436 {
 437    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 438    int i = cs->buffer_indices_hashlist[hash];
 439
 440    /* not found or found */
 441    if (i == -1 || cs->buffers[i].bo == bo)
 442       return i;
 443
 444    /* Hash collision, look for the BO in the list of buffers linearly. */
 445    for (i = cs->num_buffers - 1; i >= 0; i--) {
 446       if (cs->buffers[i].bo == bo) {
 447          /* Put this buffer in the hash list.
 448           * This will prevent additional hash collisions if there are
 449           * several consecutive lookup_buffer calls for the same buffer.
 450           *
 451           * Example: Assuming buffers A,B,C collide in the hash list,
 452           * the following sequence of buffers:
 453           *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
 454           * will collide here: ^ and here:   ^,
 455           * meaning that we should get very few collisions in the end. */
 456          cs->buffer_indices_hashlist[hash] = i;
 457          return i;
 458       }
 459    }
 460    return -1;
 461 }
 462
 463 static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
 464                                  struct amdgpu_winsys_bo *bo,
 465                                  enum radeon_bo_usage usage,
 466                                  enum radeon_bo_domain domains,
 467                                  unsigned priority,
 468                                  enum radeon_bo_domain *added_domains)
 469 {
 470    struct amdgpu_cs_buffer *buffer;
 471    unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
 472    int i = -1;
 473
 474    assert(priority < 64);
 475    *added_domains = 0;
 476
 477    i = amdgpu_lookup_buffer(cs, bo);
 478
 479    if (i >= 0) {
 480       buffer = &cs->buffers[i];
 481       buffer->priority_usage |= 1llu << priority;
 482       buffer->usage |= usage;
 483       *added_domains = domains & ~buffer->domains;
 484       buffer->domains |= domains;
 485       cs->flags[i] = MAX2(cs->flags[i], priority / 4);
 486       return i;
 487    }
 488
 489    /* New buffer, check if the backing array is large enough. */
 490    if (cs->num_buffers >= cs->max_num_buffers) {
 491       uint32_t size;
 492       cs->max_num_buffers += 10;
 493
 494       size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
 495       cs->buffers = realloc(cs->buffers, size);
 496
 497       size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
 498       cs->handles = realloc(cs->handles, size);
 499
 500       cs->flags = realloc(cs->flags, cs->max_num_buffers);
 501    }
 502
 503    /* Initialize the new buffer. */
 504    cs->buffers[cs->num_buffers].bo = NULL;
 505    amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
 506    cs->handles[cs->num_buffers] = bo->bo;
 507    cs->flags[cs->num_buffers] = priority / 4;
 508    p_atomic_inc(&bo->num_cs_references);
 509    buffer = &cs->buffers[cs->num_buffers];
 510    buffer->bo = bo;
 511    buffer->priority_usage = 1llu << priority;
 512    buffer->usage = usage;
 513    buffer->domains = domains;
 514
 515    cs->buffer_indices_hashlist[hash] = cs->num_buffers;
 516
 517    *added_domains = domains;
 518    return cs->num_buffers++;
 519 }
 520
 521 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
 522                                     struct pb_buffer *buf,
 523                                     enum radeon_bo_usage usage,
 524                                     enum radeon_bo_domain domains,
 525                                     enum radeon_bo_priority priority)
 526 {
 527    /* Don't use the "domains" parameter. Amdgpu doesn't support changing
 528     * the buffer placement during command submission.
 529     */
 530    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 531    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 532    enum radeon_bo_domain added_domains;
 533    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
 534                                      priority, &added_domains);
 535
 536    if (added_domains & RADEON_DOMAIN_VRAM)
 537       cs->used_vram += bo->base.size;
 538    else if (added_domains & RADEON_DOMAIN_GTT)
 539       cs->used_gart += bo->base.size;
 540
 541    return index;
 542 }
 543
 544 static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
 545                                struct pb_buffer *buf)
 546 {
 547    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 548
 549    return amdgpu_lookup_buffer(cs, (struct amdgpu_winsys_bo*)buf);
 550 }
 551
 552 static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 553 {
 554    return TRUE;
 555 }
 556
 557 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 558 {
 559    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 560    struct amdgpu_winsys *ws = cs->ctx->ws;
 561
 562    vram += cs->used_vram;
 563    gtt += cs->used_gart;
 564
 565    /* Anything that goes above the VRAM size should go to GTT. */
 566    if (vram > ws->info.vram_size)
 567        gtt += vram - ws->info.vram_size;
 568
 569    /* Now we just need to check if we have enough GTT. */
 570    return gtt < ws->info.gart_size * 0.7;
 571 }
 572
 573 static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
 574 {
 575    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 576
 577    return cs->used_vram + cs->used_gart;
 578 }
 579
 580 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
 581                                           struct radeon_bo_list_item *list)
 582 {
 583     struct amdgpu_cs *cs = amdgpu_cs(rcs);
 584     int i;
 585
 586     if (list) {
 587         for (i = 0; i < cs->num_buffers; i++) {
 588             pb_reference(&list[i].buf, &cs->buffers[i].bo->base);
 589             list[i].vm_address = cs->buffers[i].bo->va;
 590             list[i].priority_usage = cs->buffers[i].priority_usage;
 591         }
 592     }
 593     return cs->num_buffers;
 594 }
 595
 596 static void amdgpu_cs_do_submission(struct amdgpu_cs *cs,
 597                                     struct pipe_fence_handle **out_fence)
 598 {
 599    struct amdgpu_winsys *ws = cs->ctx->ws;
 600    struct pipe_fence_handle *fence;
 601    int i, j, r;
 602
 603    /* Create a fence. */
 604    fence = amdgpu_fence_create(cs->ctx,
 605                                cs->request.ip_type,
 606                                cs->request.ip_instance,
 607                                cs->request.ring);
 608    if (out_fence)
 609       amdgpu_fence_reference(out_fence, fence);
 610
 611    cs->request.number_of_dependencies = 0;
 612
 613    /* Since the kernel driver doesn't synchronize execution between different
 614     * rings automatically, we have to add fence dependencies manually. */
 615    pipe_mutex_lock(ws->bo_fence_lock);
 616    for (i = 0; i < cs->num_buffers; i++) {
 617       for (j = 0; j < RING_LAST; j++) {
 618          struct amdgpu_cs_fence *dep;
 619          unsigned idx;
 620
 621          struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
 622          if (!bo_fence)
 623             continue;
 624
 625          if (bo_fence->ctx == cs->ctx &&
 626              bo_fence->fence.ip_type == cs->request.ip_type &&
 627              bo_fence->fence.ip_instance == cs->request.ip_instance &&
 628              bo_fence->fence.ring == cs->request.ring)
 629             continue;
 630
 631          if (amdgpu_fence_wait((void *)bo_fence, 0, false))
 632             continue;
 633
 634          idx = cs->request.number_of_dependencies++;
 635          if (idx >= cs->max_dependencies) {
 636             unsigned size;
 637
 638             cs->max_dependencies = idx + 8;
 639             size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
 640             cs->request.dependencies = realloc(cs->request.dependencies, size);
 641          }
 642
 643          dep = &cs->request.dependencies[idx];
 644          memcpy(dep, &bo_fence->fence, sizeof(*dep));
 645       }
 646    }
 647
 648    cs->request.fence_info.handle = NULL;
 649    if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE) {
 650         cs->request.fence_info.handle = cs->ctx->user_fence_bo;
 651         cs->request.fence_info.offset = cs->ring_type;
 652    }
 653
 654    r = amdgpu_cs_submit(cs->ctx->ctx, 0, &cs->request, 1);
 655    if (r) {
 656       if (r == -ENOMEM)
 657          fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
 658       else
 659          fprintf(stderr, "amdgpu: The CS has been rejected, "
 660                  "see dmesg for more information.\n");
 661
 662       amdgpu_fence_signalled(fence);
 663    } else {
 664       /* Success. */
 665       uint64_t *user_fence = NULL;
 666       if (cs->request.ip_type != AMDGPU_HW_IP_UVD && cs->request.ip_type != AMDGPU_HW_IP_VCE)
 667          user_fence = cs->ctx->user_fence_cpu_address_base +
 668                       cs->request.fence_info.offset;
 669       amdgpu_fence_submitted(fence, &cs->request, user_fence);
 670
 671       for (i = 0; i < cs->num_buffers; i++)
 672          amdgpu_fence_reference(&cs->buffers[i].bo->fence[cs->ring_type],
 673                                 fence);
 674    }
 675    pipe_mutex_unlock(ws->bo_fence_lock);
 676    amdgpu_fence_reference(&fence, NULL);
 677 }
 678
 679 static void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 680 {
 681    /* no-op */
 682 }
 683
 684 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", FALSE)
 685 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", FALSE)
 686
 687 static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 688                             unsigned flags,
 689                             struct pipe_fence_handle **fence)
 690 {
 691    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 692    struct amdgpu_winsys *ws = cs->ctx->ws;
 693
 694    switch (cs->ring_type) {
 695    case RING_DMA:
 696       /* pad DMA ring to 8 DWs */
 697       while (rcs->cdw & 7)
 698          OUT_CS(rcs, 0x00000000); /* NOP packet */
 699       break;
 700    case RING_GFX:
 701       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
 702       while (rcs->cdw & 7)
 703          OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
 704
 705       /* Also pad the const IB. */
 706       if (cs->const_ib.ib_mapped)
 707          while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
 708             OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
 709
 710       if (cs->const_preamble_ib.ib_mapped)
 711          while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
 712             OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
 713       break;
 714    case RING_UVD:
 715       while (rcs->cdw & 15)
 716          OUT_CS(rcs, 0x80000000); /* type2 nop packet */
 717       break;
 718    default:
 719       break;
 720    }
 721
 722    if (rcs->cdw > rcs->max_dw) {
 723       fprintf(stderr, "amdgpu: command stream overflowed\n");
 724    }
 725
 726    amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
 727                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 728
 729    if (cs->const_ib.ib_mapped)
 730       amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
 731                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 732
 733    if (cs->const_preamble_ib.ib_mapped)
 734       amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
 735                            RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 736
 737    /* If the CS is not empty or overflowed.... */
 738    if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw && !debug_get_option_noop()) {
 739       int r;
 740
 741       /* Use a buffer list containing all allocated buffers if requested. */
 742       if (debug_get_option_all_bos()) {
 743          struct amdgpu_winsys_bo *bo;
 744          amdgpu_bo_handle *handles;
 745          unsigned num = 0;
 746
 747          pipe_mutex_lock(ws->global_bo_list_lock);
 748
 749          handles = malloc(sizeof(handles[0]) * ws->num_buffers);
 750          if (!handles) {
 751             pipe_mutex_unlock(ws->global_bo_list_lock);
 752             goto cleanup;
 753          }
 754
 755          LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
 756             assert(num < ws->num_buffers);
 757             handles[num++] = bo->bo;
 758          }
 759
 760          r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
 761                                    handles, NULL,
 762                                    &cs->request.resources);
 763          free(handles);
 764          pipe_mutex_unlock(ws->global_bo_list_lock);
 765       } else {
 766          r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
 767                                    cs->handles, cs->flags,
 768                                    &cs->request.resources);
 769       }
 770
 771       if (r) {
 772          fprintf(stderr, "amdgpu: resource list creation failed (%d)\n", r);
 773          cs->request.resources = NULL;
 774          goto cleanup;
 775       }
 776
 777       cs->ib[IB_MAIN].size = cs->main.base.cdw;
 778       cs->main.used_ib_space += cs->main.base.cdw * 4;
 779
 780       if (cs->const_ib.ib_mapped) {
 781          cs->ib[IB_CONST].size = cs->const_ib.base.cdw;
 782          cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
 783       }
 784
 785       if (cs->const_preamble_ib.ib_mapped) {
 786          cs->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
 787          cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
 788       }
 789
 790       amdgpu_cs_do_submission(cs, fence);
 791
 792       /* Cleanup. */
 793       if (cs->request.resources)
 794          amdgpu_bo_list_destroy(cs->request.resources);
 795    }
 796
 797 cleanup:
 798    amdgpu_cs_context_cleanup(cs);
 799
 800    amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
 801    if (cs->const_ib.ib_mapped)
 802       amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
 803    if (cs->const_preamble_ib.ib_mapped)
 804       amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
 805                                  &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
 806
 807    ws->num_cs_flushes++;
 808 }
 809
 810 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
 811 {
 812    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 813
 814    amdgpu_destroy_cs_context(cs);
 815    p_atomic_dec(&cs->ctx->ws->num_cs);
 816    pb_reference(&cs->main.big_ib_buffer, NULL);
 817    pb_reference(&cs->const_ib.big_ib_buffer, NULL);
 818    pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
 819    FREE(cs);
 820 }
 821
 822 static boolean amdgpu_bo_is_referenced(struct radeon_winsys_cs *rcs,
 823                                        struct pb_buffer *_buf,
 824                                        enum radeon_bo_usage usage)
 825 {
 826    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 827    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
 828
 829    return amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo, usage);
 830 }
 831
 832 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
 833 {
 834    ws->base.ctx_create = amdgpu_ctx_create;
 835    ws->base.ctx_destroy = amdgpu_ctx_destroy;
 836    ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
 837    ws->base.cs_create = amdgpu_cs_create;
 838    ws->base.cs_add_const_ib = amdgpu_cs_add_const_ib;
 839    ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
 840    ws->base.cs_destroy = amdgpu_cs_destroy;
 841    ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
 842    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
 843    ws->base.cs_validate = amdgpu_cs_validate;
 844    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
 845    ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
 846    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
 847    ws->base.cs_flush = amdgpu_cs_flush;
 848    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;
 849    ws->base.cs_sync_flush = amdgpu_cs_sync_flush;
 850    ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;
 851    ws->base.fence_reference = amdgpu_fence_reference;
 852 }