2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
35 #include "amdgpu_bo.h"
36 #include "util/u_memory.h"
39 struct amdgpu_winsys
*ws
;
40 amdgpu_context_handle ctx
;
41 amdgpu_bo_handle user_fence_bo
;
42 uint64_t *user_fence_cpu_address_base
;
46 struct amdgpu_cs_buffer
{
47 struct amdgpu_winsys_bo
*bo
;
48 uint64_t priority_usage
;
49 enum radeon_bo_usage usage
;
50 enum radeon_bo_domain domains
;
54 struct radeon_winsys_cs base
;
56 /* A buffer out of which new IBs are allocated. */
57 struct pb_buffer
*big_ib_buffer
;
59 unsigned used_ib_space
;
63 IB_CONST_PREAMBLE
= 0,
64 IB_CONST
= 1, /* the const IB must be first */
69 struct amdgpu_cs_context
{
70 struct amdgpu_cs_request request
;
71 struct amdgpu_cs_ib_info ib
[IB_NUM
];
74 unsigned max_num_buffers
;
76 amdgpu_bo_handle
*handles
;
78 struct amdgpu_cs_buffer
*buffers
;
80 int buffer_indices_hashlist
[4096];
85 unsigned max_dependencies
;
87 struct pipe_fence_handle
*fence
;
91 struct amdgpu_ib main
; /* must be first because this is inherited */
92 struct amdgpu_ib const_ib
; /* optional constant engine IB */
93 struct amdgpu_ib const_preamble_ib
;
94 struct amdgpu_ctx
*ctx
;
95 enum ring_type ring_type
;
97 /* We flip between these two CS. While one is being consumed
98 * by the kernel in another thread, the other one is being filled
99 * by the pipe driver. */
100 struct amdgpu_cs_context csc1
;
101 struct amdgpu_cs_context csc2
;
102 /* The currently-used CS. */
103 struct amdgpu_cs_context
*csc
;
104 /* The CS being currently-owned by the other thread. */
105 struct amdgpu_cs_context
*cst
;
108 void (*flush_cs
)(void *ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
111 pipe_semaphore flush_completed
;
114 struct amdgpu_fence
{
115 struct pipe_reference reference
;
117 struct amdgpu_ctx
*ctx
; /* submission context */
118 struct amdgpu_cs_fence fence
;
119 uint64_t *user_fence_cpu_address
;
121 /* If the fence is unknown due to an IB still being submitted
122 * in the other thread. */
123 volatile int submission_in_progress
; /* bool (int for atomicity) */
124 volatile int signalled
; /* bool (int for atomicity) */
127 static inline void amdgpu_ctx_unref(struct amdgpu_ctx
*ctx
)
129 if (p_atomic_dec_zero(&ctx
->refcount
)) {
130 amdgpu_cs_ctx_free(ctx
->ctx
);
131 amdgpu_bo_free(ctx
->user_fence_bo
);
136 static inline void amdgpu_fence_reference(struct pipe_fence_handle
**dst
,
137 struct pipe_fence_handle
*src
)
139 struct amdgpu_fence
**rdst
= (struct amdgpu_fence
**)dst
;
140 struct amdgpu_fence
*rsrc
= (struct amdgpu_fence
*)src
;
142 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
143 amdgpu_ctx_unref((*rdst
)->ctx
);
149 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
);
151 static inline struct amdgpu_cs
*
152 amdgpu_cs(struct radeon_winsys_cs
*base
)
154 return (struct amdgpu_cs
*)base
;
157 static inline boolean
158 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs
*cs
,
159 struct amdgpu_winsys_bo
*bo
)
161 int num_refs
= bo
->num_cs_references
;
162 return num_refs
== bo
->ws
->num_cs
||
163 (num_refs
&& amdgpu_lookup_buffer(cs
->csc
, bo
) != -1);
166 static inline boolean
167 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs
*cs
,
168 struct amdgpu_winsys_bo
*bo
,
169 enum radeon_bo_usage usage
)
173 if (!bo
->num_cs_references
)
176 index
= amdgpu_lookup_buffer(cs
->csc
, bo
);
180 return (cs
->csc
->buffers
[index
].usage
& usage
) != 0;
183 static inline boolean
184 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo
*bo
)
186 return bo
->num_cs_references
!= 0;
189 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
191 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
);
192 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
);
193 void amdgpu_cs_submit_ib(struct amdgpu_cs
*cs
);