src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_CS_H
  33 #define AMDGPU_CS_H
  34
  35 #include "amdgpu_bo.h"
  36 #include "util/u_memory.h"
  37
  38 struct amdgpu_ctx {
  39    struct amdgpu_winsys *ws;
  40    amdgpu_context_handle ctx;
  41    amdgpu_bo_handle user_fence_bo;
  42    uint64_t *user_fence_cpu_address_base;
  43    int refcount;
  44 };
  45
  46 struct amdgpu_cs_buffer {
  47    struct amdgpu_winsys_bo *bo;
  48    uint64_t priority_usage;
  49    enum radeon_bo_usage usage;
  50    enum radeon_bo_domain domains;
  51 };
  52
  53 struct amdgpu_ib {
  54    struct radeon_winsys_cs base;
  55
  56    /* A buffer out of which new IBs are allocated. */
  57    struct pb_buffer        *big_ib_buffer;
  58    uint8_t                 *ib_mapped;
  59    unsigned                used_ib_space;
  60 };
  61
  62 enum {
  63    IB_CONST_PREAMBLE = 0,
  64    IB_CONST = 1, /* the const IB must be first */
  65    IB_MAIN = 2,
  66    IB_NUM
  67 };
  68
  69 struct amdgpu_cs {
  70    struct amdgpu_ib main; /* must be first because this is inherited */
  71    struct amdgpu_ib const_ib; /* optional constant engine IB */
  72    struct amdgpu_ib const_preamble_ib;
  73    struct amdgpu_ctx *ctx;
  74
  75    /* Flush CS. */
  76    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
  77    void *flush_data;
  78
  79    /* amdgpu_cs_submit parameters */
  80    enum ring_type              ring_type;
  81    struct amdgpu_cs_request    request;
  82    struct amdgpu_cs_ib_info    ib[IB_NUM];
  83
  84    /* Buffers. */
  85    unsigned                    max_num_buffers;
  86    unsigned                    num_buffers;
  87    amdgpu_bo_handle            *handles;
  88    uint8_t                     *flags;
  89    struct amdgpu_cs_buffer     *buffers;
  90
  91    int                         buffer_indices_hashlist[4096];
  92
  93    uint64_t                    used_vram;
  94    uint64_t                    used_gart;
  95
  96    unsigned                    max_dependencies;
  97 };
  98
  99 struct amdgpu_fence {
 100    struct pipe_reference reference;
 101
 102    struct amdgpu_ctx *ctx;  /* submission context */
 103    struct amdgpu_cs_fence fence;
 104    uint64_t *user_fence_cpu_address;
 105
 106    volatile int signalled;              /* bool (int for atomicity) */
 107 };
 108
 109 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
 110 {
 111    if (p_atomic_dec_zero(&ctx->refcount)) {
 112       amdgpu_cs_ctx_free(ctx->ctx);
 113       amdgpu_bo_free(ctx->user_fence_bo);
 114       FREE(ctx);
 115    }
 116 }
 117
 118 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 119                                           struct pipe_fence_handle *src)
 120 {
 121    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 122    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 123
 124    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 125       amdgpu_ctx_unref((*rdst)->ctx);
 126       FREE(*rdst);
 127    }
 128    *rdst = rsrc;
 129 }
 130
 131 int amdgpu_lookup_buffer(struct amdgpu_cs *csc, struct amdgpu_winsys_bo *bo);
 132
 133 static inline struct amdgpu_cs *
 134 amdgpu_cs(struct radeon_winsys_cs *base)
 135 {
 136    return (struct amdgpu_cs*)base;
 137 }
 138
 139 static inline boolean
 140 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 141                               struct amdgpu_winsys_bo *bo)
 142 {
 143    int num_refs = bo->num_cs_references;
 144    return num_refs == bo->ws->num_cs ||
 145          (num_refs && amdgpu_lookup_buffer(cs, bo) != -1);
 146 }
 147
 148 static inline boolean
 149 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 150                                          struct amdgpu_winsys_bo *bo,
 151                                          enum radeon_bo_usage usage)
 152 {
 153    int index;
 154
 155    if (!bo->num_cs_references)
 156       return FALSE;
 157
 158    index = amdgpu_lookup_buffer(cs, bo);
 159    if (index == -1)
 160       return FALSE;
 161
 162    return (cs->buffers[index].usage & usage) != 0;
 163 }
 164
 165 static inline boolean
 166 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 167 {
 168    return bo->num_cs_references != 0;
 169 }
 170
 171 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 172                        bool absolute);
 173 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 174
 175 #endif