src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_CS_H
  33 #define AMDGPU_CS_H
  34
  35 #include "amdgpu_bo.h"
  36 #include "util/u_memory.h"
  37
  38 struct amdgpu_ctx {
  39    struct amdgpu_winsys *ws;
  40    amdgpu_context_handle ctx;
  41    amdgpu_bo_handle user_fence_bo;
  42    uint64_t *user_fence_cpu_address_base;
  43    int refcount;
  44    unsigned initial_num_total_rejected_cs;
  45    unsigned num_rejected_cs;
  46 };
  47
  48 struct amdgpu_cs_buffer {
  49    struct amdgpu_winsys_bo *bo;
  50    union {
  51       struct {
  52          uint64_t priority_usage;
  53       } real;
  54       struct {
  55          uint32_t real_idx; /* index of underlying real BO */
  56       } slab;
  57    } u;
  58    enum radeon_bo_usage usage;
  59 };
  60
  61 enum ib_type {
  62    IB_MAIN,
  63    IB_NUM,
  64 };
  65
  66 struct amdgpu_ib {
  67    struct radeon_winsys_cs base;
  68
  69    /* A buffer out of which new IBs are allocated. */
  70    struct pb_buffer        *big_ib_buffer;
  71    uint8_t                 *ib_mapped;
  72    unsigned                used_ib_space;
  73    unsigned                max_ib_size;
  74    uint32_t                *ptr_ib_size;
  75    enum ib_type            ib_type;
  76 };
  77
  78 struct amdgpu_cs_context {
  79    struct amdgpu_cs_request    request;
  80    struct amdgpu_cs_ib_info    ib[IB_NUM];
  81
  82    /* Buffers. */
  83    unsigned                    max_real_buffers;
  84    unsigned                    num_real_buffers;
  85    struct amdgpu_cs_buffer     *real_buffers;
  86
  87    unsigned                    max_real_submit;
  88    amdgpu_bo_handle            *handles;
  89    uint8_t                     *flags;
  90
  91    unsigned                    num_slab_buffers;
  92    unsigned                    max_slab_buffers;
  93    struct amdgpu_cs_buffer     *slab_buffers;
  94
  95    unsigned                    num_sparse_buffers;
  96    unsigned                    max_sparse_buffers;
  97    struct amdgpu_cs_buffer     *sparse_buffers;
  98
  99    int                         buffer_indices_hashlist[4096];
 100
 101    struct amdgpu_winsys_bo     *last_added_bo;
 102    unsigned                    last_added_bo_index;
 103    unsigned                    last_added_bo_usage;
 104    uint64_t                    last_added_bo_priority_usage;
 105
 106    struct pipe_fence_handle    **fence_dependencies;
 107    unsigned                    num_fence_dependencies;
 108    unsigned                    max_fence_dependencies;
 109
 110    struct pipe_fence_handle    *fence;
 111
 112    /* the error returned from cs_flush for non-async submissions */
 113    int                         error_code;
 114 };
 115
 116 struct amdgpu_cs {
 117    struct amdgpu_ib main; /* must be first because this is inherited */
 118    struct amdgpu_ctx *ctx;
 119    enum ring_type ring_type;
 120
 121    /* We flip between these two CS. While one is being consumed
 122     * by the kernel in another thread, the other one is being filled
 123     * by the pipe driver. */
 124    struct amdgpu_cs_context csc1;
 125    struct amdgpu_cs_context csc2;
 126    /* The currently-used CS. */
 127    struct amdgpu_cs_context *csc;
 128    /* The CS being currently-owned by the other thread. */
 129    struct amdgpu_cs_context *cst;
 130
 131    /* Flush CS. */
 132    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
 133    void *flush_data;
 134
 135    struct util_queue_fence flush_completed;
 136    struct pipe_fence_handle *next_fence;
 137 };
 138
 139 struct amdgpu_fence {
 140    struct pipe_reference reference;
 141
 142    struct amdgpu_ctx *ctx;  /* submission context */
 143    struct amdgpu_cs_fence fence;
 144    uint64_t *user_fence_cpu_address;
 145
 146    /* If the fence is unknown due to an IB still being submitted
 147     * in the other thread. */
 148    volatile int submission_in_progress; /* bool (int for atomicity) */
 149    volatile int signalled;              /* bool (int for atomicity) */
 150 };
 151
 152 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
 153 {
 154    if (p_atomic_dec_zero(&ctx->refcount)) {
 155       amdgpu_cs_ctx_free(ctx->ctx);
 156       amdgpu_bo_free(ctx->user_fence_bo);
 157       FREE(ctx);
 158    }
 159 }
 160
 161 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 162                                           struct pipe_fence_handle *src)
 163 {
 164    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 165    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 166
 167    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 168       amdgpu_ctx_unref((*rdst)->ctx);
 169       FREE(*rdst);
 170    }
 171    *rdst = rsrc;
 172 }
 173
 174 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
 175
 176 static inline struct amdgpu_ib *
 177 amdgpu_ib(struct radeon_winsys_cs *base)
 178 {
 179    return (struct amdgpu_ib *)base;
 180 }
 181
 182 static inline struct amdgpu_cs *
 183 amdgpu_cs(struct radeon_winsys_cs *base)
 184 {
 185    assert(amdgpu_ib(base)->ib_type == IB_MAIN);
 186    return (struct amdgpu_cs*)base;
 187 }
 188
 189 #define get_container(member_ptr, container_type, container_member) \
 190    (container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
 191
 192 static inline struct amdgpu_cs *
 193 amdgpu_cs_from_ib(struct amdgpu_ib *ib)
 194 {
 195    switch (ib->ib_type) {
 196    case IB_MAIN:
 197       return get_container(ib, struct amdgpu_cs, main);
 198    default:
 199       unreachable("bad ib_type");
 200    }
 201 }
 202
 203 static inline bool
 204 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 205                               struct amdgpu_winsys_bo *bo)
 206 {
 207    int num_refs = bo->num_cs_references;
 208    return num_refs == bo->ws->num_cs ||
 209          (num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1);
 210 }
 211
 212 static inline bool
 213 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 214                                          struct amdgpu_winsys_bo *bo,
 215                                          enum radeon_bo_usage usage)
 216 {
 217    int index;
 218    struct amdgpu_cs_buffer *buffer;
 219
 220    if (!bo->num_cs_references)
 221       return false;
 222
 223    index = amdgpu_lookup_buffer(cs->csc, bo);
 224    if (index == -1)
 225       return false;
 226
 227    buffer = bo->bo ? &cs->csc->real_buffers[index] :
 228             bo->sparse ? &cs->csc->sparse_buffers[index] :
 229             &cs->csc->slab_buffers[index];
 230
 231    return (buffer->usage & usage) != 0;
 232 }
 233
 234 static inline bool
 235 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 236 {
 237    return bo->num_cs_references != 0;
 238 }
 239
 240 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 241                        bool absolute);
 242 void amdgpu_add_fences(struct amdgpu_winsys_bo *bo,
 243                        unsigned num_fences,
 244                        struct pipe_fence_handle **fences);
 245 void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
 246 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 247 void amdgpu_cs_submit_ib(void *job, int thread_index);
 248
 249 #endif