src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Marek Olšák <maraeo@gmail.com>
  30  */
  31
  32 #ifndef AMDGPU_CS_H
  33 #define AMDGPU_CS_H
  34
  35 #include "amdgpu_bo.h"
  36 #include "util/u_memory.h"
  37
  38 struct amdgpu_ctx {
  39    struct amdgpu_winsys *ws;
  40    amdgpu_context_handle ctx;
  41    amdgpu_bo_handle user_fence_bo;
  42    uint64_t *user_fence_cpu_address_base;
  43    int refcount;
  44 };
  45
  46 struct amdgpu_cs_buffer {
  47    struct amdgpu_winsys_bo *bo;
  48    uint64_t priority_usage;
  49    enum radeon_bo_usage usage;
  50    enum radeon_bo_domain domains;
  51 };
  52
  53
  54 struct amdgpu_cs {
  55    struct radeon_winsys_cs base;
  56    struct amdgpu_ctx *ctx;
  57
  58    /* Flush CS. */
  59    void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
  60    void *flush_data;
  61
  62    /* A buffer out of which new IBs are allocated. */
  63    struct pb_buffer *big_ib_buffer; /* for holding the reference */
  64    struct amdgpu_winsys_bo *big_ib_winsys_buffer;
  65    uint8_t *ib_mapped;
  66    unsigned used_ib_space;
  67
  68    /* amdgpu_cs_submit parameters */
  69    struct amdgpu_cs_request    request;
  70    struct amdgpu_cs_ib_info    ib;
  71
  72    /* Buffers. */
  73    unsigned                    max_num_buffers;
  74    unsigned                    num_buffers;
  75    amdgpu_bo_handle            *handles;
  76    uint8_t                     *flags;
  77    struct amdgpu_cs_buffer     *buffers;
  78
  79    int                         buffer_indices_hashlist[4096];
  80
  81    uint64_t                    used_vram;
  82    uint64_t                    used_gart;
  83
  84    unsigned                    max_dependencies;
  85 };
  86
  87 struct amdgpu_fence {
  88    struct pipe_reference reference;
  89
  90    struct amdgpu_ctx *ctx;  /* submission context */
  91    struct amdgpu_cs_fence fence;
  92    uint64_t *user_fence_cpu_address;
  93
  94    volatile int signalled;              /* bool (int for atomicity) */
  95 };
  96
  97 static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
  98 {
  99    if (p_atomic_dec_zero(&ctx->refcount)) {
 100       amdgpu_cs_ctx_free(ctx->ctx);
 101       amdgpu_bo_free(ctx->user_fence_bo);
 102       FREE(ctx);
 103    }
 104 }
 105
 106 static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 107                                           struct pipe_fence_handle *src)
 108 {
 109    struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
 110    struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
 111
 112    if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 113       amdgpu_ctx_unref((*rdst)->ctx);
 114       FREE(*rdst);
 115    }
 116    *rdst = rsrc;
 117 }
 118
 119 int amdgpu_lookup_buffer(struct amdgpu_cs *csc, struct amdgpu_winsys_bo *bo);
 120
 121 static inline struct amdgpu_cs *
 122 amdgpu_cs(struct radeon_winsys_cs *base)
 123 {
 124    return (struct amdgpu_cs*)base;
 125 }
 126
 127 static inline boolean
 128 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
 129                               struct amdgpu_winsys_bo *bo)
 130 {
 131    int num_refs = bo->num_cs_references;
 132    return num_refs == bo->ws->num_cs ||
 133          (num_refs && amdgpu_lookup_buffer(cs, bo) != -1);
 134 }
 135
 136 static inline boolean
 137 amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
 138                                          struct amdgpu_winsys_bo *bo,
 139                                          enum radeon_bo_usage usage)
 140 {
 141    int index;
 142
 143    if (!bo->num_cs_references)
 144       return FALSE;
 145
 146    index = amdgpu_lookup_buffer(cs, bo);
 147    if (index == -1)
 148       return FALSE;
 149
 150    return (cs->buffers[index].usage & usage) != 0;
 151 }
 152
 153 static inline boolean
 154 amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
 155 {
 156    return bo->num_cs_references != 0;
 157 }
 158
 159 bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
 160                        bool absolute);
 161 void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
 162
 163 #endif